2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
19 #include <linux/frame.h>
20 #include <linux/highmem.h>
21 #include <linux/hrtimer.h>
22 #include <linux/kernel.h>
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/mod_devicetable.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/tboot.h>
31 #include <linux/trace_events.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/kexec.h>
42 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/spec-ctrl.h>
47 #include <asm/virtext.h>
50 #include "capabilities.h"
55 #include "kvm_cache_regs.h"
67 MODULE_AUTHOR("Qumranet");
68 MODULE_LICENSE("GPL");
70 static const struct x86_cpu_id vmx_cpu_id
[] = {
71 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
74 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
76 bool __read_mostly enable_vpid
= 1;
77 module_param_named(vpid
, enable_vpid
, bool, 0444);
79 static bool __read_mostly enable_vnmi
= 1;
80 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
82 bool __read_mostly flexpriority_enabled
= 1;
83 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
85 bool __read_mostly enable_ept
= 1;
86 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
88 bool __read_mostly enable_unrestricted_guest
= 1;
89 module_param_named(unrestricted_guest
,
90 enable_unrestricted_guest
, bool, S_IRUGO
);
92 bool __read_mostly enable_ept_ad_bits
= 1;
93 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
95 static bool __read_mostly emulate_invalid_guest_state
= true;
96 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
98 static bool __read_mostly fasteoi
= 1;
99 module_param(fasteoi
, bool, S_IRUGO
);
101 static bool __read_mostly enable_apicv
= 1;
102 module_param(enable_apicv
, bool, S_IRUGO
);
104 static bool __read_mostly enable_shadow_vmcs
= 1;
105 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
107 * If nested=1, nested virtualization is supported, i.e., guests may use
108 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
109 * use VMX instructions.
111 static bool __read_mostly nested
= 1;
112 module_param(nested
, bool, S_IRUGO
);
114 static bool __read_mostly nested_early_check
= 0;
115 module_param(nested_early_check
, bool, S_IRUGO
);
117 static u64 __read_mostly host_xss
;
119 bool __read_mostly enable_pml
= 1;
120 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
122 #define MSR_BITMAP_MODE_X2APIC 1
123 #define MSR_BITMAP_MODE_X2APIC_APICV 2
125 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
128 static int __read_mostly cpu_preemption_timer_multi
;
129 static bool __read_mostly enable_preemption_timer
= 1;
131 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
134 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON \
137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS \
140 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
141 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 static unsigned int ple_gap
= KVM_DEFAULT_PLE_GAP
;
173 module_param(ple_gap
, uint
, 0444);
175 static unsigned int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
176 module_param(ple_window
, uint
, 0444);
178 /* Default doubles per-vcpu window every exit. */
179 static unsigned int ple_window_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
180 module_param(ple_window_grow
, uint
, 0444);
182 /* Default resets per-vcpu window every exit to ple_window. */
183 static unsigned int ple_window_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
184 module_param(ple_window_shrink
, uint
, 0444);
186 /* Default is to compute the maximum so we can never overflow. */
187 static unsigned int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
188 module_param(ple_window_max
, uint
, 0444);
190 extern const ulong vmx_early_consistency_check_return
;
192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush
);
193 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond
);
194 static DEFINE_MUTEX(vmx_l1d_flush_mutex
);
196 /* Storage for pre module init parameter parsing */
197 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param
= VMENTER_L1D_FLUSH_AUTO
;
199 static const struct {
202 } vmentry_l1d_param
[] = {
203 [VMENTER_L1D_FLUSH_AUTO
] = {"auto", true},
204 [VMENTER_L1D_FLUSH_NEVER
] = {"never", true},
205 [VMENTER_L1D_FLUSH_COND
] = {"cond", true},
206 [VMENTER_L1D_FLUSH_ALWAYS
] = {"always", true},
207 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = {"EPT disabled", false},
208 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = {"not required", false},
211 #define L1D_CACHE_ORDER 4
212 static void *vmx_l1d_flush_pages
;
214 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf
)
220 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_EPT_DISABLED
;
224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
)) {
227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, msr
);
228 if (msr
& ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
) {
229 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_NOT_REQUIRED
;
234 /* If set to auto use the default l1tf mitigation method */
235 if (l1tf
== VMENTER_L1D_FLUSH_AUTO
) {
236 switch (l1tf_mitigation
) {
237 case L1TF_MITIGATION_OFF
:
238 l1tf
= VMENTER_L1D_FLUSH_NEVER
;
240 case L1TF_MITIGATION_FLUSH_NOWARN
:
241 case L1TF_MITIGATION_FLUSH
:
242 case L1TF_MITIGATION_FLUSH_NOSMT
:
243 l1tf
= VMENTER_L1D_FLUSH_COND
;
245 case L1TF_MITIGATION_FULL
:
246 case L1TF_MITIGATION_FULL_FORCE
:
247 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
250 } else if (l1tf_mitigation
== L1TF_MITIGATION_FULL_FORCE
) {
251 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
254 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
&& !vmx_l1d_flush_pages
&&
255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
256 page
= alloc_pages(GFP_KERNEL
, L1D_CACHE_ORDER
);
259 vmx_l1d_flush_pages
= page_address(page
);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i
= 0; i
< 1u << L1D_CACHE_ORDER
; ++i
) {
267 memset(vmx_l1d_flush_pages
+ i
* PAGE_SIZE
, i
+ 1,
272 l1tf_vmx_mitigation
= l1tf
;
274 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
)
275 static_branch_enable(&vmx_l1d_should_flush
);
277 static_branch_disable(&vmx_l1d_should_flush
);
279 if (l1tf
== VMENTER_L1D_FLUSH_COND
)
280 static_branch_enable(&vmx_l1d_flush_cond
);
282 static_branch_disable(&vmx_l1d_flush_cond
);
286 static int vmentry_l1d_flush_parse(const char *s
)
291 for (i
= 0; i
< ARRAY_SIZE(vmentry_l1d_param
); i
++) {
292 if (vmentry_l1d_param
[i
].for_parse
&&
293 sysfs_streq(s
, vmentry_l1d_param
[i
].option
))
300 static int vmentry_l1d_flush_set(const char *s
, const struct kernel_param
*kp
)
304 l1tf
= vmentry_l1d_flush_parse(s
);
308 if (!boot_cpu_has(X86_BUG_L1TF
))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
) {
318 vmentry_l1d_flush_param
= l1tf
;
322 mutex_lock(&vmx_l1d_flush_mutex
);
323 ret
= vmx_setup_l1d_flush(l1tf
);
324 mutex_unlock(&vmx_l1d_flush_mutex
);
328 static int vmentry_l1d_flush_get(char *s
, const struct kernel_param
*kp
)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation
>= ARRAY_SIZE(vmentry_l1d_param
)))
331 return sprintf(s
, "???\n");
333 return sprintf(s
, "%s\n", vmentry_l1d_param
[l1tf_vmx_mitigation
].option
);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops
= {
337 .set
= vmentry_l1d_flush_set
,
338 .get
= vmentry_l1d_flush_get
,
340 module_param_cb(vmentry_l1d_flush
, &vmentry_l1d_flush_ops
, NULL
, 0644);
342 static u16 shadow_read_only_fields
[] = {
343 #define SHADOW_FIELD_RO(x) x,
344 #include "vmcs_shadow_fields.h"
346 static int max_shadow_read_only_fields
=
347 ARRAY_SIZE(shadow_read_only_fields
);
349 static u16 shadow_read_write_fields
[] = {
350 #define SHADOW_FIELD_RW(x) x,
351 #include "vmcs_shadow_fields.h"
353 static int max_shadow_read_write_fields
=
354 ARRAY_SIZE(shadow_read_write_fields
);
356 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
358 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
361 static inline struct vmcs12
*get_shadow_vmcs12(struct kvm_vcpu
*vcpu
)
363 return to_vmx(vcpu
)->nested
.cached_shadow_vmcs12
;
366 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
367 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
368 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
369 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
370 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
371 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
373 static __always_inline
void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
376 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
377 DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
379 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
380 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
382 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
385 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
386 * can find which vCPU should be waken up.
388 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
389 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
397 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
399 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
400 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
402 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
403 static DEFINE_SPINLOCK(vmx_vpid_lock
);
405 struct vmcs_config vmcs_config
;
406 struct vmx_capability vmx_capability
;
408 #define VMX_SEGMENT_FIELD(seg) \
409 [VCPU_SREG_##seg] = { \
410 .selector = GUEST_##seg##_SELECTOR, \
411 .base = GUEST_##seg##_BASE, \
412 .limit = GUEST_##seg##_LIMIT, \
413 .ar_bytes = GUEST_##seg##_AR_BYTES, \
416 static const struct kvm_vmx_segment_field
{
421 } kvm_vmx_segment_fields
[] = {
422 VMX_SEGMENT_FIELD(CS
),
423 VMX_SEGMENT_FIELD(DS
),
424 VMX_SEGMENT_FIELD(ES
),
425 VMX_SEGMENT_FIELD(FS
),
426 VMX_SEGMENT_FIELD(GS
),
427 VMX_SEGMENT_FIELD(SS
),
428 VMX_SEGMENT_FIELD(TR
),
429 VMX_SEGMENT_FIELD(LDTR
),
435 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
436 * away by decrementing the array size.
438 const u32 vmx_msr_index
[] = {
440 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
442 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
445 #if IS_ENABLED(CONFIG_HYPERV)
446 static bool __read_mostly enlightened_vmcs
= true;
447 module_param(enlightened_vmcs
, bool, 0444);
449 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
450 static void check_ept_pointer_match(struct kvm
*kvm
)
452 struct kvm_vcpu
*vcpu
;
453 u64 tmp_eptp
= INVALID_PAGE
;
456 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
457 if (!VALID_PAGE(tmp_eptp
)) {
458 tmp_eptp
= to_vmx(vcpu
)->ept_pointer
;
459 } else if (tmp_eptp
!= to_vmx(vcpu
)->ept_pointer
) {
460 to_kvm_vmx(kvm
)->ept_pointers_match
461 = EPT_POINTERS_MISMATCH
;
466 to_kvm_vmx(kvm
)->ept_pointers_match
= EPT_POINTERS_MATCH
;
469 static int vmx_hv_remote_flush_tlb(struct kvm
*kvm
)
471 struct kvm_vcpu
*vcpu
;
472 int ret
= -ENOTSUPP
, i
;
474 spin_lock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
476 if (to_kvm_vmx(kvm
)->ept_pointers_match
== EPT_POINTERS_CHECK
)
477 check_ept_pointer_match(kvm
);
480 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs the address of the
481 * base of EPT PML4 table, strip off EPT configuration information.
483 if (to_kvm_vmx(kvm
)->ept_pointers_match
!= EPT_POINTERS_MATCH
) {
484 kvm_for_each_vcpu(i
, vcpu
, kvm
)
485 ret
|= hyperv_flush_guest_mapping(
486 to_vmx(kvm_get_vcpu(kvm
, i
))->ept_pointer
& PAGE_MASK
);
488 ret
= hyperv_flush_guest_mapping(
489 to_vmx(kvm_get_vcpu(kvm
, 0))->ept_pointer
& PAGE_MASK
);
492 spin_unlock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
495 #endif /* IS_ENABLED(CONFIG_HYPERV) */
498 * Comment's format: document - errata name - stepping - processor name.
500 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
502 static u32 vmx_preemption_cpu_tfms
[] = {
503 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
505 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
506 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
507 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
509 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
511 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
512 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
514 * 320767.pdf - AAP86 - B1 -
515 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
518 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
520 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
522 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
524 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
525 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
526 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
530 static inline bool cpu_has_broken_vmx_preemption_timer(void)
532 u32 eax
= cpuid_eax(0x00000001), i
;
534 /* Clear the reserved bits */
535 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
536 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
537 if (eax
== vmx_preemption_cpu_tfms
[i
])
543 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
545 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
548 static inline bool report_flexpriority(void)
550 return flexpriority_enabled
;
553 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
555 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.msrs
.misc_low
);
559 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
560 * to modify any valid field of the VMCS, or are the VM-exit
561 * information fields read-only?
563 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu
*vcpu
)
565 return to_vmx(vcpu
)->nested
.msrs
.misc_low
&
566 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
;
569 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu
*vcpu
)
571 return to_vmx(vcpu
)->nested
.msrs
.misc_low
& VMX_MISC_ZERO_LEN_INS
;
574 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu
*vcpu
)
576 return to_vmx(vcpu
)->nested
.msrs
.procbased_ctls_high
&
577 CPU_BASED_MONITOR_TRAP_FLAG
;
580 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu
*vcpu
)
582 return to_vmx(vcpu
)->nested
.msrs
.secondary_ctls_high
&
583 SECONDARY_EXEC_SHADOW_VMCS
;
586 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
588 return vmcs12
->cpu_based_vm_exec_control
& bit
;
591 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
593 return (vmcs12
->cpu_based_vm_exec_control
&
594 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
595 (vmcs12
->secondary_vm_exec_control
& bit
);
598 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
600 return vmcs12
->pin_based_vm_exec_control
&
601 PIN_BASED_VMX_PREEMPTION_TIMER
;
604 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12
*vmcs12
)
606 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_NMI_EXITING
;
609 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
611 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
614 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
616 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
619 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
621 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
624 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
626 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
629 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
631 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
634 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
636 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
639 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
641 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
644 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
646 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
649 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
651 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
654 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
656 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
659 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
661 return nested_cpu_has_vmfunc(vmcs12
) &&
662 (vmcs12
->vm_function_control
&
663 VMX_VMFUNC_EPTP_SWITCHING
);
666 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12
*vmcs12
)
668 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
);
671 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12
*vmcs12
)
673 return vmcs12
->vm_exit_controls
&
674 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
677 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
679 unsigned long exit_qualification
);
681 static inline int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
685 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
686 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
691 struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
695 i
= __find_msr_index(vmx
, msr
);
697 return &vmx
->guest_msrs
[i
];
701 void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
703 vmcs_clear(loaded_vmcs
->vmcs
);
704 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
705 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
706 loaded_vmcs
->cpu
= -1;
707 loaded_vmcs
->launched
= 0;
710 #ifdef CONFIG_KEXEC_CORE
712 * This bitmap is used to indicate whether the vmclear
713 * operation is enabled on all cpus. All disabled by
716 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
718 static inline void crash_enable_local_vmclear(int cpu
)
720 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
723 static inline void crash_disable_local_vmclear(int cpu
)
725 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
728 static inline int crash_local_vmclear_enabled(int cpu
)
730 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
733 static void crash_vmclear_local_loaded_vmcss(void)
735 int cpu
= raw_smp_processor_id();
736 struct loaded_vmcs
*v
;
738 if (!crash_local_vmclear_enabled(cpu
))
741 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
742 loaded_vmcss_on_cpu_link
)
746 static inline void crash_enable_local_vmclear(int cpu
) { }
747 static inline void crash_disable_local_vmclear(int cpu
) { }
748 #endif /* CONFIG_KEXEC_CORE */
750 static void __loaded_vmcs_clear(void *arg
)
752 struct loaded_vmcs
*loaded_vmcs
= arg
;
753 int cpu
= raw_smp_processor_id();
755 if (loaded_vmcs
->cpu
!= cpu
)
756 return; /* vcpu migration can race with cpu offline */
757 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
758 per_cpu(current_vmcs
, cpu
) = NULL
;
759 crash_disable_local_vmclear(cpu
);
760 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
763 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
764 * is before setting loaded_vmcs->vcpu to -1 which is done in
765 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
766 * then adds the vmcs into percpu list before it is deleted.
770 loaded_vmcs_init(loaded_vmcs
);
771 crash_enable_local_vmclear(cpu
);
774 void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
776 int cpu
= loaded_vmcs
->cpu
;
779 smp_call_function_single(cpu
,
780 __loaded_vmcs_clear
, loaded_vmcs
, 1);
783 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
787 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
789 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
790 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
791 vmx
->segment_cache
.bitmask
= 0;
793 ret
= vmx
->segment_cache
.bitmask
& mask
;
794 vmx
->segment_cache
.bitmask
|= mask
;
798 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
800 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
802 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
803 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
807 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
809 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
811 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
812 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
816 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
818 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
820 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
821 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
825 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
827 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
829 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
830 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
834 void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
838 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
839 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
841 * Guest access to VMware backdoor ports could legitimately
842 * trigger #GP because of TSS I/O permission bitmap.
843 * We intercept those #GP and allow access to them anyway
846 if (enable_vmware_backdoor
)
847 eb
|= (1u << GP_VECTOR
);
848 if ((vcpu
->guest_debug
&
849 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
850 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
851 eb
|= 1u << BP_VECTOR
;
852 if (to_vmx(vcpu
)->rmode
.vm86_active
)
855 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
857 /* When we are running a nested L2 guest and L1 specified for it a
858 * certain exception bitmap, we must trap the same exceptions and pass
859 * them to L1. When running L2, we will only handle the exceptions
860 * specified above if L1 did not want them.
862 if (is_guest_mode(vcpu
))
863 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
865 vmcs_write32(EXCEPTION_BITMAP
, eb
);
869 * Check if MSR is intercepted for currently loaded MSR bitmap.
871 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
873 unsigned long *msr_bitmap
;
874 int f
= sizeof(unsigned long);
876 if (!cpu_has_vmx_msr_bitmap())
879 msr_bitmap
= to_vmx(vcpu
)->loaded_vmcs
->msr_bitmap
;
882 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
883 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
885 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
892 * Check if MSR is intercepted for L01 MSR bitmap.
894 static bool msr_write_intercepted_l01(struct kvm_vcpu
*vcpu
, u32 msr
)
896 unsigned long *msr_bitmap
;
897 int f
= sizeof(unsigned long);
899 if (!cpu_has_vmx_msr_bitmap())
902 msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
905 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
906 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
908 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
914 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
915 unsigned long entry
, unsigned long exit
)
917 vm_entry_controls_clearbit(vmx
, entry
);
918 vm_exit_controls_clearbit(vmx
, exit
);
921 static int find_msr(struct vmx_msrs
*m
, unsigned int msr
)
925 for (i
= 0; i
< m
->nr
; ++i
) {
926 if (m
->val
[i
].index
== msr
)
932 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
935 struct msr_autoload
*m
= &vmx
->msr_autoload
;
939 if (cpu_has_load_ia32_efer()) {
940 clear_atomic_switch_msr_special(vmx
,
941 VM_ENTRY_LOAD_IA32_EFER
,
942 VM_EXIT_LOAD_IA32_EFER
);
946 case MSR_CORE_PERF_GLOBAL_CTRL
:
947 if (cpu_has_load_perf_global_ctrl()) {
948 clear_atomic_switch_msr_special(vmx
,
949 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
950 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
955 i
= find_msr(&m
->guest
, msr
);
959 m
->guest
.val
[i
] = m
->guest
.val
[m
->guest
.nr
];
960 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
963 i
= find_msr(&m
->host
, msr
);
968 m
->host
.val
[i
] = m
->host
.val
[m
->host
.nr
];
969 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
972 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
973 unsigned long entry
, unsigned long exit
,
974 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
975 u64 guest_val
, u64 host_val
)
977 vmcs_write64(guest_val_vmcs
, guest_val
);
978 if (host_val_vmcs
!= HOST_IA32_EFER
)
979 vmcs_write64(host_val_vmcs
, host_val
);
980 vm_entry_controls_setbit(vmx
, entry
);
981 vm_exit_controls_setbit(vmx
, exit
);
984 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
985 u64 guest_val
, u64 host_val
, bool entry_only
)
988 struct msr_autoload
*m
= &vmx
->msr_autoload
;
992 if (cpu_has_load_ia32_efer()) {
993 add_atomic_switch_msr_special(vmx
,
994 VM_ENTRY_LOAD_IA32_EFER
,
995 VM_EXIT_LOAD_IA32_EFER
,
998 guest_val
, host_val
);
1002 case MSR_CORE_PERF_GLOBAL_CTRL
:
1003 if (cpu_has_load_perf_global_ctrl()) {
1004 add_atomic_switch_msr_special(vmx
,
1005 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1006 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1007 GUEST_IA32_PERF_GLOBAL_CTRL
,
1008 HOST_IA32_PERF_GLOBAL_CTRL
,
1009 guest_val
, host_val
);
1013 case MSR_IA32_PEBS_ENABLE
:
1014 /* PEBS needs a quiescent period after being disabled (to write
1015 * a record). Disabling PEBS through VMX MSR swapping doesn't
1016 * provide that period, so a CPU could write host's record into
1019 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1022 i
= find_msr(&m
->guest
, msr
);
1024 j
= find_msr(&m
->host
, msr
);
1026 if (i
== NR_AUTOLOAD_MSRS
|| j
== NR_AUTOLOAD_MSRS
) {
1027 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1028 "Can't add msr %x\n", msr
);
1033 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
1035 m
->guest
.val
[i
].index
= msr
;
1036 m
->guest
.val
[i
].value
= guest_val
;
1043 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
1045 m
->host
.val
[j
].index
= msr
;
1046 m
->host
.val
[j
].value
= host_val
;
1049 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1051 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1052 u64 ignore_bits
= 0;
1056 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1057 * host CPUID is more efficient than testing guest CPUID
1058 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1060 if (boot_cpu_has(X86_FEATURE_SMEP
))
1061 guest_efer
|= EFER_NX
;
1062 else if (!(guest_efer
& EFER_NX
))
1063 ignore_bits
|= EFER_NX
;
1067 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1069 ignore_bits
|= EFER_SCE
;
1070 #ifdef CONFIG_X86_64
1071 ignore_bits
|= EFER_LMA
| EFER_LME
;
1072 /* SCE is meaningful only in long mode on Intel */
1073 if (guest_efer
& EFER_LMA
)
1074 ignore_bits
&= ~(u64
)EFER_SCE
;
1078 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1079 * On CPUs that support "load IA32_EFER", always switch EFER
1080 * atomically, since it's faster than switching it manually.
1082 if (cpu_has_load_ia32_efer() ||
1083 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1084 if (!(guest_efer
& EFER_LMA
))
1085 guest_efer
&= ~EFER_LME
;
1086 if (guest_efer
!= host_efer
)
1087 add_atomic_switch_msr(vmx
, MSR_EFER
,
1088 guest_efer
, host_efer
, false);
1090 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1093 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1095 guest_efer
&= ~ignore_bits
;
1096 guest_efer
|= host_efer
& ignore_bits
;
1098 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1099 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1105 #ifdef CONFIG_X86_32
1107 * On 32-bit kernels, VM exits still load the FS and GS bases from the
1108 * VMCS rather than the segment table. KVM uses this helper to figure
1109 * out the current bases to poke them into the VMCS before entry.
1111 static unsigned long segment_base(u16 selector
)
1113 struct desc_struct
*table
;
1116 if (!(selector
& ~SEGMENT_RPL_MASK
))
1119 table
= get_current_gdt_ro();
1121 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
1122 u16 ldt_selector
= kvm_read_ldt();
1124 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
1127 table
= (struct desc_struct
*)segment_base(ldt_selector
);
1129 v
= get_desc_base(&table
[selector
>> 3]);
1134 void vmx_prepare_switch_to_guest(struct kvm_vcpu
*vcpu
)
1136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1137 struct vmcs_host_state
*host_state
;
1138 #ifdef CONFIG_X86_64
1139 int cpu
= raw_smp_processor_id();
1141 unsigned long fs_base
, gs_base
;
1145 vmx
->req_immediate_exit
= false;
1148 * Note that guest MSRs to be saved/restored can also be changed
1149 * when guest state is loaded. This happens when guest transitions
1150 * to/from long-mode by setting MSR_EFER.LMA.
1152 if (!vmx
->loaded_cpu_state
|| vmx
->guest_msrs_dirty
) {
1153 vmx
->guest_msrs_dirty
= false;
1154 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1155 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1156 vmx
->guest_msrs
[i
].data
,
1157 vmx
->guest_msrs
[i
].mask
);
1161 if (vmx
->loaded_cpu_state
)
1164 vmx
->loaded_cpu_state
= vmx
->loaded_vmcs
;
1165 host_state
= &vmx
->loaded_cpu_state
->host_state
;
1168 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1169 * allow segment selectors with cpl > 0 or ti == 1.
1171 host_state
->ldt_sel
= kvm_read_ldt();
1173 #ifdef CONFIG_X86_64
1174 savesegment(ds
, host_state
->ds_sel
);
1175 savesegment(es
, host_state
->es_sel
);
1177 gs_base
= cpu_kernelmode_gs_base(cpu
);
1178 if (likely(is_64bit_mm(current
->mm
))) {
1179 save_fsgs_for_kvm();
1180 fs_sel
= current
->thread
.fsindex
;
1181 gs_sel
= current
->thread
.gsindex
;
1182 fs_base
= current
->thread
.fsbase
;
1183 vmx
->msr_host_kernel_gs_base
= current
->thread
.gsbase
;
1185 savesegment(fs
, fs_sel
);
1186 savesegment(gs
, gs_sel
);
1187 fs_base
= read_msr(MSR_FS_BASE
);
1188 vmx
->msr_host_kernel_gs_base
= read_msr(MSR_KERNEL_GS_BASE
);
1191 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1193 savesegment(fs
, fs_sel
);
1194 savesegment(gs
, gs_sel
);
1195 fs_base
= segment_base(fs_sel
);
1196 gs_base
= segment_base(gs_sel
);
1199 if (unlikely(fs_sel
!= host_state
->fs_sel
)) {
1201 vmcs_write16(HOST_FS_SELECTOR
, fs_sel
);
1203 vmcs_write16(HOST_FS_SELECTOR
, 0);
1204 host_state
->fs_sel
= fs_sel
;
1206 if (unlikely(gs_sel
!= host_state
->gs_sel
)) {
1208 vmcs_write16(HOST_GS_SELECTOR
, gs_sel
);
1210 vmcs_write16(HOST_GS_SELECTOR
, 0);
1211 host_state
->gs_sel
= gs_sel
;
1213 if (unlikely(fs_base
!= host_state
->fs_base
)) {
1214 vmcs_writel(HOST_FS_BASE
, fs_base
);
1215 host_state
->fs_base
= fs_base
;
1217 if (unlikely(gs_base
!= host_state
->gs_base
)) {
1218 vmcs_writel(HOST_GS_BASE
, gs_base
);
1219 host_state
->gs_base
= gs_base
;
1223 static void vmx_prepare_switch_to_host(struct vcpu_vmx
*vmx
)
1225 struct vmcs_host_state
*host_state
;
1227 if (!vmx
->loaded_cpu_state
)
1230 WARN_ON_ONCE(vmx
->loaded_cpu_state
!= vmx
->loaded_vmcs
);
1231 host_state
= &vmx
->loaded_cpu_state
->host_state
;
1233 ++vmx
->vcpu
.stat
.host_state_reload
;
1234 vmx
->loaded_cpu_state
= NULL
;
1236 #ifdef CONFIG_X86_64
1237 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1239 if (host_state
->ldt_sel
|| (host_state
->gs_sel
& 7)) {
1240 kvm_load_ldt(host_state
->ldt_sel
);
1241 #ifdef CONFIG_X86_64
1242 load_gs_index(host_state
->gs_sel
);
1244 loadsegment(gs
, host_state
->gs_sel
);
1247 if (host_state
->fs_sel
& 7)
1248 loadsegment(fs
, host_state
->fs_sel
);
1249 #ifdef CONFIG_X86_64
1250 if (unlikely(host_state
->ds_sel
| host_state
->es_sel
)) {
1251 loadsegment(ds
, host_state
->ds_sel
);
1252 loadsegment(es
, host_state
->es_sel
);
1255 invalidate_tss_limit();
1256 #ifdef CONFIG_X86_64
1257 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1259 load_fixmap_gdt(raw_smp_processor_id());
1262 #ifdef CONFIG_X86_64
1263 static u64
vmx_read_guest_kernel_gs_base(struct vcpu_vmx
*vmx
)
1266 if (vmx
->loaded_cpu_state
)
1267 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1269 return vmx
->msr_guest_kernel_gs_base
;
1272 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx
*vmx
, u64 data
)
1275 if (vmx
->loaded_cpu_state
)
1276 wrmsrl(MSR_KERNEL_GS_BASE
, data
);
1278 vmx
->msr_guest_kernel_gs_base
= data
;
1282 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
1284 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
1285 struct pi_desc old
, new;
1289 * In case of hot-plug or hot-unplug, we may have to undo
1290 * vmx_vcpu_pi_put even if there is no assigned device. And we
1291 * always keep PI.NDST up to date for simplicity: it makes the
1292 * code easier, and CPU migration is not a fast path.
1294 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
1298 * First handle the simple case where no cmpxchg is necessary; just
1299 * allow posting non-urgent interrupts.
1301 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1302 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
1303 * expects the VCPU to be on the blocked_vcpu_list that matches
1306 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
1308 pi_clear_sn(pi_desc
);
1312 /* The full case. */
1314 old
.control
= new.control
= pi_desc
->control
;
1316 dest
= cpu_physical_id(cpu
);
1318 if (x2apic_enabled())
1321 new.ndst
= (dest
<< 8) & 0xFF00;
1324 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
1325 new.control
) != old
.control
);
1329 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1330 * vcpu mutex is already taken.
1332 void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1335 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
1337 if (!already_loaded
) {
1338 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1339 local_irq_disable();
1340 crash_disable_local_vmclear(cpu
);
1343 * Read loaded_vmcs->cpu should be before fetching
1344 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1345 * See the comments in __loaded_vmcs_clear().
1349 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1350 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1351 crash_enable_local_vmclear(cpu
);
1355 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1356 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1357 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1358 indirect_branch_prediction_barrier();
1361 if (!already_loaded
) {
1362 void *gdt
= get_current_gdt_ro();
1363 unsigned long sysenter_esp
;
1365 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1368 * Linux uses per-cpu TSS and GDT, so set these when switching
1369 * processors. See 22.2.4.
1371 vmcs_writel(HOST_TR_BASE
,
1372 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1373 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
1376 * VM exits change the host TR limit to 0x67 after a VM
1377 * exit. This is okay, since 0x67 covers everything except
1378 * the IO bitmap and have have code to handle the IO bitmap
1379 * being lost after a VM exit.
1381 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
1383 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1384 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1386 vmx
->loaded_vmcs
->cpu
= cpu
;
1389 /* Setup TSC multiplier */
1390 if (kvm_has_tsc_control
&&
1391 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
1392 decache_tsc_multiplier(vmx
);
1394 vmx_vcpu_pi_load(vcpu
, cpu
);
1395 vmx
->host_pkru
= read_pkru();
1396 vmx
->host_debugctlmsr
= get_debugctlmsr();
1399 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
1401 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
1403 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
1404 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
1405 !kvm_vcpu_apicv_active(vcpu
))
1408 /* Set SN when the vCPU is preempted */
1409 if (vcpu
->preempted
)
1413 void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1415 vmx_vcpu_pi_put(vcpu
);
1417 vmx_prepare_switch_to_host(to_vmx(vcpu
));
1420 static bool emulation_required(struct kvm_vcpu
*vcpu
)
1422 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
1425 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1428 * Return the cr0 value that a nested guest would read. This is a combination
1429 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1430 * its hypervisor (cr0_read_shadow).
1432 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1434 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1435 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1437 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1439 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1440 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1443 unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1445 unsigned long rflags
, save_rflags
;
1447 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1448 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1449 rflags
= vmcs_readl(GUEST_RFLAGS
);
1450 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1451 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1452 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1453 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1455 to_vmx(vcpu
)->rflags
= rflags
;
1457 return to_vmx(vcpu
)->rflags
;
1460 void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1462 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
1464 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1465 to_vmx(vcpu
)->rflags
= rflags
;
1466 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1467 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1468 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1470 vmcs_writel(GUEST_RFLAGS
, rflags
);
1472 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
1473 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
1476 u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1478 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1481 if (interruptibility
& GUEST_INTR_STATE_STI
)
1482 ret
|= KVM_X86_SHADOW_INT_STI
;
1483 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1484 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1489 void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1491 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1492 u32 interruptibility
= interruptibility_old
;
1494 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1496 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1497 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1498 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1499 interruptibility
|= GUEST_INTR_STATE_STI
;
1501 if ((interruptibility
!= interruptibility_old
))
1502 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1505 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1509 rip
= kvm_rip_read(vcpu
);
1510 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1511 kvm_rip_write(vcpu
, rip
);
1513 /* skipping an emulated instruction also counts */
1514 vmx_set_interrupt_shadow(vcpu
, 0);
1517 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
1518 unsigned long exit_qual
)
1520 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1521 unsigned int nr
= vcpu
->arch
.exception
.nr
;
1522 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1524 if (vcpu
->arch
.exception
.has_error_code
) {
1525 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
1526 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1529 if (kvm_exception_is_soft(nr
))
1530 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1532 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1534 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
1535 vmx_get_nmi_mask(vcpu
))
1536 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
1538 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
1542 * KVM wants to inject page-faults which it got to the guest. This function
1543 * checks whether in a nested guest, we need to inject them to L1 or L2.
1545 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
1547 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1548 unsigned int nr
= vcpu
->arch
.exception
.nr
;
1549 bool has_payload
= vcpu
->arch
.exception
.has_payload
;
1550 unsigned long payload
= vcpu
->arch
.exception
.payload
;
1552 if (nr
== PF_VECTOR
) {
1553 if (vcpu
->arch
.exception
.nested_apf
) {
1554 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
1557 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
1558 vcpu
->arch
.exception
.error_code
)) {
1559 *exit_qual
= has_payload
? payload
: vcpu
->arch
.cr2
;
1562 } else if (vmcs12
->exception_bitmap
& (1u << nr
)) {
1563 if (nr
== DB_VECTOR
) {
1565 payload
= vcpu
->arch
.dr6
;
1566 payload
&= ~(DR6_FIXED_1
| DR6_BT
);
1569 *exit_qual
= payload
;
1578 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1581 * Ensure that we clear the HLT state in the VMCS. We don't need to
1582 * explicitly skip the instruction because if the HLT state is set,
1583 * then the instruction is already executing and RIP has already been
1586 if (kvm_hlt_in_guest(vcpu
->kvm
) &&
1587 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1588 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1591 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
1593 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1594 unsigned nr
= vcpu
->arch
.exception
.nr
;
1595 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
1596 u32 error_code
= vcpu
->arch
.exception
.error_code
;
1597 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1599 kvm_deliver_exception_payload(vcpu
);
1601 if (has_error_code
) {
1602 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1603 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1606 if (vmx
->rmode
.vm86_active
) {
1608 if (kvm_exception_is_soft(nr
))
1609 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1610 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1611 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1615 WARN_ON_ONCE(vmx
->emulation_required
);
1617 if (kvm_exception_is_soft(nr
)) {
1618 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1619 vmx
->vcpu
.arch
.event_exit_inst_len
);
1620 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1622 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1624 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1626 vmx_clear_hlt(vcpu
);
1629 static bool vmx_rdtscp_supported(void)
1631 return cpu_has_vmx_rdtscp();
1634 static bool vmx_invpcid_supported(void)
1636 return cpu_has_vmx_invpcid();
1640 * Swap MSR entry in host/guest MSR entry array.
1642 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1644 struct shared_msr_entry tmp
;
1646 tmp
= vmx
->guest_msrs
[to
];
1647 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1648 vmx
->guest_msrs
[from
] = tmp
;
1652 * Set up the vmcs to automatically save and restore system
1653 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1654 * mode, as fiddling with msrs is very expensive.
1656 static void setup_msrs(struct vcpu_vmx
*vmx
)
1658 int save_nmsrs
, index
;
1661 #ifdef CONFIG_X86_64
1662 if (is_long_mode(&vmx
->vcpu
)) {
1663 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1665 move_msr_up(vmx
, index
, save_nmsrs
++);
1666 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1668 move_msr_up(vmx
, index
, save_nmsrs
++);
1669 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1671 move_msr_up(vmx
, index
, save_nmsrs
++);
1672 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1673 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
1674 move_msr_up(vmx
, index
, save_nmsrs
++);
1676 * MSR_STAR is only needed on long mode guests, and only
1677 * if efer.sce is enabled.
1679 index
= __find_msr_index(vmx
, MSR_STAR
);
1680 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1681 move_msr_up(vmx
, index
, save_nmsrs
++);
1684 index
= __find_msr_index(vmx
, MSR_EFER
);
1685 if (index
>= 0 && update_transition_efer(vmx
, index
))
1686 move_msr_up(vmx
, index
, save_nmsrs
++);
1688 vmx
->save_nmsrs
= save_nmsrs
;
1689 vmx
->guest_msrs_dirty
= true;
1691 if (cpu_has_vmx_msr_bitmap())
1692 vmx_update_msr_bitmap(&vmx
->vcpu
);
1695 static u64
vmx_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
1697 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1699 if (is_guest_mode(vcpu
) &&
1700 (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
))
1701 return vcpu
->arch
.tsc_offset
- vmcs12
->tsc_offset
;
1703 return vcpu
->arch
.tsc_offset
;
1706 static u64
vmx_write_l1_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1708 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1709 u64 g_tsc_offset
= 0;
1712 * We're here if L1 chose not to trap WRMSR to TSC. According
1713 * to the spec, this should set L1's TSC; The offset that L1
1714 * set for L2 remains unchanged, and still needs to be added
1715 * to the newly set TSC to get L2's TSC.
1717 if (is_guest_mode(vcpu
) &&
1718 (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
))
1719 g_tsc_offset
= vmcs12
->tsc_offset
;
1721 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1722 vcpu
->arch
.tsc_offset
- g_tsc_offset
,
1724 vmcs_write64(TSC_OFFSET
, offset
+ g_tsc_offset
);
1725 return offset
+ g_tsc_offset
;
1729 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1730 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1731 * all guests if the "nested" module option is off, and can also be disabled
1732 * for a single guest by disabling its VMX cpuid bit.
1734 bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1736 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
1740 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1741 * returned for the various VMX controls MSRs when nested VMX is enabled.
1742 * The same values should also be used to verify that vmcs12 control fields are
1743 * valid during nested entry from L1 to L2.
1744 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1745 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1746 * bit in the high half is on if the corresponding bit in the control field
1747 * may be on. See also vmx_control_verify().
1749 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs
*msrs
,
1750 u32 ept_caps
, bool apicv
)
1753 * Note that as a general rule, the high half of the MSRs (bits in
1754 * the control fields which may be 1) should be initialized by the
1755 * intersection of the underlying hardware's MSR (i.e., features which
1756 * can be supported) and the list of features we want to expose -
1757 * because they are known to be properly supported in our code.
1758 * Also, usually, the low half of the MSRs (bits which must be 1) can
1759 * be set to 0, meaning that L1 may turn off any of these bits. The
1760 * reason is that if one of these bits is necessary, it will appear
1761 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1762 * fields of vmcs01 and vmcs02, will turn these bits off - and
1763 * nested_vmx_exit_reflected() will not pass related exits to L1.
1764 * These rules have exceptions below.
1767 /* pin-based controls */
1768 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
1769 msrs
->pinbased_ctls_low
,
1770 msrs
->pinbased_ctls_high
);
1771 msrs
->pinbased_ctls_low
|=
1772 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
1773 msrs
->pinbased_ctls_high
&=
1774 PIN_BASED_EXT_INTR_MASK
|
1775 PIN_BASED_NMI_EXITING
|
1776 PIN_BASED_VIRTUAL_NMIS
|
1777 (apicv
? PIN_BASED_POSTED_INTR
: 0);
1778 msrs
->pinbased_ctls_high
|=
1779 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
1780 PIN_BASED_VMX_PREEMPTION_TIMER
;
1783 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
1784 msrs
->exit_ctls_low
,
1785 msrs
->exit_ctls_high
);
1786 msrs
->exit_ctls_low
=
1787 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
1789 msrs
->exit_ctls_high
&=
1790 #ifdef CONFIG_X86_64
1791 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
1793 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
1794 msrs
->exit_ctls_high
|=
1795 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
1796 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
1797 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
1799 /* We support free control of debug control saving. */
1800 msrs
->exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
1802 /* entry controls */
1803 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1804 msrs
->entry_ctls_low
,
1805 msrs
->entry_ctls_high
);
1806 msrs
->entry_ctls_low
=
1807 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
1808 msrs
->entry_ctls_high
&=
1809 #ifdef CONFIG_X86_64
1810 VM_ENTRY_IA32E_MODE
|
1812 VM_ENTRY_LOAD_IA32_PAT
;
1813 msrs
->entry_ctls_high
|=
1814 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
1816 /* We support free control of debug control loading. */
1817 msrs
->entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
1819 /* cpu-based controls */
1820 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1821 msrs
->procbased_ctls_low
,
1822 msrs
->procbased_ctls_high
);
1823 msrs
->procbased_ctls_low
=
1824 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
1825 msrs
->procbased_ctls_high
&=
1826 CPU_BASED_VIRTUAL_INTR_PENDING
|
1827 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1828 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1829 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1830 CPU_BASED_CR3_STORE_EXITING
|
1831 #ifdef CONFIG_X86_64
1832 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1834 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1835 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
1836 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
1837 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
1838 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1840 * We can allow some features even when not supported by the
1841 * hardware. For example, L1 can specify an MSR bitmap - and we
1842 * can use it to avoid exits to L1 - even when L0 runs L2
1843 * without MSR bitmaps.
1845 msrs
->procbased_ctls_high
|=
1846 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
1847 CPU_BASED_USE_MSR_BITMAPS
;
1849 /* We support free control of CR3 access interception. */
1850 msrs
->procbased_ctls_low
&=
1851 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
1854 * secondary cpu-based controls. Do not include those that
1855 * depend on CPUID bits, they are added later by vmx_cpuid_update.
1857 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1858 msrs
->secondary_ctls_low
,
1859 msrs
->secondary_ctls_high
);
1860 msrs
->secondary_ctls_low
= 0;
1861 msrs
->secondary_ctls_high
&=
1862 SECONDARY_EXEC_DESC
|
1863 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
1864 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
1865 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
1866 SECONDARY_EXEC_WBINVD_EXITING
;
1869 * We can emulate "VMCS shadowing," even if the hardware
1870 * doesn't support it.
1872 msrs
->secondary_ctls_high
|=
1873 SECONDARY_EXEC_SHADOW_VMCS
;
1876 /* nested EPT: emulate EPT also to L1 */
1877 msrs
->secondary_ctls_high
|=
1878 SECONDARY_EXEC_ENABLE_EPT
;
1879 msrs
->ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
1880 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
1881 if (cpu_has_vmx_ept_execute_only())
1883 VMX_EPT_EXECUTE_ONLY_BIT
;
1884 msrs
->ept_caps
&= ept_caps
;
1885 msrs
->ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
1886 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
1887 VMX_EPT_1GB_PAGE_BIT
;
1888 if (enable_ept_ad_bits
) {
1889 msrs
->secondary_ctls_high
|=
1890 SECONDARY_EXEC_ENABLE_PML
;
1891 msrs
->ept_caps
|= VMX_EPT_AD_BIT
;
1895 if (cpu_has_vmx_vmfunc()) {
1896 msrs
->secondary_ctls_high
|=
1897 SECONDARY_EXEC_ENABLE_VMFUNC
;
1899 * Advertise EPTP switching unconditionally
1900 * since we emulate it
1903 msrs
->vmfunc_controls
=
1904 VMX_VMFUNC_EPTP_SWITCHING
;
1908 * Old versions of KVM use the single-context version without
1909 * checking for support, so declare that it is supported even
1910 * though it is treated as global context. The alternative is
1911 * not failing the single-context invvpid, and it is worse.
1914 msrs
->secondary_ctls_high
|=
1915 SECONDARY_EXEC_ENABLE_VPID
;
1916 msrs
->vpid_caps
= VMX_VPID_INVVPID_BIT
|
1917 VMX_VPID_EXTENT_SUPPORTED_MASK
;
1920 if (enable_unrestricted_guest
)
1921 msrs
->secondary_ctls_high
|=
1922 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1924 if (flexpriority_enabled
)
1925 msrs
->secondary_ctls_high
|=
1926 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1928 /* miscellaneous data */
1929 rdmsr(MSR_IA32_VMX_MISC
,
1932 msrs
->misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
1934 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
|
1935 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
1936 VMX_MISC_ACTIVITY_HLT
;
1937 msrs
->misc_high
= 0;
1940 * This MSR reports some information about VMX support. We
1941 * should return information about the VMX we emulate for the
1942 * guest, and the VMCS structure we give it - not about the
1943 * VMX support of the underlying hardware.
1947 VMX_BASIC_TRUE_CTLS
|
1948 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
1949 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
1951 if (cpu_has_vmx_basic_inout())
1952 msrs
->basic
|= VMX_BASIC_INOUT
;
1955 * These MSRs specify bits which the guest must keep fixed on
1956 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1957 * We picked the standard core2 setting.
1959 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1960 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1961 msrs
->cr0_fixed0
= VMXON_CR0_ALWAYSON
;
1962 msrs
->cr4_fixed0
= VMXON_CR4_ALWAYSON
;
1964 /* These MSRs specify bits which the guest must keep fixed off. */
1965 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, msrs
->cr0_fixed1
);
1966 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, msrs
->cr4_fixed1
);
1968 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
1969 msrs
->vmcs_enum
= VMCS12_MAX_FIELD_INDEX
<< 1;
1973 * if fixed0[i] == 1: val[i] must be 1
1974 * if fixed1[i] == 0: val[i] must be 0
1976 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
1978 return ((val
& fixed1
) | fixed0
) == val
;
1981 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
1983 return fixed_bits_valid(control
, low
, high
);
1986 static inline u64
vmx_control_msr(u32 low
, u32 high
)
1988 return low
| ((u64
)high
<< 32);
1991 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
1996 return (superset
| subset
) == superset
;
1999 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2001 const u64 feature_and_reserved
=
2002 /* feature (except bit 48; see below) */
2003 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2005 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2006 u64 vmx_basic
= vmx
->nested
.msrs
.basic
;
2008 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2012 * KVM does not emulate a version of VMX that constrains physical
2013 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2015 if (data
& BIT_ULL(48))
2018 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2019 vmx_basic_vmcs_revision_id(data
))
2022 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2025 vmx
->nested
.msrs
.basic
= data
;
2030 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2035 switch (msr_index
) {
2036 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2037 lowp
= &vmx
->nested
.msrs
.pinbased_ctls_low
;
2038 highp
= &vmx
->nested
.msrs
.pinbased_ctls_high
;
2040 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2041 lowp
= &vmx
->nested
.msrs
.procbased_ctls_low
;
2042 highp
= &vmx
->nested
.msrs
.procbased_ctls_high
;
2044 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2045 lowp
= &vmx
->nested
.msrs
.exit_ctls_low
;
2046 highp
= &vmx
->nested
.msrs
.exit_ctls_high
;
2048 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2049 lowp
= &vmx
->nested
.msrs
.entry_ctls_low
;
2050 highp
= &vmx
->nested
.msrs
.entry_ctls_high
;
2052 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2053 lowp
= &vmx
->nested
.msrs
.secondary_ctls_low
;
2054 highp
= &vmx
->nested
.msrs
.secondary_ctls_high
;
2060 supported
= vmx_control_msr(*lowp
, *highp
);
2062 /* Check must-be-1 bits are still 1. */
2063 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2066 /* Check must-be-0 bits are still 0. */
2067 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2071 *highp
= data
>> 32;
2075 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2077 const u64 feature_and_reserved_bits
=
2079 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2080 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2082 GENMASK_ULL(13, 9) | BIT_ULL(31);
2085 vmx_misc
= vmx_control_msr(vmx
->nested
.msrs
.misc_low
,
2086 vmx
->nested
.msrs
.misc_high
);
2088 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2091 if ((vmx
->nested
.msrs
.pinbased_ctls_high
&
2092 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2093 vmx_misc_preemption_timer_rate(data
) !=
2094 vmx_misc_preemption_timer_rate(vmx_misc
))
2097 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2100 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2103 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2106 vmx
->nested
.msrs
.misc_low
= data
;
2107 vmx
->nested
.msrs
.misc_high
= data
>> 32;
2110 * If L1 has read-only VM-exit information fields, use the
2111 * less permissive vmx_vmwrite_bitmap to specify write
2112 * permissions for the shadow VMCS.
2114 if (enable_shadow_vmcs
&& !nested_cpu_has_vmwrite_any_field(&vmx
->vcpu
))
2115 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
2120 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2122 u64 vmx_ept_vpid_cap
;
2124 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.msrs
.ept_caps
,
2125 vmx
->nested
.msrs
.vpid_caps
);
2127 /* Every bit is either reserved or a feature bit. */
2128 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2131 vmx
->nested
.msrs
.ept_caps
= data
;
2132 vmx
->nested
.msrs
.vpid_caps
= data
>> 32;
2136 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2140 switch (msr_index
) {
2141 case MSR_IA32_VMX_CR0_FIXED0
:
2142 msr
= &vmx
->nested
.msrs
.cr0_fixed0
;
2144 case MSR_IA32_VMX_CR4_FIXED0
:
2145 msr
= &vmx
->nested
.msrs
.cr4_fixed0
;
2152 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
2153 * must be 1 in the restored value.
2155 if (!is_bitwise_subset(data
, *msr
, -1ULL))
2163 * Called when userspace is restoring VMX MSRs.
2165 * Returns 0 on success, non-0 otherwise.
2167 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2169 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2172 * Don't allow changes to the VMX capability MSRs while the vCPU
2173 * is in VMX operation.
2175 if (vmx
->nested
.vmxon
)
2178 switch (msr_index
) {
2179 case MSR_IA32_VMX_BASIC
:
2180 return vmx_restore_vmx_basic(vmx
, data
);
2181 case MSR_IA32_VMX_PINBASED_CTLS
:
2182 case MSR_IA32_VMX_PROCBASED_CTLS
:
2183 case MSR_IA32_VMX_EXIT_CTLS
:
2184 case MSR_IA32_VMX_ENTRY_CTLS
:
2186 * The "non-true" VMX capability MSRs are generated from the
2187 * "true" MSRs, so we do not support restoring them directly.
2189 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
2190 * should restore the "true" MSRs with the must-be-1 bits
2191 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
2192 * DEFAULT SETTINGS".
2195 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2196 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2197 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2198 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2199 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2200 return vmx_restore_control_msr(vmx
, msr_index
, data
);
2201 case MSR_IA32_VMX_MISC
:
2202 return vmx_restore_vmx_misc(vmx
, data
);
2203 case MSR_IA32_VMX_CR0_FIXED0
:
2204 case MSR_IA32_VMX_CR4_FIXED0
:
2205 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
2206 case MSR_IA32_VMX_CR0_FIXED1
:
2207 case MSR_IA32_VMX_CR4_FIXED1
:
2209 * These MSRs are generated based on the vCPU's CPUID, so we
2210 * do not support restoring them directly.
2213 case MSR_IA32_VMX_EPT_VPID_CAP
:
2214 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
2215 case MSR_IA32_VMX_VMCS_ENUM
:
2216 vmx
->nested
.msrs
.vmcs_enum
= data
;
2220 * The rest of the VMX capability MSRs do not support restore.
2226 /* Returns 0 on success, non-0 otherwise. */
2227 static int vmx_get_vmx_msr(struct nested_vmx_msrs
*msrs
, u32 msr_index
, u64
*pdata
)
2229 switch (msr_index
) {
2230 case MSR_IA32_VMX_BASIC
:
2231 *pdata
= msrs
->basic
;
2233 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2234 case MSR_IA32_VMX_PINBASED_CTLS
:
2235 *pdata
= vmx_control_msr(
2236 msrs
->pinbased_ctls_low
,
2237 msrs
->pinbased_ctls_high
);
2238 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
2239 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2241 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2242 case MSR_IA32_VMX_PROCBASED_CTLS
:
2243 *pdata
= vmx_control_msr(
2244 msrs
->procbased_ctls_low
,
2245 msrs
->procbased_ctls_high
);
2246 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
2247 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2249 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2250 case MSR_IA32_VMX_EXIT_CTLS
:
2251 *pdata
= vmx_control_msr(
2252 msrs
->exit_ctls_low
,
2253 msrs
->exit_ctls_high
);
2254 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
2255 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2257 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2258 case MSR_IA32_VMX_ENTRY_CTLS
:
2259 *pdata
= vmx_control_msr(
2260 msrs
->entry_ctls_low
,
2261 msrs
->entry_ctls_high
);
2262 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
2263 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2265 case MSR_IA32_VMX_MISC
:
2266 *pdata
= vmx_control_msr(
2270 case MSR_IA32_VMX_CR0_FIXED0
:
2271 *pdata
= msrs
->cr0_fixed0
;
2273 case MSR_IA32_VMX_CR0_FIXED1
:
2274 *pdata
= msrs
->cr0_fixed1
;
2276 case MSR_IA32_VMX_CR4_FIXED0
:
2277 *pdata
= msrs
->cr4_fixed0
;
2279 case MSR_IA32_VMX_CR4_FIXED1
:
2280 *pdata
= msrs
->cr4_fixed1
;
2282 case MSR_IA32_VMX_VMCS_ENUM
:
2283 *pdata
= msrs
->vmcs_enum
;
2285 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2286 *pdata
= vmx_control_msr(
2287 msrs
->secondary_ctls_low
,
2288 msrs
->secondary_ctls_high
);
2290 case MSR_IA32_VMX_EPT_VPID_CAP
:
2291 *pdata
= msrs
->ept_caps
|
2292 ((u64
)msrs
->vpid_caps
<< 32);
2294 case MSR_IA32_VMX_VMFUNC
:
2295 *pdata
= msrs
->vmfunc_controls
;
2304 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
2307 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
2309 return !(val
& ~valid_bits
);
2312 static int vmx_get_msr_feature(struct kvm_msr_entry
*msr
)
2314 switch (msr
->index
) {
2315 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2318 return vmx_get_vmx_msr(&vmcs_config
.nested
, msr
->index
, &msr
->data
);
2327 * Reads an msr value (of 'msr_index') into 'pdata'.
2328 * Returns 0 on success, non-0 otherwise.
2329 * Assumes vcpu_load() was already called.
2331 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2333 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2334 struct shared_msr_entry
*msr
;
2336 switch (msr_info
->index
) {
2337 #ifdef CONFIG_X86_64
2339 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2342 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2344 case MSR_KERNEL_GS_BASE
:
2345 msr_info
->data
= vmx_read_guest_kernel_gs_base(vmx
);
2349 return kvm_get_msr_common(vcpu
, msr_info
);
2350 case MSR_IA32_SPEC_CTRL
:
2351 if (!msr_info
->host_initiated
&&
2352 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
2355 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
2357 case MSR_IA32_ARCH_CAPABILITIES
:
2358 if (!msr_info
->host_initiated
&&
2359 !guest_cpuid_has(vcpu
, X86_FEATURE_ARCH_CAPABILITIES
))
2361 msr_info
->data
= to_vmx(vcpu
)->arch_capabilities
;
2363 case MSR_IA32_SYSENTER_CS
:
2364 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2366 case MSR_IA32_SYSENTER_EIP
:
2367 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2369 case MSR_IA32_SYSENTER_ESP
:
2370 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2372 case MSR_IA32_BNDCFGS
:
2373 if (!kvm_mpx_supported() ||
2374 (!msr_info
->host_initiated
&&
2375 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
2377 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2379 case MSR_IA32_MCG_EXT_CTL
:
2380 if (!msr_info
->host_initiated
&&
2381 !(vmx
->msr_ia32_feature_control
&
2382 FEATURE_CONTROL_LMCE
))
2384 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
2386 case MSR_IA32_FEATURE_CONTROL
:
2387 msr_info
->data
= vmx
->msr_ia32_feature_control
;
2389 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2390 if (!nested_vmx_allowed(vcpu
))
2392 return vmx_get_vmx_msr(&vmx
->nested
.msrs
, msr_info
->index
,
2395 if (!vmx_xsaves_supported())
2397 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2400 if (!msr_info
->host_initiated
&&
2401 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2403 /* Otherwise falls through */
2405 msr
= find_msr_entry(vmx
, msr_info
->index
);
2407 msr_info
->data
= msr
->data
;
2410 return kvm_get_msr_common(vcpu
, msr_info
);
2416 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2419 * Writes msr value into into the appropriate "register".
2420 * Returns 0 on success, non-0 otherwise.
2421 * Assumes vcpu_load() was already called.
2423 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2426 struct shared_msr_entry
*msr
;
2428 u32 msr_index
= msr_info
->index
;
2429 u64 data
= msr_info
->data
;
2431 switch (msr_index
) {
2433 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2435 #ifdef CONFIG_X86_64
2437 vmx_segment_cache_clear(vmx
);
2438 vmcs_writel(GUEST_FS_BASE
, data
);
2441 vmx_segment_cache_clear(vmx
);
2442 vmcs_writel(GUEST_GS_BASE
, data
);
2444 case MSR_KERNEL_GS_BASE
:
2445 vmx_write_guest_kernel_gs_base(vmx
, data
);
2448 case MSR_IA32_SYSENTER_CS
:
2449 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2451 case MSR_IA32_SYSENTER_EIP
:
2452 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2454 case MSR_IA32_SYSENTER_ESP
:
2455 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2457 case MSR_IA32_BNDCFGS
:
2458 if (!kvm_mpx_supported() ||
2459 (!msr_info
->host_initiated
&&
2460 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
2462 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
2463 (data
& MSR_IA32_BNDCFGS_RSVD
))
2465 vmcs_write64(GUEST_BNDCFGS
, data
);
2467 case MSR_IA32_SPEC_CTRL
:
2468 if (!msr_info
->host_initiated
&&
2469 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
2472 /* The STIBP bit doesn't fault even if it's not advertised */
2473 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
2476 vmx
->spec_ctrl
= data
;
2483 * When it's written (to non-zero) for the first time, pass
2487 * The handling of the MSR bitmap for L2 guests is done in
2488 * nested_vmx_merge_msr_bitmap. We should not touch the
2489 * vmcs02.msr_bitmap here since it gets completely overwritten
2490 * in the merging. We update the vmcs01 here for L1 as well
2491 * since it will end up touching the MSR anyway now.
2493 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
,
2497 case MSR_IA32_PRED_CMD
:
2498 if (!msr_info
->host_initiated
&&
2499 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
2502 if (data
& ~PRED_CMD_IBPB
)
2508 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
2512 * When it's written (to non-zero) for the first time, pass
2516 * The handling of the MSR bitmap for L2 guests is done in
2517 * nested_vmx_merge_msr_bitmap. We should not touch the
2518 * vmcs02.msr_bitmap here since it gets completely overwritten
2521 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
, MSR_IA32_PRED_CMD
,
2524 case MSR_IA32_ARCH_CAPABILITIES
:
2525 if (!msr_info
->host_initiated
)
2527 vmx
->arch_capabilities
= data
;
2529 case MSR_IA32_CR_PAT
:
2530 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2531 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2533 vmcs_write64(GUEST_IA32_PAT
, data
);
2534 vcpu
->arch
.pat
= data
;
2537 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2539 case MSR_IA32_TSC_ADJUST
:
2540 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2542 case MSR_IA32_MCG_EXT_CTL
:
2543 if ((!msr_info
->host_initiated
&&
2544 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
2545 FEATURE_CONTROL_LMCE
)) ||
2546 (data
& ~MCG_EXT_CTL_LMCE_EN
))
2548 vcpu
->arch
.mcg_ext_ctl
= data
;
2550 case MSR_IA32_FEATURE_CONTROL
:
2551 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
2552 (to_vmx(vcpu
)->msr_ia32_feature_control
&
2553 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2555 vmx
->msr_ia32_feature_control
= data
;
2556 if (msr_info
->host_initiated
&& data
== 0)
2557 vmx_leave_nested(vcpu
);
2559 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2560 if (!msr_info
->host_initiated
)
2561 return 1; /* they are read-only */
2562 if (!nested_vmx_allowed(vcpu
))
2564 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
2566 if (!vmx_xsaves_supported())
2569 * The only supported bit as of Skylake is bit 8, but
2570 * it is not supported on KVM.
2574 vcpu
->arch
.ia32_xss
= data
;
2575 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2576 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2577 vcpu
->arch
.ia32_xss
, host_xss
, false);
2579 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2582 if (!msr_info
->host_initiated
&&
2583 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2585 /* Check reserved bit, higher 32 bits should be zero */
2586 if ((data
>> 32) != 0)
2588 /* Otherwise falls through */
2590 msr
= find_msr_entry(vmx
, msr_index
);
2592 u64 old_msr_data
= msr
->data
;
2594 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2596 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2600 msr
->data
= old_msr_data
;
2604 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2610 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2612 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2615 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2618 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2620 case VCPU_EXREG_PDPTR
:
2622 ept_save_pdptrs(vcpu
);
2629 static __init
int cpu_has_kvm_support(void)
2631 return cpu_has_vmx();
2634 static __init
int vmx_disabled_by_bios(void)
2638 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2639 if (msr
& FEATURE_CONTROL_LOCKED
) {
2640 /* launched w/ TXT and VMX disabled */
2641 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2644 /* launched w/o TXT and VMX only enabled w/ TXT */
2645 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2646 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2647 && !tboot_enabled()) {
2648 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2649 "activate TXT before enabling KVM\n");
2652 /* launched w/o TXT and VMX disabled */
2653 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2654 && !tboot_enabled())
2661 static void kvm_cpu_vmxon(u64 addr
)
2663 cr4_set_bits(X86_CR4_VMXE
);
2664 intel_pt_handle_vmx(1);
2666 asm volatile ("vmxon %0" : : "m"(addr
));
2669 static int hardware_enable(void)
2671 int cpu
= raw_smp_processor_id();
2672 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2675 if (cr4_read_shadow() & X86_CR4_VMXE
)
2679 * This can happen if we hot-added a CPU but failed to allocate
2680 * VP assist page for it.
2682 if (static_branch_unlikely(&enable_evmcs
) &&
2683 !hv_get_vp_assist_page(cpu
))
2686 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2687 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
2688 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
2691 * Now we can enable the vmclear operation in kdump
2692 * since the loaded_vmcss_on_cpu list on this cpu
2693 * has been initialized.
2695 * Though the cpu is not in VMX operation now, there
2696 * is no problem to enable the vmclear operation
2697 * for the loaded_vmcss_on_cpu list is empty!
2699 crash_enable_local_vmclear(cpu
);
2701 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2703 test_bits
= FEATURE_CONTROL_LOCKED
;
2704 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2705 if (tboot_enabled())
2706 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2708 if ((old
& test_bits
) != test_bits
) {
2709 /* enable and lock */
2710 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2712 kvm_cpu_vmxon(phys_addr
);
2719 static void vmclear_local_loaded_vmcss(void)
2721 int cpu
= raw_smp_processor_id();
2722 struct loaded_vmcs
*v
, *n
;
2724 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2725 loaded_vmcss_on_cpu_link
)
2726 __loaded_vmcs_clear(v
);
2730 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2733 static void kvm_cpu_vmxoff(void)
2735 asm volatile (__ex("vmxoff"));
2737 intel_pt_handle_vmx(0);
2738 cr4_clear_bits(X86_CR4_VMXE
);
2741 static void hardware_disable(void)
2743 vmclear_local_loaded_vmcss();
2747 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2748 u32 msr
, u32
*result
)
2750 u32 vmx_msr_low
, vmx_msr_high
;
2751 u32 ctl
= ctl_min
| ctl_opt
;
2753 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2755 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2756 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2758 /* Ensure minimum (required) set of control bits are supported. */
2766 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
,
2767 struct vmx_capability
*vmx_cap
)
2769 u32 vmx_msr_low
, vmx_msr_high
;
2770 u32 min
, opt
, min2
, opt2
;
2771 u32 _pin_based_exec_control
= 0;
2772 u32 _cpu_based_exec_control
= 0;
2773 u32 _cpu_based_2nd_exec_control
= 0;
2774 u32 _vmexit_control
= 0;
2775 u32 _vmentry_control
= 0;
2777 memset(vmcs_conf
, 0, sizeof(*vmcs_conf
));
2778 min
= CPU_BASED_HLT_EXITING
|
2779 #ifdef CONFIG_X86_64
2780 CPU_BASED_CR8_LOAD_EXITING
|
2781 CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_CR3_LOAD_EXITING
|
2784 CPU_BASED_CR3_STORE_EXITING
|
2785 CPU_BASED_UNCOND_IO_EXITING
|
2786 CPU_BASED_MOV_DR_EXITING
|
2787 CPU_BASED_USE_TSC_OFFSETING
|
2788 CPU_BASED_MWAIT_EXITING
|
2789 CPU_BASED_MONITOR_EXITING
|
2790 CPU_BASED_INVLPG_EXITING
|
2791 CPU_BASED_RDPMC_EXITING
;
2793 opt
= CPU_BASED_TPR_SHADOW
|
2794 CPU_BASED_USE_MSR_BITMAPS
|
2795 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2796 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2797 &_cpu_based_exec_control
) < 0)
2799 #ifdef CONFIG_X86_64
2800 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2801 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2802 ~CPU_BASED_CR8_STORE_EXITING
;
2804 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2806 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2807 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2808 SECONDARY_EXEC_WBINVD_EXITING
|
2809 SECONDARY_EXEC_ENABLE_VPID
|
2810 SECONDARY_EXEC_ENABLE_EPT
|
2811 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2812 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2813 SECONDARY_EXEC_DESC
|
2814 SECONDARY_EXEC_RDTSCP
|
2815 SECONDARY_EXEC_ENABLE_INVPCID
|
2816 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2817 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2818 SECONDARY_EXEC_SHADOW_VMCS
|
2819 SECONDARY_EXEC_XSAVES
|
2820 SECONDARY_EXEC_RDSEED_EXITING
|
2821 SECONDARY_EXEC_RDRAND_EXITING
|
2822 SECONDARY_EXEC_ENABLE_PML
|
2823 SECONDARY_EXEC_TSC_SCALING
|
2824 SECONDARY_EXEC_ENABLE_VMFUNC
|
2825 SECONDARY_EXEC_ENCLS_EXITING
;
2826 if (adjust_vmx_controls(min2
, opt2
,
2827 MSR_IA32_VMX_PROCBASED_CTLS2
,
2828 &_cpu_based_2nd_exec_control
) < 0)
2831 #ifndef CONFIG_X86_64
2832 if (!(_cpu_based_2nd_exec_control
&
2833 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2834 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2837 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2838 _cpu_based_2nd_exec_control
&= ~(
2839 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2840 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2841 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2843 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
2844 &vmx_cap
->ept
, &vmx_cap
->vpid
);
2846 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2847 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2849 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2850 CPU_BASED_CR3_STORE_EXITING
|
2851 CPU_BASED_INVLPG_EXITING
);
2852 } else if (vmx_cap
->ept
) {
2854 pr_warn_once("EPT CAP should not exist if not support "
2855 "1-setting enable EPT VM-execution control\n");
2857 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
2860 pr_warn_once("VPID CAP should not exist if not support "
2861 "1-setting enable VPID VM-execution control\n");
2864 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
2865 #ifdef CONFIG_X86_64
2866 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2868 opt
= VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2869 VM_EXIT_SAVE_IA32_PAT
|
2870 VM_EXIT_LOAD_IA32_PAT
|
2871 VM_EXIT_LOAD_IA32_EFER
|
2872 VM_EXIT_CLEAR_BNDCFGS
;
2873 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2874 &_vmexit_control
) < 0)
2877 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2878 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
2879 PIN_BASED_VMX_PREEMPTION_TIMER
;
2880 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2881 &_pin_based_exec_control
) < 0)
2884 if (cpu_has_broken_vmx_preemption_timer())
2885 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2886 if (!(_cpu_based_2nd_exec_control
&
2887 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
2888 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2890 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2891 opt
= VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
|
2892 VM_ENTRY_LOAD_IA32_PAT
|
2893 VM_ENTRY_LOAD_IA32_EFER
|
2894 VM_ENTRY_LOAD_BNDCFGS
;
2895 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2896 &_vmentry_control
) < 0)
2900 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2901 * can't be used due to an errata where VM Exit may incorrectly clear
2902 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2903 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2905 if (boot_cpu_data
.x86
== 0x6) {
2906 switch (boot_cpu_data
.x86_model
) {
2907 case 26: /* AAK155 */
2908 case 30: /* AAP115 */
2909 case 37: /* AAT100 */
2910 case 44: /* BC86,AAY89,BD102 */
2912 _vmexit_control
&= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
;
2913 _vmexit_control
&= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
;
2914 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2915 "does not work properly. Using workaround\n");
2923 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2925 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2926 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2929 #ifdef CONFIG_X86_64
2930 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2931 if (vmx_msr_high
& (1u<<16))
2935 /* Require Write-Back (WB) memory type for VMCS accesses. */
2936 if (((vmx_msr_high
>> 18) & 15) != 6)
2939 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2940 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
2941 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
2943 vmcs_conf
->revision_id
= vmx_msr_low
;
2945 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2946 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2947 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2948 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2949 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2951 if (static_branch_unlikely(&enable_evmcs
))
2952 evmcs_sanitize_exec_ctrls(vmcs_conf
);
2957 struct vmcs
*alloc_vmcs_cpu(bool shadow
, int cpu
)
2959 int node
= cpu_to_node(cpu
);
2963 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2966 vmcs
= page_address(pages
);
2967 memset(vmcs
, 0, vmcs_config
.size
);
2969 /* KVM supports Enlightened VMCS v1 only */
2970 if (static_branch_unlikely(&enable_evmcs
))
2971 vmcs
->hdr
.revision_id
= KVM_EVMCS_VERSION
;
2973 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
2976 vmcs
->hdr
.shadow_vmcs
= 1;
2980 void free_vmcs(struct vmcs
*vmcs
)
2982 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2986 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2988 void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2990 if (!loaded_vmcs
->vmcs
)
2992 loaded_vmcs_clear(loaded_vmcs
);
2993 free_vmcs(loaded_vmcs
->vmcs
);
2994 loaded_vmcs
->vmcs
= NULL
;
2995 if (loaded_vmcs
->msr_bitmap
)
2996 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
2997 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3000 int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3002 loaded_vmcs
->vmcs
= alloc_vmcs(false);
3003 if (!loaded_vmcs
->vmcs
)
3006 loaded_vmcs
->shadow_vmcs
= NULL
;
3007 loaded_vmcs_init(loaded_vmcs
);
3009 if (cpu_has_vmx_msr_bitmap()) {
3010 loaded_vmcs
->msr_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3011 if (!loaded_vmcs
->msr_bitmap
)
3013 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
3015 if (IS_ENABLED(CONFIG_HYPERV
) &&
3016 static_branch_unlikely(&enable_evmcs
) &&
3017 (ms_hyperv
.nested_features
& HV_X64_NESTED_MSR_BITMAP
)) {
3018 struct hv_enlightened_vmcs
*evmcs
=
3019 (struct hv_enlightened_vmcs
*)loaded_vmcs
->vmcs
;
3021 evmcs
->hv_enlightenments_control
.msr_bitmap
= 1;
3025 memset(&loaded_vmcs
->host_state
, 0, sizeof(struct vmcs_host_state
));
3030 free_loaded_vmcs(loaded_vmcs
);
3034 static void free_kvm_area(void)
3038 for_each_possible_cpu(cpu
) {
3039 free_vmcs(per_cpu(vmxarea
, cpu
));
3040 per_cpu(vmxarea
, cpu
) = NULL
;
3044 static void init_vmcs_shadow_fields(void)
3048 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
3049 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
3051 for (i
= j
= 0; i
< max_shadow_read_only_fields
; i
++) {
3052 u16 field
= shadow_read_only_fields
[i
];
3053 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
3054 (i
+ 1 == max_shadow_read_only_fields
||
3055 shadow_read_only_fields
[i
+ 1] != field
+ 1))
3056 pr_err("Missing field from shadow_read_only_field %x\n",
3059 clear_bit(field
, vmx_vmread_bitmap
);
3060 #ifdef CONFIG_X86_64
3065 shadow_read_only_fields
[j
] = field
;
3068 max_shadow_read_only_fields
= j
;
3070 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3071 u16 field
= shadow_read_write_fields
[i
];
3072 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
3073 (i
+ 1 == max_shadow_read_write_fields
||
3074 shadow_read_write_fields
[i
+ 1] != field
+ 1))
3075 pr_err("Missing field from shadow_read_write_field %x\n",
3079 * PML and the preemption timer can be emulated, but the
3080 * processor cannot vmwrite to fields that don't exist
3084 case GUEST_PML_INDEX
:
3085 if (!cpu_has_vmx_pml())
3088 case VMX_PREEMPTION_TIMER_VALUE
:
3089 if (!cpu_has_vmx_preemption_timer())
3092 case GUEST_INTR_STATUS
:
3093 if (!cpu_has_vmx_apicv())
3100 clear_bit(field
, vmx_vmwrite_bitmap
);
3101 clear_bit(field
, vmx_vmread_bitmap
);
3102 #ifdef CONFIG_X86_64
3107 shadow_read_write_fields
[j
] = field
;
3110 max_shadow_read_write_fields
= j
;
3113 static __init
int alloc_kvm_area(void)
3117 for_each_possible_cpu(cpu
) {
3120 vmcs
= alloc_vmcs_cpu(false, cpu
);
3127 * When eVMCS is enabled, alloc_vmcs_cpu() sets
3128 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
3129 * revision_id reported by MSR_IA32_VMX_BASIC.
3131 * However, even though not explictly documented by
3132 * TLFS, VMXArea passed as VMXON argument should
3133 * still be marked with revision_id reported by
3136 if (static_branch_unlikely(&enable_evmcs
))
3137 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
3139 per_cpu(vmxarea
, cpu
) = vmcs
;
3144 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3145 struct kvm_segment
*save
)
3147 if (!emulate_invalid_guest_state
) {
3149 * CS and SS RPL should be equal during guest entry according
3150 * to VMX spec, but in reality it is not always so. Since vcpu
3151 * is in the middle of the transition from real mode to
3152 * protected mode it is safe to assume that RPL 0 is a good
3155 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3156 save
->selector
&= ~SEGMENT_RPL_MASK
;
3157 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3160 vmx_set_segment(vcpu
, save
, seg
);
3163 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3165 unsigned long flags
;
3166 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3169 * Update real mode segment cache. It may be not up-to-date if sement
3170 * register was written while vcpu was in a guest mode.
3172 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3173 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3174 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3175 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3176 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3177 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3179 vmx
->rmode
.vm86_active
= 0;
3181 vmx_segment_cache_clear(vmx
);
3183 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3185 flags
= vmcs_readl(GUEST_RFLAGS
);
3186 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3187 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3188 vmcs_writel(GUEST_RFLAGS
, flags
);
3190 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3191 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3193 update_exception_bitmap(vcpu
);
3195 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3196 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3197 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3198 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3199 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3200 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3203 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3205 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3206 struct kvm_segment var
= *save
;
3209 if (seg
== VCPU_SREG_CS
)
3212 if (!emulate_invalid_guest_state
) {
3213 var
.selector
= var
.base
>> 4;
3214 var
.base
= var
.base
& 0xffff0;
3224 if (save
->base
& 0xf)
3225 printk_once(KERN_WARNING
"kvm: segment base is not "
3226 "paragraph aligned when entering "
3227 "protected mode (seg=%d)", seg
);
3230 vmcs_write16(sf
->selector
, var
.selector
);
3231 vmcs_writel(sf
->base
, var
.base
);
3232 vmcs_write32(sf
->limit
, var
.limit
);
3233 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3236 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3238 unsigned long flags
;
3239 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3240 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(vcpu
->kvm
);
3242 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3243 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3244 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3245 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3246 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3247 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3248 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3250 vmx
->rmode
.vm86_active
= 1;
3253 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3254 * vcpu. Warn the user that an update is overdue.
3256 if (!kvm_vmx
->tss_addr
)
3257 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3258 "called before entering vcpu\n");
3260 vmx_segment_cache_clear(vmx
);
3262 vmcs_writel(GUEST_TR_BASE
, kvm_vmx
->tss_addr
);
3263 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3264 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3266 flags
= vmcs_readl(GUEST_RFLAGS
);
3267 vmx
->rmode
.save_rflags
= flags
;
3269 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3271 vmcs_writel(GUEST_RFLAGS
, flags
);
3272 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3273 update_exception_bitmap(vcpu
);
3275 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3276 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3277 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3278 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3279 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3280 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3282 kvm_mmu_reset_context(vcpu
);
3285 void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3287 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3288 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3293 vcpu
->arch
.efer
= efer
;
3294 if (efer
& EFER_LMA
) {
3295 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3298 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3300 msr
->data
= efer
& ~EFER_LME
;
3305 #ifdef CONFIG_X86_64
3307 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3311 vmx_segment_cache_clear(to_vmx(vcpu
));
3313 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3314 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3315 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3317 vmcs_write32(GUEST_TR_AR_BYTES
,
3318 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3319 | VMX_AR_TYPE_BUSY_64_TSS
);
3321 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3324 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3326 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3327 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3332 static void vmx_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t addr
)
3334 int vpid
= to_vmx(vcpu
)->vpid
;
3336 if (!vpid_sync_vcpu_addr(vpid
, addr
))
3337 vpid_sync_context(vpid
);
3340 * If VPIDs are not supported or enabled, then the above is a no-op.
3341 * But we don't really need a TLB flush in that case anyway, because
3342 * each VM entry/exit includes an implicit flush when VPID is 0.
3346 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3348 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3350 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3351 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3354 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3356 if (enable_unrestricted_guest
|| (enable_ept
&& is_paging(vcpu
)))
3357 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3358 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3361 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3363 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3365 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3366 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3369 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3371 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3373 if (!test_bit(VCPU_EXREG_PDPTR
,
3374 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3377 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3378 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3379 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3380 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3381 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3385 void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3387 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3389 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3390 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3391 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3392 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3393 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3396 __set_bit(VCPU_EXREG_PDPTR
,
3397 (unsigned long *)&vcpu
->arch
.regs_avail
);
3398 __set_bit(VCPU_EXREG_PDPTR
,
3399 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3402 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
3404 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed0
;
3405 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed1
;
3406 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
3408 if (to_vmx(vcpu
)->nested
.msrs
.secondary_ctls_high
&
3409 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
3410 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
3411 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
3413 return fixed_bits_valid(val
, fixed0
, fixed1
);
3416 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
3418 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed0
;
3419 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed1
;
3421 return fixed_bits_valid(val
, fixed0
, fixed1
);
3424 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
3426 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr4_fixed0
;
3427 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr4_fixed1
;
3429 return fixed_bits_valid(val
, fixed0
, fixed1
);
3432 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
3433 #define nested_guest_cr4_valid nested_cr4_valid
3434 #define nested_host_cr4_valid nested_cr4_valid
3436 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3438 struct kvm_vcpu
*vcpu
)
3440 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3441 vmx_decache_cr3(vcpu
);
3442 if (!(cr0
& X86_CR0_PG
)) {
3443 /* From paging/starting to nonpaging */
3444 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3445 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3446 (CPU_BASED_CR3_LOAD_EXITING
|
3447 CPU_BASED_CR3_STORE_EXITING
));
3448 vcpu
->arch
.cr0
= cr0
;
3449 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3450 } else if (!is_paging(vcpu
)) {
3451 /* From nonpaging to paging */
3452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3453 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3454 ~(CPU_BASED_CR3_LOAD_EXITING
|
3455 CPU_BASED_CR3_STORE_EXITING
));
3456 vcpu
->arch
.cr0
= cr0
;
3457 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3460 if (!(cr0
& X86_CR0_WP
))
3461 *hw_cr0
&= ~X86_CR0_WP
;
3464 void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3466 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3467 unsigned long hw_cr0
;
3469 hw_cr0
= (cr0
& ~KVM_VM_CR0_ALWAYS_OFF
);
3470 if (enable_unrestricted_guest
)
3471 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3473 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3475 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3478 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3482 #ifdef CONFIG_X86_64
3483 if (vcpu
->arch
.efer
& EFER_LME
) {
3484 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3486 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3491 if (enable_ept
&& !enable_unrestricted_guest
)
3492 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3494 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3495 vmcs_writel(GUEST_CR0
, hw_cr0
);
3496 vcpu
->arch
.cr0
= cr0
;
3498 /* depends on vcpu->arch.cr0 to be set to a new value */
3499 vmx
->emulation_required
= emulation_required(vcpu
);
3502 static int get_ept_level(struct kvm_vcpu
*vcpu
)
3504 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
3509 u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
3511 u64 eptp
= VMX_EPTP_MT_WB
;
3513 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
3515 if (enable_ept_ad_bits
&&
3516 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
3517 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
3518 eptp
|= (root_hpa
& PAGE_MASK
);
3523 void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3525 struct kvm
*kvm
= vcpu
->kvm
;
3526 unsigned long guest_cr3
;
3531 eptp
= construct_eptp(vcpu
, cr3
);
3532 vmcs_write64(EPT_POINTER
, eptp
);
3534 if (kvm_x86_ops
->tlb_remote_flush
) {
3535 spin_lock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
3536 to_vmx(vcpu
)->ept_pointer
= eptp
;
3537 to_kvm_vmx(kvm
)->ept_pointers_match
3538 = EPT_POINTERS_CHECK
;
3539 spin_unlock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
3542 if (enable_unrestricted_guest
|| is_paging(vcpu
) ||
3543 is_guest_mode(vcpu
))
3544 guest_cr3
= kvm_read_cr3(vcpu
);
3546 guest_cr3
= to_kvm_vmx(kvm
)->ept_identity_map_addr
;
3547 ept_load_pdptrs(vcpu
);
3550 vmcs_writel(GUEST_CR3
, guest_cr3
);
3553 int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3556 * Pass through host's Machine Check Enable value to hw_cr4, which
3557 * is in force while we are in guest mode. Do not let guests control
3558 * this bit, even if host CR4.MCE == 0.
3560 unsigned long hw_cr4
;
3562 hw_cr4
= (cr4_read_shadow() & X86_CR4_MCE
) | (cr4
& ~X86_CR4_MCE
);
3563 if (enable_unrestricted_guest
)
3564 hw_cr4
|= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST
;
3565 else if (to_vmx(vcpu
)->rmode
.vm86_active
)
3566 hw_cr4
|= KVM_RMODE_VM_CR4_ALWAYS_ON
;
3568 hw_cr4
|= KVM_PMODE_VM_CR4_ALWAYS_ON
;
3570 if (!boot_cpu_has(X86_FEATURE_UMIP
) && vmx_umip_emulated()) {
3571 if (cr4
& X86_CR4_UMIP
) {
3572 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
3573 SECONDARY_EXEC_DESC
);
3574 hw_cr4
&= ~X86_CR4_UMIP
;
3575 } else if (!is_guest_mode(vcpu
) ||
3576 !nested_cpu_has2(get_vmcs12(vcpu
), SECONDARY_EXEC_DESC
))
3577 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
3578 SECONDARY_EXEC_DESC
);
3581 if (cr4
& X86_CR4_VMXE
) {
3583 * To use VMXON (and later other VMX instructions), a guest
3584 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3585 * So basically the check on whether to allow nested VMX
3586 * is here. We operate under the default treatment of SMM,
3587 * so VMX cannot be enabled under SMM.
3589 if (!nested_vmx_allowed(vcpu
) || is_smm(vcpu
))
3593 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
3596 vcpu
->arch
.cr4
= cr4
;
3598 if (!enable_unrestricted_guest
) {
3600 if (!is_paging(vcpu
)) {
3601 hw_cr4
&= ~X86_CR4_PAE
;
3602 hw_cr4
|= X86_CR4_PSE
;
3603 } else if (!(cr4
& X86_CR4_PAE
)) {
3604 hw_cr4
&= ~X86_CR4_PAE
;
3609 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3610 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3611 * to be manually disabled when guest switches to non-paging
3614 * If !enable_unrestricted_guest, the CPU is always running
3615 * with CR0.PG=1 and CR4 needs to be modified.
3616 * If enable_unrestricted_guest, the CPU automatically
3617 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3619 if (!is_paging(vcpu
))
3620 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
3623 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3624 vmcs_writel(GUEST_CR4
, hw_cr4
);
3628 void vmx_get_segment(struct kvm_vcpu
*vcpu
, struct kvm_segment
*var
, int seg
)
3630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3633 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3634 *var
= vmx
->rmode
.segs
[seg
];
3635 if (seg
== VCPU_SREG_TR
3636 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3638 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3639 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3642 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3643 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3644 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3645 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3646 var
->unusable
= (ar
>> 16) & 1;
3647 var
->type
= ar
& 15;
3648 var
->s
= (ar
>> 4) & 1;
3649 var
->dpl
= (ar
>> 5) & 3;
3651 * Some userspaces do not preserve unusable property. Since usable
3652 * segment has to be present according to VMX spec we can use present
3653 * property to amend userspace bug by making unusable segment always
3654 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3655 * segment as unusable.
3657 var
->present
= !var
->unusable
;
3658 var
->avl
= (ar
>> 12) & 1;
3659 var
->l
= (ar
>> 13) & 1;
3660 var
->db
= (ar
>> 14) & 1;
3661 var
->g
= (ar
>> 15) & 1;
3664 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3666 struct kvm_segment s
;
3668 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3669 vmx_get_segment(vcpu
, &s
, seg
);
3672 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3675 int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3679 if (unlikely(vmx
->rmode
.vm86_active
))
3682 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3683 return VMX_AR_DPL(ar
);
3687 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3691 if (var
->unusable
|| !var
->present
)
3694 ar
= var
->type
& 15;
3695 ar
|= (var
->s
& 1) << 4;
3696 ar
|= (var
->dpl
& 3) << 5;
3697 ar
|= (var
->present
& 1) << 7;
3698 ar
|= (var
->avl
& 1) << 12;
3699 ar
|= (var
->l
& 1) << 13;
3700 ar
|= (var
->db
& 1) << 14;
3701 ar
|= (var
->g
& 1) << 15;
3707 void vmx_set_segment(struct kvm_vcpu
*vcpu
, struct kvm_segment
*var
, int seg
)
3709 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3710 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3712 vmx_segment_cache_clear(vmx
);
3714 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3715 vmx
->rmode
.segs
[seg
] = *var
;
3716 if (seg
== VCPU_SREG_TR
)
3717 vmcs_write16(sf
->selector
, var
->selector
);
3719 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3723 vmcs_writel(sf
->base
, var
->base
);
3724 vmcs_write32(sf
->limit
, var
->limit
);
3725 vmcs_write16(sf
->selector
, var
->selector
);
3728 * Fix the "Accessed" bit in AR field of segment registers for older
3730 * IA32 arch specifies that at the time of processor reset the
3731 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3732 * is setting it to 0 in the userland code. This causes invalid guest
3733 * state vmexit when "unrestricted guest" mode is turned on.
3734 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3735 * tree. Newer qemu binaries with that qemu fix would not need this
3738 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3739 var
->type
|= 0x1; /* Accessed */
3741 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3744 vmx
->emulation_required
= emulation_required(vcpu
);
3747 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3749 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3751 *db
= (ar
>> 14) & 1;
3752 *l
= (ar
>> 13) & 1;
3755 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3757 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3758 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3761 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3763 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3764 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3767 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3769 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3770 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3773 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3775 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3776 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3779 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3781 struct kvm_segment var
;
3784 vmx_get_segment(vcpu
, &var
, seg
);
3786 if (seg
== VCPU_SREG_CS
)
3788 ar
= vmx_segment_access_rights(&var
);
3790 if (var
.base
!= (var
.selector
<< 4))
3792 if (var
.limit
!= 0xffff)
3800 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3802 struct kvm_segment cs
;
3803 unsigned int cs_rpl
;
3805 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3806 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3810 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3814 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3815 if (cs
.dpl
> cs_rpl
)
3818 if (cs
.dpl
!= cs_rpl
)
3824 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3828 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3830 struct kvm_segment ss
;
3831 unsigned int ss_rpl
;
3833 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3834 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
3838 if (ss
.type
!= 3 && ss
.type
!= 7)
3842 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3850 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3852 struct kvm_segment var
;
3855 vmx_get_segment(vcpu
, &var
, seg
);
3856 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
3864 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
3865 if (var
.dpl
< rpl
) /* DPL < RPL */
3869 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3875 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3877 struct kvm_segment tr
;
3879 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3883 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3885 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3893 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3895 struct kvm_segment ldtr
;
3897 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3901 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3911 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3913 struct kvm_segment cs
, ss
;
3915 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3916 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3918 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
3919 (ss
.selector
& SEGMENT_RPL_MASK
));
3923 * Check if guest state is valid. Returns true if valid, false if
3925 * We assume that registers are always usable
3927 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3929 if (enable_unrestricted_guest
)
3932 /* real mode guest state checks */
3933 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3934 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3936 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3938 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3940 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3942 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3944 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3947 /* protected mode guest state checks */
3948 if (!cs_ss_rpl_check(vcpu
))
3950 if (!code_segment_valid(vcpu
))
3952 if (!stack_segment_valid(vcpu
))
3954 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3956 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3958 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3960 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3962 if (!tr_valid(vcpu
))
3964 if (!ldtr_valid(vcpu
))
3968 * - Add checks on RIP
3969 * - Add checks on RFLAGS
3975 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
3977 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
3980 static int init_rmode_tss(struct kvm
*kvm
)
3986 idx
= srcu_read_lock(&kvm
->srcu
);
3987 fn
= to_kvm_vmx(kvm
)->tss_addr
>> PAGE_SHIFT
;
3988 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3991 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3992 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3993 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3996 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3999 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4003 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4004 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4007 srcu_read_unlock(&kvm
->srcu
, idx
);
4011 static int init_rmode_identity_map(struct kvm
*kvm
)
4013 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(kvm
);
4015 kvm_pfn_t identity_map_pfn
;
4018 /* Protect kvm_vmx->ept_identity_pagetable_done. */
4019 mutex_lock(&kvm
->slots_lock
);
4021 if (likely(kvm_vmx
->ept_identity_pagetable_done
))
4024 if (!kvm_vmx
->ept_identity_map_addr
)
4025 kvm_vmx
->ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4026 identity_map_pfn
= kvm_vmx
->ept_identity_map_addr
>> PAGE_SHIFT
;
4028 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4029 kvm_vmx
->ept_identity_map_addr
, PAGE_SIZE
);
4033 idx
= srcu_read_lock(&kvm
->srcu
);
4034 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4037 /* Set up identity-mapping pagetable for EPT in real mode */
4038 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4039 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4040 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4041 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4042 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4046 kvm_vmx
->ept_identity_pagetable_done
= true;
4049 srcu_read_unlock(&kvm
->srcu
, idx
);
4052 mutex_unlock(&kvm
->slots_lock
);
4056 static void seg_setup(int seg
)
4058 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4061 vmcs_write16(sf
->selector
, 0);
4062 vmcs_writel(sf
->base
, 0);
4063 vmcs_write32(sf
->limit
, 0xffff);
4065 if (seg
== VCPU_SREG_CS
)
4066 ar
|= 0x08; /* code segment */
4068 vmcs_write32(sf
->ar_bytes
, ar
);
4071 static int alloc_apic_access_page(struct kvm
*kvm
)
4076 mutex_lock(&kvm
->slots_lock
);
4077 if (kvm
->arch
.apic_access_page_done
)
4079 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4080 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4084 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4085 if (is_error_page(page
)) {
4091 * Do not pin the page in memory, so that memory hot-unplug
4092 * is able to migrate it.
4095 kvm
->arch
.apic_access_page_done
= true;
4097 mutex_unlock(&kvm
->slots_lock
);
4101 int allocate_vpid(void)
4107 spin_lock(&vmx_vpid_lock
);
4108 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4109 if (vpid
< VMX_NR_VPIDS
)
4110 __set_bit(vpid
, vmx_vpid_bitmap
);
4113 spin_unlock(&vmx_vpid_lock
);
4117 void free_vpid(int vpid
)
4119 if (!enable_vpid
|| vpid
== 0)
4121 spin_lock(&vmx_vpid_lock
);
4122 __clear_bit(vpid
, vmx_vpid_bitmap
);
4123 spin_unlock(&vmx_vpid_lock
);
4126 static __always_inline
void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4129 int f
= sizeof(unsigned long);
4131 if (!cpu_has_vmx_msr_bitmap())
4134 if (static_branch_unlikely(&enable_evmcs
))
4135 evmcs_touch_msr_bitmap();
4138 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4139 * have the write-low and read-high bitmap offsets the wrong way round.
4140 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4142 if (msr
<= 0x1fff) {
4143 if (type
& MSR_TYPE_R
)
4145 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4147 if (type
& MSR_TYPE_W
)
4149 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4151 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4153 if (type
& MSR_TYPE_R
)
4155 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4157 if (type
& MSR_TYPE_W
)
4159 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4164 static __always_inline
void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4167 int f
= sizeof(unsigned long);
4169 if (!cpu_has_vmx_msr_bitmap())
4172 if (static_branch_unlikely(&enable_evmcs
))
4173 evmcs_touch_msr_bitmap();
4176 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4177 * have the write-low and read-high bitmap offsets the wrong way round.
4178 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4180 if (msr
<= 0x1fff) {
4181 if (type
& MSR_TYPE_R
)
4183 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4185 if (type
& MSR_TYPE_W
)
4187 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4189 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4191 if (type
& MSR_TYPE_R
)
4193 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4195 if (type
& MSR_TYPE_W
)
4197 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4202 static __always_inline
void vmx_set_intercept_for_msr(unsigned long *msr_bitmap
,
4203 u32 msr
, int type
, bool value
)
4206 vmx_enable_intercept_for_msr(msr_bitmap
, msr
, type
);
4208 vmx_disable_intercept_for_msr(msr_bitmap
, msr
, type
);
4212 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4213 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4215 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4216 unsigned long *msr_bitmap_nested
,
4219 int f
= sizeof(unsigned long);
4222 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4223 * have the write-low and read-high bitmap offsets the wrong way round.
4224 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4226 if (msr
<= 0x1fff) {
4227 if (type
& MSR_TYPE_R
&&
4228 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4230 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4232 if (type
& MSR_TYPE_W
&&
4233 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4235 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4237 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4239 if (type
& MSR_TYPE_R
&&
4240 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4242 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4244 if (type
& MSR_TYPE_W
&&
4245 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4247 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4252 static u8
vmx_msr_bitmap_mode(struct kvm_vcpu
*vcpu
)
4256 if (cpu_has_secondary_exec_ctrls() &&
4257 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
4258 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
4259 mode
|= MSR_BITMAP_MODE_X2APIC
;
4260 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
4261 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
4267 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap
,
4272 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
4273 unsigned word
= msr
/ BITS_PER_LONG
;
4274 msr_bitmap
[word
] = (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
4275 msr_bitmap
[word
+ (0x800 / sizeof(long))] = ~0;
4278 if (mode
& MSR_BITMAP_MODE_X2APIC
) {
4280 * TPR reads and writes can be virtualized even if virtual interrupt
4281 * delivery is not in use.
4283 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
);
4284 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
4285 vmx_enable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_R
);
4286 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
4287 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
4292 void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
)
4294 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4295 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
4296 u8 mode
= vmx_msr_bitmap_mode(vcpu
);
4297 u8 changed
= mode
^ vmx
->msr_bitmap_mode
;
4302 if (changed
& (MSR_BITMAP_MODE_X2APIC
| MSR_BITMAP_MODE_X2APIC_APICV
))
4303 vmx_update_msr_bitmap_x2apic(msr_bitmap
, mode
);
4305 vmx
->msr_bitmap_mode
= mode
;
4308 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
4310 return enable_apicv
;
4313 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
4315 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4319 * Don't need to mark the APIC access page dirty; it is never
4320 * written to by the CPU during APIC virtualization.
4323 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
4324 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
4325 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
4328 if (nested_cpu_has_posted_intr(vmcs12
)) {
4329 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
4330 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
4335 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4337 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4342 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
4345 vmx
->nested
.pi_pending
= false;
4346 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4349 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4350 if (max_irr
!= 256) {
4351 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4352 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
,
4353 vapic_page
, &max_irr
);
4354 kunmap(vmx
->nested
.virtual_apic_page
);
4356 status
= vmcs_read16(GUEST_INTR_STATUS
);
4357 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4359 status
|= (u8
)max_irr
;
4360 vmcs_write16(GUEST_INTR_STATUS
, status
);
4364 nested_mark_vmcs12_pages_dirty(vcpu
);
4367 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
4369 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4374 if (WARN_ON_ONCE(!is_guest_mode(vcpu
)) ||
4375 !nested_cpu_has_vid(get_vmcs12(vcpu
)) ||
4376 WARN_ON_ONCE(!vmx
->nested
.virtual_apic_page
))
4379 rvi
= vmx_get_rvi();
4381 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4382 vppr
= *((u32
*)(vapic_page
+ APIC_PROCPRI
));
4383 kunmap(vmx
->nested
.virtual_apic_page
);
4385 return ((rvi
& 0xf0) > (vppr
& 0xf0));
4388 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
4392 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
4394 if (vcpu
->mode
== IN_GUEST_MODE
) {
4396 * The vector of interrupt to be delivered to vcpu had
4397 * been set in PIR before this function.
4399 * Following cases will be reached in this block, and
4400 * we always send a notification event in all cases as
4403 * Case 1: vcpu keeps in non-root mode. Sending a
4404 * notification event posts the interrupt to vcpu.
4406 * Case 2: vcpu exits to root mode and is still
4407 * runnable. PIR will be synced to vIRR before the
4408 * next vcpu entry. Sending a notification event in
4409 * this case has no effect, as vcpu is not in root
4412 * Case 3: vcpu exits to root mode and is blocked.
4413 * vcpu_block() has already synced PIR to vIRR and
4414 * never blocks vcpu if vIRR is not cleared. Therefore,
4415 * a blocked vcpu here does not wait for any requested
4416 * interrupts in PIR, and sending a notification event
4417 * which has no effect is safe here.
4420 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
4427 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4430 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4432 if (is_guest_mode(vcpu
) &&
4433 vector
== vmx
->nested
.posted_intr_nv
) {
4435 * If a posted intr is not recognized by hardware,
4436 * we will accomplish it in the next vmentry.
4438 vmx
->nested
.pi_pending
= true;
4439 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4440 /* the PIR and ON have been set by L1. */
4441 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
4442 kvm_vcpu_kick(vcpu
);
4448 * Send interrupt to vcpu via posted interrupt way.
4449 * 1. If target vcpu is running(non-root mode), send posted interrupt
4450 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4451 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4452 * interrupt from PIR in next vmentry.
4454 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4456 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4459 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4463 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4466 /* If a previous notification has sent the IPI, nothing to do. */
4467 if (pi_test_and_set_on(&vmx
->pi_desc
))
4470 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
4471 kvm_vcpu_kick(vcpu
);
4475 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4476 * will not change in the lifetime of the guest.
4477 * Note that host-state that does change is set elsewhere. E.g., host-state
4478 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4480 void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4485 unsigned long cr0
, cr3
, cr4
;
4488 WARN_ON(cr0
& X86_CR0_TS
);
4489 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
4492 * Save the most likely value for this task's CR3 in the VMCS.
4493 * We can't use __get_current_cr3_fast() because we're not atomic.
4496 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
4497 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
4499 /* Save the most likely value for this task's CR4 in the VMCS. */
4500 cr4
= cr4_read_shadow();
4501 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4502 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
4504 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4505 #ifdef CONFIG_X86_64
4507 * Load null selectors, so we can avoid reloading them in
4508 * vmx_prepare_switch_to_host(), in case userspace uses
4509 * the null selectors too (the expected case).
4511 vmcs_write16(HOST_DS_SELECTOR
, 0);
4512 vmcs_write16(HOST_ES_SELECTOR
, 0);
4514 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4515 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4517 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4518 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4521 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4522 vmx
->host_idt_base
= dt
.address
;
4524 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4526 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4527 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4528 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4529 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4531 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4532 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4533 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4536 if (cpu_has_load_ia32_efer())
4537 vmcs_write64(HOST_IA32_EFER
, host_efer
);
4540 void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4542 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4544 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4545 if (is_guest_mode(&vmx
->vcpu
))
4546 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4547 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4548 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4551 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4553 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4555 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4556 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4559 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
4561 /* Enable the preemption timer dynamically */
4562 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4563 return pin_based_exec_ctrl
;
4566 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4568 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4570 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4571 if (cpu_has_secondary_exec_ctrls()) {
4572 if (kvm_vcpu_apicv_active(vcpu
))
4573 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4574 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4575 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4577 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4578 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4579 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4582 if (cpu_has_vmx_msr_bitmap())
4583 vmx_update_msr_bitmap(vcpu
);
4586 u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4588 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4590 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4591 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4593 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4594 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4595 #ifdef CONFIG_X86_64
4596 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4597 CPU_BASED_CR8_LOAD_EXITING
;
4601 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4602 CPU_BASED_CR3_LOAD_EXITING
|
4603 CPU_BASED_INVLPG_EXITING
;
4604 if (kvm_mwait_in_guest(vmx
->vcpu
.kvm
))
4605 exec_control
&= ~(CPU_BASED_MWAIT_EXITING
|
4606 CPU_BASED_MONITOR_EXITING
);
4607 if (kvm_hlt_in_guest(vmx
->vcpu
.kvm
))
4608 exec_control
&= ~CPU_BASED_HLT_EXITING
;
4609 return exec_control
;
4613 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
4615 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
4617 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4619 if (!cpu_need_virtualize_apic_accesses(vcpu
))
4620 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4622 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4624 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4625 enable_unrestricted_guest
= 0;
4627 if (!enable_unrestricted_guest
)
4628 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4629 if (kvm_pause_in_guest(vmx
->vcpu
.kvm
))
4630 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4631 if (!kvm_vcpu_apicv_active(vcpu
))
4632 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4633 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4634 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4636 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4637 * in vmx_set_cr4. */
4638 exec_control
&= ~SECONDARY_EXEC_DESC
;
4640 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4642 We can NOT enable shadow_vmcs here because we don't have yet
4645 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4648 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4650 if (vmx_xsaves_supported()) {
4651 /* Exposing XSAVES only when XSAVE is exposed */
4652 bool xsaves_enabled
=
4653 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
4654 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
4656 if (!xsaves_enabled
)
4657 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
4661 vmx
->nested
.msrs
.secondary_ctls_high
|=
4662 SECONDARY_EXEC_XSAVES
;
4664 vmx
->nested
.msrs
.secondary_ctls_high
&=
4665 ~SECONDARY_EXEC_XSAVES
;
4669 if (vmx_rdtscp_supported()) {
4670 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
4671 if (!rdtscp_enabled
)
4672 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4676 vmx
->nested
.msrs
.secondary_ctls_high
|=
4677 SECONDARY_EXEC_RDTSCP
;
4679 vmx
->nested
.msrs
.secondary_ctls_high
&=
4680 ~SECONDARY_EXEC_RDTSCP
;
4684 if (vmx_invpcid_supported()) {
4685 /* Exposing INVPCID only when PCID is exposed */
4686 bool invpcid_enabled
=
4687 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
4688 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
4690 if (!invpcid_enabled
) {
4691 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4692 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
4696 if (invpcid_enabled
)
4697 vmx
->nested
.msrs
.secondary_ctls_high
|=
4698 SECONDARY_EXEC_ENABLE_INVPCID
;
4700 vmx
->nested
.msrs
.secondary_ctls_high
&=
4701 ~SECONDARY_EXEC_ENABLE_INVPCID
;
4705 if (vmx_rdrand_supported()) {
4706 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
4708 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
4712 vmx
->nested
.msrs
.secondary_ctls_high
|=
4713 SECONDARY_EXEC_RDRAND_EXITING
;
4715 vmx
->nested
.msrs
.secondary_ctls_high
&=
4716 ~SECONDARY_EXEC_RDRAND_EXITING
;
4720 if (vmx_rdseed_supported()) {
4721 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
4723 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
4727 vmx
->nested
.msrs
.secondary_ctls_high
|=
4728 SECONDARY_EXEC_RDSEED_EXITING
;
4730 vmx
->nested
.msrs
.secondary_ctls_high
&=
4731 ~SECONDARY_EXEC_RDSEED_EXITING
;
4735 vmx
->secondary_exec_control
= exec_control
;
4738 static void ept_set_mmio_spte_mask(void)
4741 * EPT Misconfigurations can be generated if the value of bits 2:0
4742 * of an EPT paging-structure entry is 110b (write/execute).
4744 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
4745 VMX_EPT_MISCONFIG_WX_VALUE
);
4748 #define VMX_XSS_EXIT_BITMAP 0
4750 static void nested_vmx_vcpu_setup(void)
4752 if (enable_shadow_vmcs
) {
4754 * At vCPU creation, "VMWRITE to any supported field
4755 * in the VMCS" is supported, so use the more
4756 * permissive vmx_vmread_bitmap to specify both read
4757 * and write permissions for the shadow VMCS.
4759 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4760 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmread_bitmap
));
4765 * Sets up the vmcs for emulated real mode.
4767 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4772 nested_vmx_vcpu_setup();
4774 if (cpu_has_vmx_msr_bitmap())
4775 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
4777 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4780 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4781 vmx
->hv_deadline_tsc
= -1;
4783 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4785 if (cpu_has_secondary_exec_ctrls()) {
4786 vmx_compute_secondary_exec_control(vmx
);
4787 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4788 vmx
->secondary_exec_control
);
4791 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
4792 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4793 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4794 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4795 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4797 vmcs_write16(GUEST_INTR_STATUS
, 0);
4799 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4800 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4803 if (!kvm_pause_in_guest(vmx
->vcpu
.kvm
)) {
4804 vmcs_write32(PLE_GAP
, ple_gap
);
4805 vmx
->ple_window
= ple_window
;
4806 vmx
->ple_window_dirty
= true;
4809 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4810 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4811 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4813 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4814 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4815 vmx_set_constant_host_state(vmx
);
4816 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4817 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4819 if (cpu_has_vmx_vmfunc())
4820 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
4822 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4823 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4824 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
.val
));
4825 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4826 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
.val
));
4828 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4829 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4831 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4832 u32 index
= vmx_msr_index
[i
];
4833 u32 data_low
, data_high
;
4836 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4838 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4840 vmx
->guest_msrs
[j
].index
= i
;
4841 vmx
->guest_msrs
[j
].data
= 0;
4842 vmx
->guest_msrs
[j
].mask
= -1ull;
4846 vmx
->arch_capabilities
= kvm_get_arch_capabilities();
4848 vm_exit_controls_init(vmx
, vmx_vmexit_ctrl());
4850 /* 22.2.1, 20.8.1 */
4851 vm_entry_controls_init(vmx
, vmx_vmentry_ctrl());
4853 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
4854 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
4856 set_cr4_guest_host_mask(vmx
);
4858 if (vmx_xsaves_supported())
4859 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4862 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
4863 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
4866 if (cpu_has_vmx_encls_vmexit())
4867 vmcs_write64(ENCLS_EXITING_BITMAP
, -1ull);
4870 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4872 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4873 struct msr_data apic_base_msr
;
4876 vmx
->rmode
.vm86_active
= 0;
4879 vcpu
->arch
.microcode_version
= 0x100000000ULL
;
4880 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4881 kvm_set_cr8(vcpu
, 0);
4884 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4885 MSR_IA32_APICBASE_ENABLE
;
4886 if (kvm_vcpu_is_reset_bsp(vcpu
))
4887 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4888 apic_base_msr
.host_initiated
= true;
4889 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4892 vmx_segment_cache_clear(vmx
);
4894 seg_setup(VCPU_SREG_CS
);
4895 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4896 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
4898 seg_setup(VCPU_SREG_DS
);
4899 seg_setup(VCPU_SREG_ES
);
4900 seg_setup(VCPU_SREG_FS
);
4901 seg_setup(VCPU_SREG_GS
);
4902 seg_setup(VCPU_SREG_SS
);
4904 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4905 vmcs_writel(GUEST_TR_BASE
, 0);
4906 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4907 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4909 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4910 vmcs_writel(GUEST_LDTR_BASE
, 0);
4911 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4912 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4915 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4916 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4917 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4918 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4921 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
4922 kvm_rip_write(vcpu
, 0xfff0);
4924 vmcs_writel(GUEST_GDTR_BASE
, 0);
4925 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4927 vmcs_writel(GUEST_IDTR_BASE
, 0);
4928 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4930 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4931 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4932 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4933 if (kvm_mpx_supported())
4934 vmcs_write64(GUEST_BNDCFGS
, 0);
4938 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4940 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4941 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4942 if (cpu_need_tpr_shadow(vcpu
))
4943 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4944 __pa(vcpu
->arch
.apic
->regs
));
4945 vmcs_write32(TPR_THRESHOLD
, 0);
4948 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4951 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4953 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4954 vmx
->vcpu
.arch
.cr0
= cr0
;
4955 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4956 vmx_set_cr4(vcpu
, 0);
4957 vmx_set_efer(vcpu
, 0);
4959 update_exception_bitmap(vcpu
);
4961 vpid_sync_context(vmx
->vpid
);
4963 vmx_clear_hlt(vcpu
);
4967 * In nested virtualization, check if L1 asked to exit on external interrupts.
4968 * For most existing hypervisors, this will always return true.
4970 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4972 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4973 PIN_BASED_EXT_INTR_MASK
;
4977 * In nested virtualization, check if L1 has set
4978 * VM_EXIT_ACK_INTR_ON_EXIT
4980 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4982 return get_vmcs12(vcpu
)->vm_exit_controls
&
4983 VM_EXIT_ACK_INTR_ON_EXIT
;
4986 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4988 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu
));
4991 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4993 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
4994 CPU_BASED_VIRTUAL_INTR_PENDING
);
4997 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5000 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5001 enable_irq_window(vcpu
);
5005 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5006 CPU_BASED_VIRTUAL_NMI_PENDING
);
5009 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5011 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5013 int irq
= vcpu
->arch
.interrupt
.nr
;
5015 trace_kvm_inj_virq(irq
);
5017 ++vcpu
->stat
.irq_injections
;
5018 if (vmx
->rmode
.vm86_active
) {
5020 if (vcpu
->arch
.interrupt
.soft
)
5021 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5022 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5023 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5026 intr
= irq
| INTR_INFO_VALID_MASK
;
5027 if (vcpu
->arch
.interrupt
.soft
) {
5028 intr
|= INTR_TYPE_SOFT_INTR
;
5029 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5030 vmx
->vcpu
.arch
.event_exit_inst_len
);
5032 intr
|= INTR_TYPE_EXT_INTR
;
5033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5035 vmx_clear_hlt(vcpu
);
5038 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5040 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5044 * Tracking the NMI-blocked state in software is built upon
5045 * finding the next open IRQ window. This, in turn, depends on
5046 * well-behaving guests: They have to keep IRQs disabled at
5047 * least as long as the NMI handler runs. Otherwise we may
5048 * cause NMI nesting, maybe breaking the guest. But as this is
5049 * highly unlikely, we can live with the residual risk.
5051 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5052 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5055 ++vcpu
->stat
.nmi_injections
;
5056 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5058 if (vmx
->rmode
.vm86_active
) {
5059 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5060 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5064 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5065 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5067 vmx_clear_hlt(vcpu
);
5070 bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5072 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5076 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5077 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5079 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5080 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5084 void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5086 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5089 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5090 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5091 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5094 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5097 GUEST_INTR_STATE_NMI
);
5099 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5100 GUEST_INTR_STATE_NMI
);
5104 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5106 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5110 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
5113 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5114 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5115 | GUEST_INTR_STATE_NMI
));
5118 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5120 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5121 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5122 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5123 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5126 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5130 if (enable_unrestricted_guest
)
5133 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5137 to_kvm_vmx(kvm
)->tss_addr
= addr
;
5138 return init_rmode_tss(kvm
);
5141 static int vmx_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
5143 to_kvm_vmx(kvm
)->ept_identity_map_addr
= ident_addr
;
5147 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5152 * Update instruction length as we may reinject the exception
5153 * from user space while in guest debugging mode.
5155 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5156 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5157 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5161 if (vcpu
->guest_debug
&
5162 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5179 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5180 int vec
, u32 err_code
)
5183 * Instruction with address size override prefix opcode 0x67
5184 * Cause the #SS fault with 0 error code in VM86 mode.
5186 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5187 if (kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5188 if (vcpu
->arch
.halt_request
) {
5189 vcpu
->arch
.halt_request
= 0;
5190 return kvm_vcpu_halt(vcpu
);
5198 * Forward all other exceptions that are valid in real mode.
5199 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5200 * the required debugging infrastructure rework.
5202 kvm_queue_exception(vcpu
, vec
);
5207 * Trigger machine check on the host. We assume all the MSRs are already set up
5208 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5209 * We pass a fake environment to the machine check handler because we want
5210 * the guest to be always treated like user space, no matter what context
5211 * it used internally.
5213 static void kvm_machine_check(void)
5215 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5216 struct pt_regs regs
= {
5217 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5218 .flags
= X86_EFLAGS_IF
,
5221 do_machine_check(®s
, 0);
5225 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5227 /* already handled by vcpu_run */
5231 static int handle_exception(struct kvm_vcpu
*vcpu
)
5233 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5234 struct kvm_run
*kvm_run
= vcpu
->run
;
5235 u32 intr_info
, ex_no
, error_code
;
5236 unsigned long cr2
, rip
, dr6
;
5238 enum emulation_result er
;
5240 vect_info
= vmx
->idt_vectoring_info
;
5241 intr_info
= vmx
->exit_intr_info
;
5243 if (is_machine_check(intr_info
))
5244 return handle_machine_check(vcpu
);
5246 if (is_nmi(intr_info
))
5247 return 1; /* already handled by vmx_vcpu_run() */
5249 if (is_invalid_opcode(intr_info
))
5250 return handle_ud(vcpu
);
5253 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5254 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5256 if (!vmx
->rmode
.vm86_active
&& is_gp_fault(intr_info
)) {
5257 WARN_ON_ONCE(!enable_vmware_backdoor
);
5258 er
= kvm_emulate_instruction(vcpu
,
5259 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
5260 if (er
== EMULATE_USER_EXIT
)
5262 else if (er
!= EMULATE_DONE
)
5263 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
5268 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5269 * MMIO, it is better to report an internal error.
5270 * See the comments in vmx_handle_exit.
5272 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5273 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5274 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5275 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5276 vcpu
->run
->internal
.ndata
= 3;
5277 vcpu
->run
->internal
.data
[0] = vect_info
;
5278 vcpu
->run
->internal
.data
[1] = intr_info
;
5279 vcpu
->run
->internal
.data
[2] = error_code
;
5283 if (is_page_fault(intr_info
)) {
5284 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5285 /* EPT won't cause page fault directly */
5286 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5287 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
5290 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5292 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5293 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5297 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5300 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5301 if (!(vcpu
->guest_debug
&
5302 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5303 vcpu
->arch
.dr6
&= ~15;
5304 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5305 if (is_icebp(intr_info
))
5306 skip_emulated_instruction(vcpu
);
5308 kvm_queue_exception(vcpu
, DB_VECTOR
);
5311 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5312 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5316 * Update instruction length as we may reinject #BP from
5317 * user space while in guest debugging mode. Reading it for
5318 * #DB as well causes no harm, it is not used in that case.
5320 vmx
->vcpu
.arch
.event_exit_inst_len
=
5321 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5322 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5323 rip
= kvm_rip_read(vcpu
);
5324 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5325 kvm_run
->debug
.arch
.exception
= ex_no
;
5328 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5329 kvm_run
->ex
.exception
= ex_no
;
5330 kvm_run
->ex
.error_code
= error_code
;
5336 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5338 ++vcpu
->stat
.irq_exits
;
5342 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5344 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5345 vcpu
->mmio_needed
= 0;
5349 static int handle_io(struct kvm_vcpu
*vcpu
)
5351 unsigned long exit_qualification
;
5352 int size
, in
, string
;
5355 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5356 string
= (exit_qualification
& 16) != 0;
5358 ++vcpu
->stat
.io_exits
;
5361 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5363 port
= exit_qualification
>> 16;
5364 size
= (exit_qualification
& 7) + 1;
5365 in
= (exit_qualification
& 8) != 0;
5367 return kvm_fast_pio(vcpu
, size
, port
, in
);
5371 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5374 * Patch in the VMCALL instruction:
5376 hypercall
[0] = 0x0f;
5377 hypercall
[1] = 0x01;
5378 hypercall
[2] = 0xc1;
5381 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5382 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5384 if (is_guest_mode(vcpu
)) {
5385 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5386 unsigned long orig_val
= val
;
5389 * We get here when L2 changed cr0 in a way that did not change
5390 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5391 * but did change L0 shadowed bits. So we first calculate the
5392 * effective cr0 value that L1 would like to write into the
5393 * hardware. It consists of the L2-owned bits from the new
5394 * value combined with the L1-owned bits from L1's guest_cr0.
5396 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5397 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5399 if (!nested_guest_cr0_valid(vcpu
, val
))
5402 if (kvm_set_cr0(vcpu
, val
))
5404 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5407 if (to_vmx(vcpu
)->nested
.vmxon
&&
5408 !nested_host_cr0_valid(vcpu
, val
))
5411 return kvm_set_cr0(vcpu
, val
);
5415 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5417 if (is_guest_mode(vcpu
)) {
5418 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5419 unsigned long orig_val
= val
;
5421 /* analogously to handle_set_cr0 */
5422 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5423 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5424 if (kvm_set_cr4(vcpu
, val
))
5426 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5429 return kvm_set_cr4(vcpu
, val
);
5432 static int handle_desc(struct kvm_vcpu
*vcpu
)
5434 WARN_ON(!(vcpu
->arch
.cr4
& X86_CR4_UMIP
));
5435 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5438 static int handle_cr(struct kvm_vcpu
*vcpu
)
5440 unsigned long exit_qualification
, val
;
5446 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5447 cr
= exit_qualification
& 15;
5448 reg
= (exit_qualification
>> 8) & 15;
5449 switch ((exit_qualification
>> 4) & 3) {
5450 case 0: /* mov to cr */
5451 val
= kvm_register_readl(vcpu
, reg
);
5452 trace_kvm_cr_write(cr
, val
);
5455 err
= handle_set_cr0(vcpu
, val
);
5456 return kvm_complete_insn_gp(vcpu
, err
);
5458 WARN_ON_ONCE(enable_unrestricted_guest
);
5459 err
= kvm_set_cr3(vcpu
, val
);
5460 return kvm_complete_insn_gp(vcpu
, err
);
5462 err
= handle_set_cr4(vcpu
, val
);
5463 return kvm_complete_insn_gp(vcpu
, err
);
5465 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5467 err
= kvm_set_cr8(vcpu
, cr8
);
5468 ret
= kvm_complete_insn_gp(vcpu
, err
);
5469 if (lapic_in_kernel(vcpu
))
5471 if (cr8_prev
<= cr8
)
5474 * TODO: we might be squashing a
5475 * KVM_GUESTDBG_SINGLESTEP-triggered
5476 * KVM_EXIT_DEBUG here.
5478 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5484 WARN_ONCE(1, "Guest should always own CR0.TS");
5485 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5486 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5487 return kvm_skip_emulated_instruction(vcpu
);
5488 case 1: /*mov from cr*/
5491 WARN_ON_ONCE(enable_unrestricted_guest
);
5492 val
= kvm_read_cr3(vcpu
);
5493 kvm_register_write(vcpu
, reg
, val
);
5494 trace_kvm_cr_read(cr
, val
);
5495 return kvm_skip_emulated_instruction(vcpu
);
5497 val
= kvm_get_cr8(vcpu
);
5498 kvm_register_write(vcpu
, reg
, val
);
5499 trace_kvm_cr_read(cr
, val
);
5500 return kvm_skip_emulated_instruction(vcpu
);
5504 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5505 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5506 kvm_lmsw(vcpu
, val
);
5508 return kvm_skip_emulated_instruction(vcpu
);
5512 vcpu
->run
->exit_reason
= 0;
5513 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5514 (int)(exit_qualification
>> 4) & 3, cr
);
5518 static int handle_dr(struct kvm_vcpu
*vcpu
)
5520 unsigned long exit_qualification
;
5523 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5524 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5526 /* First, if DR does not exist, trigger UD */
5527 if (!kvm_require_dr(vcpu
, dr
))
5530 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5531 if (!kvm_require_cpl(vcpu
, 0))
5533 dr7
= vmcs_readl(GUEST_DR7
);
5536 * As the vm-exit takes precedence over the debug trap, we
5537 * need to emulate the latter, either for the host or the
5538 * guest debugging itself.
5540 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5541 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5542 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5543 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5544 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5545 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5548 vcpu
->arch
.dr6
&= ~15;
5549 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5550 kvm_queue_exception(vcpu
, DB_VECTOR
);
5555 if (vcpu
->guest_debug
== 0) {
5556 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5557 CPU_BASED_MOV_DR_EXITING
);
5560 * No more DR vmexits; force a reload of the debug registers
5561 * and reenter on this instruction. The next vmexit will
5562 * retrieve the full state of the debug registers.
5564 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5568 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5569 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5572 if (kvm_get_dr(vcpu
, dr
, &val
))
5574 kvm_register_write(vcpu
, reg
, val
);
5576 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5579 return kvm_skip_emulated_instruction(vcpu
);
5582 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5584 return vcpu
->arch
.dr6
;
5587 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5591 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5593 get_debugreg(vcpu
->arch
.db
[0], 0);
5594 get_debugreg(vcpu
->arch
.db
[1], 1);
5595 get_debugreg(vcpu
->arch
.db
[2], 2);
5596 get_debugreg(vcpu
->arch
.db
[3], 3);
5597 get_debugreg(vcpu
->arch
.dr6
, 6);
5598 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5600 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5601 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5604 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5606 vmcs_writel(GUEST_DR7
, val
);
5609 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5611 return kvm_emulate_cpuid(vcpu
);
5614 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5616 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5617 struct msr_data msr_info
;
5619 msr_info
.index
= ecx
;
5620 msr_info
.host_initiated
= false;
5621 if (vmx_get_msr(vcpu
, &msr_info
)) {
5622 trace_kvm_msr_read_ex(ecx
);
5623 kvm_inject_gp(vcpu
, 0);
5627 trace_kvm_msr_read(ecx
, msr_info
.data
);
5629 /* FIXME: handling of bits 32:63 of rax, rdx */
5630 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5631 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5632 return kvm_skip_emulated_instruction(vcpu
);
5635 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5637 struct msr_data msr
;
5638 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5639 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5640 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5644 msr
.host_initiated
= false;
5645 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5646 trace_kvm_msr_write_ex(ecx
, data
);
5647 kvm_inject_gp(vcpu
, 0);
5651 trace_kvm_msr_write(ecx
, data
);
5652 return kvm_skip_emulated_instruction(vcpu
);
5655 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5657 kvm_apic_update_ppr(vcpu
);
5661 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5663 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5664 CPU_BASED_VIRTUAL_INTR_PENDING
);
5666 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5668 ++vcpu
->stat
.irq_window_exits
;
5672 static int handle_halt(struct kvm_vcpu
*vcpu
)
5674 return kvm_emulate_halt(vcpu
);
5677 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5679 return kvm_emulate_hypercall(vcpu
);
5682 static int handle_invd(struct kvm_vcpu
*vcpu
)
5684 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5687 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5689 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5691 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5692 return kvm_skip_emulated_instruction(vcpu
);
5695 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5699 err
= kvm_rdpmc(vcpu
);
5700 return kvm_complete_insn_gp(vcpu
, err
);
5703 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5705 return kvm_emulate_wbinvd(vcpu
);
5708 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5710 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5711 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5713 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5714 return kvm_skip_emulated_instruction(vcpu
);
5718 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5720 kvm_skip_emulated_instruction(vcpu
);
5721 WARN(1, "this should never happen\n");
5725 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5727 kvm_skip_emulated_instruction(vcpu
);
5728 WARN(1, "this should never happen\n");
5732 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5734 if (likely(fasteoi
)) {
5735 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5736 int access_type
, offset
;
5738 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5739 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5741 * Sane guest uses MOV to write EOI, with written value
5742 * not cared. So make a short-circuit here by avoiding
5743 * heavy instruction emulation.
5745 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5746 (offset
== APIC_EOI
)) {
5747 kvm_lapic_set_eoi(vcpu
);
5748 return kvm_skip_emulated_instruction(vcpu
);
5751 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5754 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5756 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5757 int vector
= exit_qualification
& 0xff;
5759 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5760 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5764 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5766 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5767 u32 offset
= exit_qualification
& 0xfff;
5769 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5770 kvm_apic_write_nodecode(vcpu
, offset
);
5774 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5776 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5777 unsigned long exit_qualification
;
5778 bool has_error_code
= false;
5781 int reason
, type
, idt_v
, idt_index
;
5783 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5784 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5785 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5787 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5789 reason
= (u32
)exit_qualification
>> 30;
5790 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5792 case INTR_TYPE_NMI_INTR
:
5793 vcpu
->arch
.nmi_injected
= false;
5794 vmx_set_nmi_mask(vcpu
, true);
5796 case INTR_TYPE_EXT_INTR
:
5797 case INTR_TYPE_SOFT_INTR
:
5798 kvm_clear_interrupt_queue(vcpu
);
5800 case INTR_TYPE_HARD_EXCEPTION
:
5801 if (vmx
->idt_vectoring_info
&
5802 VECTORING_INFO_DELIVER_CODE_MASK
) {
5803 has_error_code
= true;
5805 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5808 case INTR_TYPE_SOFT_EXCEPTION
:
5809 kvm_clear_exception_queue(vcpu
);
5815 tss_selector
= exit_qualification
;
5817 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5818 type
!= INTR_TYPE_EXT_INTR
&&
5819 type
!= INTR_TYPE_NMI_INTR
))
5820 skip_emulated_instruction(vcpu
);
5822 if (kvm_task_switch(vcpu
, tss_selector
,
5823 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5824 has_error_code
, error_code
) == EMULATE_FAIL
) {
5825 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5826 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5827 vcpu
->run
->internal
.ndata
= 0;
5832 * TODO: What about debug traps on tss switch?
5833 * Are we supposed to inject them and update dr6?
5839 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5841 unsigned long exit_qualification
;
5845 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5848 * EPT violation happened while executing iret from NMI,
5849 * "blocked by NMI" bit has to be set before next VM entry.
5850 * There are errata that may cause this bit to not be set:
5853 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5855 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5856 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5858 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5859 trace_kvm_page_fault(gpa
, exit_qualification
);
5861 /* Is it a read fault? */
5862 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
5863 ? PFERR_USER_MASK
: 0;
5864 /* Is it a write fault? */
5865 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
5866 ? PFERR_WRITE_MASK
: 0;
5867 /* Is it a fetch fault? */
5868 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
5869 ? PFERR_FETCH_MASK
: 0;
5870 /* ept page table entry is present? */
5871 error_code
|= (exit_qualification
&
5872 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
5873 EPT_VIOLATION_EXECUTABLE
))
5874 ? PFERR_PRESENT_MASK
: 0;
5876 error_code
|= (exit_qualification
& 0x100) != 0 ?
5877 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
5879 vcpu
->arch
.exit_qualification
= exit_qualification
;
5880 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5883 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5888 * A nested guest cannot optimize MMIO vmexits, because we have an
5889 * nGPA here instead of the required GPA.
5891 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5892 if (!is_guest_mode(vcpu
) &&
5893 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5894 trace_kvm_fast_mmio(gpa
);
5896 * Doing kvm_skip_emulated_instruction() depends on undefined
5897 * behavior: Intel's manual doesn't mandate
5898 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5899 * occurs and while on real hardware it was observed to be set,
5900 * other hypervisors (namely Hyper-V) don't set it, we end up
5901 * advancing IP with some random value. Disable fast mmio when
5902 * running nested and keep it for real hardware in hope that
5903 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5905 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
))
5906 return kvm_skip_emulated_instruction(vcpu
);
5908 return kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
) ==
5912 return kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
5915 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5917 WARN_ON_ONCE(!enable_vnmi
);
5918 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5919 CPU_BASED_VIRTUAL_NMI_PENDING
);
5920 ++vcpu
->stat
.nmi_window_exits
;
5921 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5926 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5928 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5929 enum emulation_result err
= EMULATE_DONE
;
5932 bool intr_window_requested
;
5933 unsigned count
= 130;
5936 * We should never reach the point where we are emulating L2
5937 * due to invalid guest state as that means we incorrectly
5938 * allowed a nested VMEntry with an invalid vmcs12.
5940 WARN_ON_ONCE(vmx
->emulation_required
&& vmx
->nested
.nested_run_pending
);
5942 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5943 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5945 while (vmx
->emulation_required
&& count
-- != 0) {
5946 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5947 return handle_interrupt_window(&vmx
->vcpu
);
5949 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
5952 err
= kvm_emulate_instruction(vcpu
, 0);
5954 if (err
== EMULATE_USER_EXIT
) {
5955 ++vcpu
->stat
.mmio_exits
;
5960 if (err
!= EMULATE_DONE
)
5961 goto emulation_error
;
5963 if (vmx
->emulation_required
&& !vmx
->rmode
.vm86_active
&&
5964 vcpu
->arch
.exception
.pending
)
5965 goto emulation_error
;
5967 if (vcpu
->arch
.halt_request
) {
5968 vcpu
->arch
.halt_request
= 0;
5969 ret
= kvm_vcpu_halt(vcpu
);
5973 if (signal_pending(current
))
5983 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5984 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5985 vcpu
->run
->internal
.ndata
= 0;
5989 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5991 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5992 int old
= vmx
->ple_window
;
5994 vmx
->ple_window
= __grow_ple_window(old
, ple_window
,
5998 if (vmx
->ple_window
!= old
)
5999 vmx
->ple_window_dirty
= true;
6001 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6004 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6006 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6007 int old
= vmx
->ple_window
;
6009 vmx
->ple_window
= __shrink_ple_window(old
, ple_window
,
6013 if (vmx
->ple_window
!= old
)
6014 vmx
->ple_window_dirty
= true;
6016 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6020 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6022 static void wakeup_handler(void)
6024 struct kvm_vcpu
*vcpu
;
6025 int cpu
= smp_processor_id();
6027 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6028 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6029 blocked_vcpu_list
) {
6030 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6032 if (pi_test_on(pi_desc
) == 1)
6033 kvm_vcpu_kick(vcpu
);
6035 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6038 static void vmx_enable_tdp(void)
6040 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6041 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6042 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6043 0ull, VMX_EPT_EXECUTABLE_MASK
,
6044 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6045 VMX_EPT_RWX_MASK
, 0ull);
6047 ept_set_mmio_spte_mask();
6052 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6053 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6055 static int handle_pause(struct kvm_vcpu
*vcpu
)
6057 if (!kvm_pause_in_guest(vcpu
->kvm
))
6058 grow_ple_window(vcpu
);
6061 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6062 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6063 * never set PAUSE_EXITING and just set PLE if supported,
6064 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6066 kvm_vcpu_on_spin(vcpu
, true);
6067 return kvm_skip_emulated_instruction(vcpu
);
6070 static int handle_nop(struct kvm_vcpu
*vcpu
)
6072 return kvm_skip_emulated_instruction(vcpu
);
6075 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6077 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6078 return handle_nop(vcpu
);
6081 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6083 kvm_queue_exception(vcpu
, UD_VECTOR
);
6087 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6092 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6094 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6095 return handle_nop(vcpu
);
6099 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6100 * set the success or error code of an emulated VMX instruction (as specified
6101 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
6104 static int nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6106 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6107 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6108 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6109 return kvm_skip_emulated_instruction(vcpu
);
6112 static int nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6114 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6115 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6116 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6118 return kvm_skip_emulated_instruction(vcpu
);
6121 static int nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6122 u32 vm_instruction_error
)
6124 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6127 * failValid writes the error number to the current VMCS, which
6128 * can't be done if there isn't a current VMCS.
6130 if (vmx
->nested
.current_vmptr
== -1ull && !vmx
->nested
.hv_evmcs
)
6131 return nested_vmx_failInvalid(vcpu
);
6133 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6134 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6135 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6137 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6139 * We don't need to force a shadow sync because
6140 * VM_INSTRUCTION_ERROR is not shadowed
6142 return kvm_skip_emulated_instruction(vcpu
);
6145 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6147 /* TODO: not to reset guest simply here. */
6148 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6149 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6152 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6154 struct vcpu_vmx
*vmx
=
6155 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6157 vmx
->nested
.preemption_timer_expired
= true;
6158 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6159 kvm_vcpu_kick(&vmx
->vcpu
);
6161 return HRTIMER_NORESTART
;
6165 * Decode the memory-address operand of a vmx instruction, as recorded on an
6166 * exit caused by such an instruction (run by a guest hypervisor).
6167 * On success, returns 0. When the operand is invalid, returns 1 and throws
6170 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6171 unsigned long exit_qualification
,
6172 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6176 struct kvm_segment s
;
6179 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6180 * Execution", on an exit, vmx_instruction_info holds most of the
6181 * addressing components of the operand. Only the displacement part
6182 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6183 * For how an actual address is calculated from all these components,
6184 * refer to Vol. 1, "Operand Addressing".
6186 int scaling
= vmx_instruction_info
& 3;
6187 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6188 bool is_reg
= vmx_instruction_info
& (1u << 10);
6189 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6190 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6191 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6192 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6193 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6196 kvm_queue_exception(vcpu
, UD_VECTOR
);
6200 /* Addr = segment_base + offset */
6201 /* offset = base + [index * scale] + displacement */
6202 off
= exit_qualification
; /* holds the displacement */
6204 off
+= kvm_register_read(vcpu
, base_reg
);
6206 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6207 vmx_get_segment(vcpu
, &s
, seg_reg
);
6208 *ret
= s
.base
+ off
;
6210 if (addr_size
== 1) /* 32 bit */
6213 /* Checks for #GP/#SS exceptions. */
6215 if (is_long_mode(vcpu
)) {
6216 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6217 * non-canonical form. This is the only check on the memory
6218 * destination for long mode!
6220 exn
= is_noncanonical_address(*ret
, vcpu
);
6221 } else if (is_protmode(vcpu
)) {
6222 /* Protected mode: apply checks for segment validity in the
6224 * - segment type check (#GP(0) may be thrown)
6225 * - usability check (#GP(0)/#SS(0))
6226 * - limit check (#GP(0)/#SS(0))
6229 /* #GP(0) if the destination operand is located in a
6230 * read-only data segment or any code segment.
6232 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6234 /* #GP(0) if the source operand is located in an
6235 * execute-only code segment
6237 exn
= ((s
.type
& 0xa) == 8);
6239 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6242 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6244 exn
= (s
.unusable
!= 0);
6245 /* Protected mode: #GP(0)/#SS(0) if the memory
6246 * operand is outside the segment limit.
6248 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6251 kvm_queue_exception_e(vcpu
,
6252 seg_reg
== VCPU_SREG_SS
?
6253 SS_VECTOR
: GP_VECTOR
,
6261 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
6264 struct x86_exception e
;
6266 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6267 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6270 if (kvm_read_guest_virt(vcpu
, gva
, vmpointer
, sizeof(*vmpointer
), &e
)) {
6271 kvm_inject_page_fault(vcpu
, &e
);
6279 * Allocate a shadow VMCS and associate it with the currently loaded
6280 * VMCS, unless such a shadow VMCS already exists. The newly allocated
6281 * VMCS is also VMCLEARed, so that it is ready for use.
6283 static struct vmcs
*alloc_shadow_vmcs(struct kvm_vcpu
*vcpu
)
6285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6286 struct loaded_vmcs
*loaded_vmcs
= vmx
->loaded_vmcs
;
6289 * We should allocate a shadow vmcs for vmcs01 only when L1
6290 * executes VMXON and free it when L1 executes VMXOFF.
6291 * As it is invalid to execute VMXON twice, we shouldn't reach
6292 * here when vmcs01 already have an allocated shadow vmcs.
6294 WARN_ON(loaded_vmcs
== &vmx
->vmcs01
&& loaded_vmcs
->shadow_vmcs
);
6296 if (!loaded_vmcs
->shadow_vmcs
) {
6297 loaded_vmcs
->shadow_vmcs
= alloc_vmcs(true);
6298 if (loaded_vmcs
->shadow_vmcs
)
6299 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
6301 return loaded_vmcs
->shadow_vmcs
;
6304 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
6306 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6309 r
= alloc_loaded_vmcs(&vmx
->nested
.vmcs02
);
6313 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
6314 if (!vmx
->nested
.cached_vmcs12
)
6315 goto out_cached_vmcs12
;
6317 vmx
->nested
.cached_shadow_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
6318 if (!vmx
->nested
.cached_shadow_vmcs12
)
6319 goto out_cached_shadow_vmcs12
;
6321 if (enable_shadow_vmcs
&& !alloc_shadow_vmcs(vcpu
))
6322 goto out_shadow_vmcs
;
6324 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6325 HRTIMER_MODE_REL_PINNED
);
6326 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6328 vmx
->nested
.vpid02
= allocate_vpid();
6330 vmx
->nested
.vmcs02_initialized
= false;
6331 vmx
->nested
.vmxon
= true;
6335 kfree(vmx
->nested
.cached_shadow_vmcs12
);
6337 out_cached_shadow_vmcs12
:
6338 kfree(vmx
->nested
.cached_vmcs12
);
6341 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
6348 * Emulate the VMXON instruction.
6349 * Currently, we just remember that VMX is active, and do not save or even
6350 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6351 * do not currently need to store anything in that guest-allocated memory
6352 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6353 * argument is different from the VMXON pointer (which the spec says they do).
6355 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6360 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6361 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6362 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6365 * The Intel VMX Instruction Reference lists a bunch of bits that are
6366 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
6367 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
6368 * Otherwise, we should fail with #UD. But most faulting conditions
6369 * have already been checked by hardware, prior to the VM-exit for
6370 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
6371 * that bit set to 1 in non-root mode.
6373 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
6374 kvm_queue_exception(vcpu
, UD_VECTOR
);
6378 /* CPL=0 must be checked manually. */
6379 if (vmx_get_cpl(vcpu
)) {
6380 kvm_inject_gp(vcpu
, 0);
6384 if (vmx
->nested
.vmxon
)
6385 return nested_vmx_failValid(vcpu
,
6386 VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6388 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6389 != VMXON_NEEDED_FEATURES
) {
6390 kvm_inject_gp(vcpu
, 0);
6394 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
6399 * The first 4 bytes of VMXON region contain the supported
6400 * VMCS revision identifier
6402 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
6403 * which replaces physical address width with 32
6405 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
)))
6406 return nested_vmx_failInvalid(vcpu
);
6408 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
6409 if (is_error_page(page
))
6410 return nested_vmx_failInvalid(vcpu
);
6412 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
6414 kvm_release_page_clean(page
);
6415 return nested_vmx_failInvalid(vcpu
);
6418 kvm_release_page_clean(page
);
6420 vmx
->nested
.vmxon_ptr
= vmptr
;
6421 ret
= enter_vmx_operation(vcpu
);
6425 return nested_vmx_succeed(vcpu
);
6429 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6430 * for running VMX instructions (except VMXON, whose prerequisites are
6431 * slightly different). It also specifies what exception to inject otherwise.
6432 * Note that many of these exceptions have priority over VM exits, so they
6433 * don't have to be checked again here.
6435 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6437 if (!to_vmx(vcpu
)->nested
.vmxon
) {
6438 kvm_queue_exception(vcpu
, UD_VECTOR
);
6442 if (vmx_get_cpl(vcpu
)) {
6443 kvm_inject_gp(vcpu
, 0);
6450 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
6452 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
6453 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6456 static inline void nested_release_evmcs(struct kvm_vcpu
*vcpu
)
6458 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6460 if (!vmx
->nested
.hv_evmcs
)
6463 kunmap(vmx
->nested
.hv_evmcs_page
);
6464 kvm_release_page_dirty(vmx
->nested
.hv_evmcs_page
);
6465 vmx
->nested
.hv_evmcs_vmptr
= -1ull;
6466 vmx
->nested
.hv_evmcs_page
= NULL
;
6467 vmx
->nested
.hv_evmcs
= NULL
;
6470 static inline void nested_release_vmcs12(struct kvm_vcpu
*vcpu
)
6472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6474 if (vmx
->nested
.current_vmptr
== -1ull)
6477 if (enable_shadow_vmcs
) {
6478 /* copy to memory all shadowed fields in case
6479 they were modified */
6480 copy_shadow_to_vmcs12(vmx
);
6481 vmx
->nested
.need_vmcs12_sync
= false;
6482 vmx_disable_shadow_vmcs(vmx
);
6484 vmx
->nested
.posted_intr_nv
= -1;
6486 /* Flush VMCS12 to guest memory */
6487 kvm_vcpu_write_guest_page(vcpu
,
6488 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
6489 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
6491 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
6493 vmx
->nested
.current_vmptr
= -1ull;
6497 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6498 * just stops using VMX.
6500 static void free_nested(struct kvm_vcpu
*vcpu
)
6502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6504 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
6507 vmx
->nested
.vmxon
= false;
6508 vmx
->nested
.smm
.vmxon
= false;
6509 free_vpid(vmx
->nested
.vpid02
);
6510 vmx
->nested
.posted_intr_nv
= -1;
6511 vmx
->nested
.current_vmptr
= -1ull;
6512 if (enable_shadow_vmcs
) {
6513 vmx_disable_shadow_vmcs(vmx
);
6514 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
6515 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
6516 vmx
->vmcs01
.shadow_vmcs
= NULL
;
6518 kfree(vmx
->nested
.cached_vmcs12
);
6519 kfree(vmx
->nested
.cached_shadow_vmcs12
);
6520 /* Unpin physical memory we referred to in the vmcs02 */
6521 if (vmx
->nested
.apic_access_page
) {
6522 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
6523 vmx
->nested
.apic_access_page
= NULL
;
6525 if (vmx
->nested
.virtual_apic_page
) {
6526 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
6527 vmx
->nested
.virtual_apic_page
= NULL
;
6529 if (vmx
->nested
.pi_desc_page
) {
6530 kunmap(vmx
->nested
.pi_desc_page
);
6531 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
6532 vmx
->nested
.pi_desc_page
= NULL
;
6533 vmx
->nested
.pi_desc
= NULL
;
6536 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
6538 nested_release_evmcs(vcpu
);
6540 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
6543 /* Emulate the VMXOFF instruction */
6544 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6546 if (!nested_vmx_check_permission(vcpu
))
6549 return nested_vmx_succeed(vcpu
);
6552 /* Emulate the VMCLEAR instruction */
6553 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6555 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6559 if (!nested_vmx_check_permission(vcpu
))
6562 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
6565 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
)))
6566 return nested_vmx_failValid(vcpu
,
6567 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6569 if (vmptr
== vmx
->nested
.vmxon_ptr
)
6570 return nested_vmx_failValid(vcpu
,
6571 VMXERR_VMCLEAR_VMXON_POINTER
);
6573 if (vmx
->nested
.hv_evmcs_page
) {
6574 if (vmptr
== vmx
->nested
.hv_evmcs_vmptr
)
6575 nested_release_evmcs(vcpu
);
6577 if (vmptr
== vmx
->nested
.current_vmptr
)
6578 nested_release_vmcs12(vcpu
);
6580 kvm_vcpu_write_guest(vcpu
,
6581 vmptr
+ offsetof(struct vmcs12
,
6583 &zero
, sizeof(zero
));
6586 return nested_vmx_succeed(vcpu
);
6589 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6591 /* Emulate the VMLAUNCH instruction */
6592 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6594 return nested_vmx_run(vcpu
, true);
6597 /* Emulate the VMRESUME instruction */
6598 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6601 return nested_vmx_run(vcpu
, false);
6604 static int copy_enlightened_to_vmcs12(struct vcpu_vmx
*vmx
)
6606 struct vmcs12
*vmcs12
= vmx
->nested
.cached_vmcs12
;
6607 struct hv_enlightened_vmcs
*evmcs
= vmx
->nested
.hv_evmcs
;
6609 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
6610 vmcs12
->tpr_threshold
= evmcs
->tpr_threshold
;
6611 vmcs12
->guest_rip
= evmcs
->guest_rip
;
6613 if (unlikely(!(evmcs
->hv_clean_fields
&
6614 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC
))) {
6615 vmcs12
->guest_rsp
= evmcs
->guest_rsp
;
6616 vmcs12
->guest_rflags
= evmcs
->guest_rflags
;
6617 vmcs12
->guest_interruptibility_info
=
6618 evmcs
->guest_interruptibility_info
;
6621 if (unlikely(!(evmcs
->hv_clean_fields
&
6622 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC
))) {
6623 vmcs12
->cpu_based_vm_exec_control
=
6624 evmcs
->cpu_based_vm_exec_control
;
6627 if (unlikely(!(evmcs
->hv_clean_fields
&
6628 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC
))) {
6629 vmcs12
->exception_bitmap
= evmcs
->exception_bitmap
;
6632 if (unlikely(!(evmcs
->hv_clean_fields
&
6633 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY
))) {
6634 vmcs12
->vm_entry_controls
= evmcs
->vm_entry_controls
;
6637 if (unlikely(!(evmcs
->hv_clean_fields
&
6638 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT
))) {
6639 vmcs12
->vm_entry_intr_info_field
=
6640 evmcs
->vm_entry_intr_info_field
;
6641 vmcs12
->vm_entry_exception_error_code
=
6642 evmcs
->vm_entry_exception_error_code
;
6643 vmcs12
->vm_entry_instruction_len
=
6644 evmcs
->vm_entry_instruction_len
;
6647 if (unlikely(!(evmcs
->hv_clean_fields
&
6648 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1
))) {
6649 vmcs12
->host_ia32_pat
= evmcs
->host_ia32_pat
;
6650 vmcs12
->host_ia32_efer
= evmcs
->host_ia32_efer
;
6651 vmcs12
->host_cr0
= evmcs
->host_cr0
;
6652 vmcs12
->host_cr3
= evmcs
->host_cr3
;
6653 vmcs12
->host_cr4
= evmcs
->host_cr4
;
6654 vmcs12
->host_ia32_sysenter_esp
= evmcs
->host_ia32_sysenter_esp
;
6655 vmcs12
->host_ia32_sysenter_eip
= evmcs
->host_ia32_sysenter_eip
;
6656 vmcs12
->host_rip
= evmcs
->host_rip
;
6657 vmcs12
->host_ia32_sysenter_cs
= evmcs
->host_ia32_sysenter_cs
;
6658 vmcs12
->host_es_selector
= evmcs
->host_es_selector
;
6659 vmcs12
->host_cs_selector
= evmcs
->host_cs_selector
;
6660 vmcs12
->host_ss_selector
= evmcs
->host_ss_selector
;
6661 vmcs12
->host_ds_selector
= evmcs
->host_ds_selector
;
6662 vmcs12
->host_fs_selector
= evmcs
->host_fs_selector
;
6663 vmcs12
->host_gs_selector
= evmcs
->host_gs_selector
;
6664 vmcs12
->host_tr_selector
= evmcs
->host_tr_selector
;
6667 if (unlikely(!(evmcs
->hv_clean_fields
&
6668 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1
))) {
6669 vmcs12
->pin_based_vm_exec_control
=
6670 evmcs
->pin_based_vm_exec_control
;
6671 vmcs12
->vm_exit_controls
= evmcs
->vm_exit_controls
;
6672 vmcs12
->secondary_vm_exec_control
=
6673 evmcs
->secondary_vm_exec_control
;
6676 if (unlikely(!(evmcs
->hv_clean_fields
&
6677 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP
))) {
6678 vmcs12
->io_bitmap_a
= evmcs
->io_bitmap_a
;
6679 vmcs12
->io_bitmap_b
= evmcs
->io_bitmap_b
;
6682 if (unlikely(!(evmcs
->hv_clean_fields
&
6683 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP
))) {
6684 vmcs12
->msr_bitmap
= evmcs
->msr_bitmap
;
6687 if (unlikely(!(evmcs
->hv_clean_fields
&
6688 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2
))) {
6689 vmcs12
->guest_es_base
= evmcs
->guest_es_base
;
6690 vmcs12
->guest_cs_base
= evmcs
->guest_cs_base
;
6691 vmcs12
->guest_ss_base
= evmcs
->guest_ss_base
;
6692 vmcs12
->guest_ds_base
= evmcs
->guest_ds_base
;
6693 vmcs12
->guest_fs_base
= evmcs
->guest_fs_base
;
6694 vmcs12
->guest_gs_base
= evmcs
->guest_gs_base
;
6695 vmcs12
->guest_ldtr_base
= evmcs
->guest_ldtr_base
;
6696 vmcs12
->guest_tr_base
= evmcs
->guest_tr_base
;
6697 vmcs12
->guest_gdtr_base
= evmcs
->guest_gdtr_base
;
6698 vmcs12
->guest_idtr_base
= evmcs
->guest_idtr_base
;
6699 vmcs12
->guest_es_limit
= evmcs
->guest_es_limit
;
6700 vmcs12
->guest_cs_limit
= evmcs
->guest_cs_limit
;
6701 vmcs12
->guest_ss_limit
= evmcs
->guest_ss_limit
;
6702 vmcs12
->guest_ds_limit
= evmcs
->guest_ds_limit
;
6703 vmcs12
->guest_fs_limit
= evmcs
->guest_fs_limit
;
6704 vmcs12
->guest_gs_limit
= evmcs
->guest_gs_limit
;
6705 vmcs12
->guest_ldtr_limit
= evmcs
->guest_ldtr_limit
;
6706 vmcs12
->guest_tr_limit
= evmcs
->guest_tr_limit
;
6707 vmcs12
->guest_gdtr_limit
= evmcs
->guest_gdtr_limit
;
6708 vmcs12
->guest_idtr_limit
= evmcs
->guest_idtr_limit
;
6709 vmcs12
->guest_es_ar_bytes
= evmcs
->guest_es_ar_bytes
;
6710 vmcs12
->guest_cs_ar_bytes
= evmcs
->guest_cs_ar_bytes
;
6711 vmcs12
->guest_ss_ar_bytes
= evmcs
->guest_ss_ar_bytes
;
6712 vmcs12
->guest_ds_ar_bytes
= evmcs
->guest_ds_ar_bytes
;
6713 vmcs12
->guest_fs_ar_bytes
= evmcs
->guest_fs_ar_bytes
;
6714 vmcs12
->guest_gs_ar_bytes
= evmcs
->guest_gs_ar_bytes
;
6715 vmcs12
->guest_ldtr_ar_bytes
= evmcs
->guest_ldtr_ar_bytes
;
6716 vmcs12
->guest_tr_ar_bytes
= evmcs
->guest_tr_ar_bytes
;
6717 vmcs12
->guest_es_selector
= evmcs
->guest_es_selector
;
6718 vmcs12
->guest_cs_selector
= evmcs
->guest_cs_selector
;
6719 vmcs12
->guest_ss_selector
= evmcs
->guest_ss_selector
;
6720 vmcs12
->guest_ds_selector
= evmcs
->guest_ds_selector
;
6721 vmcs12
->guest_fs_selector
= evmcs
->guest_fs_selector
;
6722 vmcs12
->guest_gs_selector
= evmcs
->guest_gs_selector
;
6723 vmcs12
->guest_ldtr_selector
= evmcs
->guest_ldtr_selector
;
6724 vmcs12
->guest_tr_selector
= evmcs
->guest_tr_selector
;
6727 if (unlikely(!(evmcs
->hv_clean_fields
&
6728 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2
))) {
6729 vmcs12
->tsc_offset
= evmcs
->tsc_offset
;
6730 vmcs12
->virtual_apic_page_addr
= evmcs
->virtual_apic_page_addr
;
6731 vmcs12
->xss_exit_bitmap
= evmcs
->xss_exit_bitmap
;
6734 if (unlikely(!(evmcs
->hv_clean_fields
&
6735 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR
))) {
6736 vmcs12
->cr0_guest_host_mask
= evmcs
->cr0_guest_host_mask
;
6737 vmcs12
->cr4_guest_host_mask
= evmcs
->cr4_guest_host_mask
;
6738 vmcs12
->cr0_read_shadow
= evmcs
->cr0_read_shadow
;
6739 vmcs12
->cr4_read_shadow
= evmcs
->cr4_read_shadow
;
6740 vmcs12
->guest_cr0
= evmcs
->guest_cr0
;
6741 vmcs12
->guest_cr3
= evmcs
->guest_cr3
;
6742 vmcs12
->guest_cr4
= evmcs
->guest_cr4
;
6743 vmcs12
->guest_dr7
= evmcs
->guest_dr7
;
6746 if (unlikely(!(evmcs
->hv_clean_fields
&
6747 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER
))) {
6748 vmcs12
->host_fs_base
= evmcs
->host_fs_base
;
6749 vmcs12
->host_gs_base
= evmcs
->host_gs_base
;
6750 vmcs12
->host_tr_base
= evmcs
->host_tr_base
;
6751 vmcs12
->host_gdtr_base
= evmcs
->host_gdtr_base
;
6752 vmcs12
->host_idtr_base
= evmcs
->host_idtr_base
;
6753 vmcs12
->host_rsp
= evmcs
->host_rsp
;
6756 if (unlikely(!(evmcs
->hv_clean_fields
&
6757 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT
))) {
6758 vmcs12
->ept_pointer
= evmcs
->ept_pointer
;
6759 vmcs12
->virtual_processor_id
= evmcs
->virtual_processor_id
;
6762 if (unlikely(!(evmcs
->hv_clean_fields
&
6763 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1
))) {
6764 vmcs12
->vmcs_link_pointer
= evmcs
->vmcs_link_pointer
;
6765 vmcs12
->guest_ia32_debugctl
= evmcs
->guest_ia32_debugctl
;
6766 vmcs12
->guest_ia32_pat
= evmcs
->guest_ia32_pat
;
6767 vmcs12
->guest_ia32_efer
= evmcs
->guest_ia32_efer
;
6768 vmcs12
->guest_pdptr0
= evmcs
->guest_pdptr0
;
6769 vmcs12
->guest_pdptr1
= evmcs
->guest_pdptr1
;
6770 vmcs12
->guest_pdptr2
= evmcs
->guest_pdptr2
;
6771 vmcs12
->guest_pdptr3
= evmcs
->guest_pdptr3
;
6772 vmcs12
->guest_pending_dbg_exceptions
=
6773 evmcs
->guest_pending_dbg_exceptions
;
6774 vmcs12
->guest_sysenter_esp
= evmcs
->guest_sysenter_esp
;
6775 vmcs12
->guest_sysenter_eip
= evmcs
->guest_sysenter_eip
;
6776 vmcs12
->guest_bndcfgs
= evmcs
->guest_bndcfgs
;
6777 vmcs12
->guest_activity_state
= evmcs
->guest_activity_state
;
6778 vmcs12
->guest_sysenter_cs
= evmcs
->guest_sysenter_cs
;
6783 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
6784 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
6785 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
6786 * vmcs12->cr3_target_value0 = evmcs->cr3_target_value0;
6787 * vmcs12->cr3_target_value1 = evmcs->cr3_target_value1;
6788 * vmcs12->cr3_target_value2 = evmcs->cr3_target_value2;
6789 * vmcs12->cr3_target_value3 = evmcs->cr3_target_value3;
6790 * vmcs12->page_fault_error_code_mask =
6791 * evmcs->page_fault_error_code_mask;
6792 * vmcs12->page_fault_error_code_match =
6793 * evmcs->page_fault_error_code_match;
6794 * vmcs12->cr3_target_count = evmcs->cr3_target_count;
6795 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
6796 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
6797 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
6802 * vmcs12->guest_physical_address = evmcs->guest_physical_address;
6803 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
6804 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
6805 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
6806 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
6807 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
6808 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
6809 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
6810 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
6811 * vmcs12->exit_qualification = evmcs->exit_qualification;
6812 * vmcs12->guest_linear_address = evmcs->guest_linear_address;
6814 * Not present in struct vmcs12:
6815 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
6816 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
6817 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
6818 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
6824 static int copy_vmcs12_to_enlightened(struct vcpu_vmx
*vmx
)
6826 struct vmcs12
*vmcs12
= vmx
->nested
.cached_vmcs12
;
6827 struct hv_enlightened_vmcs
*evmcs
= vmx
->nested
.hv_evmcs
;
6830 * Should not be changed by KVM:
6832 * evmcs->host_es_selector = vmcs12->host_es_selector;
6833 * evmcs->host_cs_selector = vmcs12->host_cs_selector;
6834 * evmcs->host_ss_selector = vmcs12->host_ss_selector;
6835 * evmcs->host_ds_selector = vmcs12->host_ds_selector;
6836 * evmcs->host_fs_selector = vmcs12->host_fs_selector;
6837 * evmcs->host_gs_selector = vmcs12->host_gs_selector;
6838 * evmcs->host_tr_selector = vmcs12->host_tr_selector;
6839 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
6840 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
6841 * evmcs->host_cr0 = vmcs12->host_cr0;
6842 * evmcs->host_cr3 = vmcs12->host_cr3;
6843 * evmcs->host_cr4 = vmcs12->host_cr4;
6844 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
6845 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
6846 * evmcs->host_rip = vmcs12->host_rip;
6847 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
6848 * evmcs->host_fs_base = vmcs12->host_fs_base;
6849 * evmcs->host_gs_base = vmcs12->host_gs_base;
6850 * evmcs->host_tr_base = vmcs12->host_tr_base;
6851 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
6852 * evmcs->host_idtr_base = vmcs12->host_idtr_base;
6853 * evmcs->host_rsp = vmcs12->host_rsp;
6854 * sync_vmcs12() doesn't read these:
6855 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
6856 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
6857 * evmcs->msr_bitmap = vmcs12->msr_bitmap;
6858 * evmcs->ept_pointer = vmcs12->ept_pointer;
6859 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
6860 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
6861 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
6862 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
6863 * evmcs->cr3_target_value0 = vmcs12->cr3_target_value0;
6864 * evmcs->cr3_target_value1 = vmcs12->cr3_target_value1;
6865 * evmcs->cr3_target_value2 = vmcs12->cr3_target_value2;
6866 * evmcs->cr3_target_value3 = vmcs12->cr3_target_value3;
6867 * evmcs->tpr_threshold = vmcs12->tpr_threshold;
6868 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
6869 * evmcs->exception_bitmap = vmcs12->exception_bitmap;
6870 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
6871 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
6872 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
6873 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
6874 * evmcs->page_fault_error_code_mask =
6875 * vmcs12->page_fault_error_code_mask;
6876 * evmcs->page_fault_error_code_match =
6877 * vmcs12->page_fault_error_code_match;
6878 * evmcs->cr3_target_count = vmcs12->cr3_target_count;
6879 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
6880 * evmcs->tsc_offset = vmcs12->tsc_offset;
6881 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
6882 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
6883 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
6884 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
6885 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
6886 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
6887 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
6888 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
6890 * Not present in struct vmcs12:
6891 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
6892 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
6893 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
6894 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
6897 evmcs
->guest_es_selector
= vmcs12
->guest_es_selector
;
6898 evmcs
->guest_cs_selector
= vmcs12
->guest_cs_selector
;
6899 evmcs
->guest_ss_selector
= vmcs12
->guest_ss_selector
;
6900 evmcs
->guest_ds_selector
= vmcs12
->guest_ds_selector
;
6901 evmcs
->guest_fs_selector
= vmcs12
->guest_fs_selector
;
6902 evmcs
->guest_gs_selector
= vmcs12
->guest_gs_selector
;
6903 evmcs
->guest_ldtr_selector
= vmcs12
->guest_ldtr_selector
;
6904 evmcs
->guest_tr_selector
= vmcs12
->guest_tr_selector
;
6906 evmcs
->guest_es_limit
= vmcs12
->guest_es_limit
;
6907 evmcs
->guest_cs_limit
= vmcs12
->guest_cs_limit
;
6908 evmcs
->guest_ss_limit
= vmcs12
->guest_ss_limit
;
6909 evmcs
->guest_ds_limit
= vmcs12
->guest_ds_limit
;
6910 evmcs
->guest_fs_limit
= vmcs12
->guest_fs_limit
;
6911 evmcs
->guest_gs_limit
= vmcs12
->guest_gs_limit
;
6912 evmcs
->guest_ldtr_limit
= vmcs12
->guest_ldtr_limit
;
6913 evmcs
->guest_tr_limit
= vmcs12
->guest_tr_limit
;
6914 evmcs
->guest_gdtr_limit
= vmcs12
->guest_gdtr_limit
;
6915 evmcs
->guest_idtr_limit
= vmcs12
->guest_idtr_limit
;
6917 evmcs
->guest_es_ar_bytes
= vmcs12
->guest_es_ar_bytes
;
6918 evmcs
->guest_cs_ar_bytes
= vmcs12
->guest_cs_ar_bytes
;
6919 evmcs
->guest_ss_ar_bytes
= vmcs12
->guest_ss_ar_bytes
;
6920 evmcs
->guest_ds_ar_bytes
= vmcs12
->guest_ds_ar_bytes
;
6921 evmcs
->guest_fs_ar_bytes
= vmcs12
->guest_fs_ar_bytes
;
6922 evmcs
->guest_gs_ar_bytes
= vmcs12
->guest_gs_ar_bytes
;
6923 evmcs
->guest_ldtr_ar_bytes
= vmcs12
->guest_ldtr_ar_bytes
;
6924 evmcs
->guest_tr_ar_bytes
= vmcs12
->guest_tr_ar_bytes
;
6926 evmcs
->guest_es_base
= vmcs12
->guest_es_base
;
6927 evmcs
->guest_cs_base
= vmcs12
->guest_cs_base
;
6928 evmcs
->guest_ss_base
= vmcs12
->guest_ss_base
;
6929 evmcs
->guest_ds_base
= vmcs12
->guest_ds_base
;
6930 evmcs
->guest_fs_base
= vmcs12
->guest_fs_base
;
6931 evmcs
->guest_gs_base
= vmcs12
->guest_gs_base
;
6932 evmcs
->guest_ldtr_base
= vmcs12
->guest_ldtr_base
;
6933 evmcs
->guest_tr_base
= vmcs12
->guest_tr_base
;
6934 evmcs
->guest_gdtr_base
= vmcs12
->guest_gdtr_base
;
6935 evmcs
->guest_idtr_base
= vmcs12
->guest_idtr_base
;
6937 evmcs
->guest_ia32_pat
= vmcs12
->guest_ia32_pat
;
6938 evmcs
->guest_ia32_efer
= vmcs12
->guest_ia32_efer
;
6940 evmcs
->guest_pdptr0
= vmcs12
->guest_pdptr0
;
6941 evmcs
->guest_pdptr1
= vmcs12
->guest_pdptr1
;
6942 evmcs
->guest_pdptr2
= vmcs12
->guest_pdptr2
;
6943 evmcs
->guest_pdptr3
= vmcs12
->guest_pdptr3
;
6945 evmcs
->guest_pending_dbg_exceptions
=
6946 vmcs12
->guest_pending_dbg_exceptions
;
6947 evmcs
->guest_sysenter_esp
= vmcs12
->guest_sysenter_esp
;
6948 evmcs
->guest_sysenter_eip
= vmcs12
->guest_sysenter_eip
;
6950 evmcs
->guest_activity_state
= vmcs12
->guest_activity_state
;
6951 evmcs
->guest_sysenter_cs
= vmcs12
->guest_sysenter_cs
;
6953 evmcs
->guest_cr0
= vmcs12
->guest_cr0
;
6954 evmcs
->guest_cr3
= vmcs12
->guest_cr3
;
6955 evmcs
->guest_cr4
= vmcs12
->guest_cr4
;
6956 evmcs
->guest_dr7
= vmcs12
->guest_dr7
;
6958 evmcs
->guest_physical_address
= vmcs12
->guest_physical_address
;
6960 evmcs
->vm_instruction_error
= vmcs12
->vm_instruction_error
;
6961 evmcs
->vm_exit_reason
= vmcs12
->vm_exit_reason
;
6962 evmcs
->vm_exit_intr_info
= vmcs12
->vm_exit_intr_info
;
6963 evmcs
->vm_exit_intr_error_code
= vmcs12
->vm_exit_intr_error_code
;
6964 evmcs
->idt_vectoring_info_field
= vmcs12
->idt_vectoring_info_field
;
6965 evmcs
->idt_vectoring_error_code
= vmcs12
->idt_vectoring_error_code
;
6966 evmcs
->vm_exit_instruction_len
= vmcs12
->vm_exit_instruction_len
;
6967 evmcs
->vmx_instruction_info
= vmcs12
->vmx_instruction_info
;
6969 evmcs
->exit_qualification
= vmcs12
->exit_qualification
;
6971 evmcs
->guest_linear_address
= vmcs12
->guest_linear_address
;
6972 evmcs
->guest_rsp
= vmcs12
->guest_rsp
;
6973 evmcs
->guest_rflags
= vmcs12
->guest_rflags
;
6975 evmcs
->guest_interruptibility_info
=
6976 vmcs12
->guest_interruptibility_info
;
6977 evmcs
->cpu_based_vm_exec_control
= vmcs12
->cpu_based_vm_exec_control
;
6978 evmcs
->vm_entry_controls
= vmcs12
->vm_entry_controls
;
6979 evmcs
->vm_entry_intr_info_field
= vmcs12
->vm_entry_intr_info_field
;
6980 evmcs
->vm_entry_exception_error_code
=
6981 vmcs12
->vm_entry_exception_error_code
;
6982 evmcs
->vm_entry_instruction_len
= vmcs12
->vm_entry_instruction_len
;
6984 evmcs
->guest_rip
= vmcs12
->guest_rip
;
6986 evmcs
->guest_bndcfgs
= vmcs12
->guest_bndcfgs
;
6992 * Copy the writable VMCS shadow fields back to the VMCS12, in case
6993 * they have been modified by the L1 guest. Note that the "read-only"
6994 * VM-exit information fields are actually writable if the vCPU is
6995 * configured to support "VMWRITE to any supported field in the VMCS."
6997 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6999 const u16
*fields
[] = {
7000 shadow_read_write_fields
,
7001 shadow_read_only_fields
7003 const int max_fields
[] = {
7004 max_shadow_read_write_fields
,
7005 max_shadow_read_only_fields
7008 unsigned long field
;
7010 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7014 vmcs_load(shadow_vmcs
);
7016 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7017 for (i
= 0; i
< max_fields
[q
]; i
++) {
7018 field
= fields
[q
][i
];
7019 field_value
= __vmcs_readl(field
);
7020 vmcs12_write_any(get_vmcs12(&vmx
->vcpu
), field
, field_value
);
7023 * Skip the VM-exit information fields if they are read-only.
7025 if (!nested_cpu_has_vmwrite_any_field(&vmx
->vcpu
))
7029 vmcs_clear(shadow_vmcs
);
7030 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7035 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7037 const u16
*fields
[] = {
7038 shadow_read_write_fields
,
7039 shadow_read_only_fields
7041 const int max_fields
[] = {
7042 max_shadow_read_write_fields
,
7043 max_shadow_read_only_fields
7046 unsigned long field
;
7047 u64 field_value
= 0;
7048 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7050 vmcs_load(shadow_vmcs
);
7052 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7053 for (i
= 0; i
< max_fields
[q
]; i
++) {
7054 field
= fields
[q
][i
];
7055 vmcs12_read_any(get_vmcs12(&vmx
->vcpu
), field
, &field_value
);
7056 __vmcs_writel(field
, field_value
);
7060 vmcs_clear(shadow_vmcs
);
7061 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7064 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7066 unsigned long field
;
7068 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7069 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7071 struct vmcs12
*vmcs12
;
7073 if (!nested_vmx_check_permission(vcpu
))
7076 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull)
7077 return nested_vmx_failInvalid(vcpu
);
7079 if (!is_guest_mode(vcpu
))
7080 vmcs12
= get_vmcs12(vcpu
);
7083 * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
7084 * to shadowed-field sets the ALU flags for VMfailInvalid.
7086 if (get_vmcs12(vcpu
)->vmcs_link_pointer
== -1ull)
7087 return nested_vmx_failInvalid(vcpu
);
7088 vmcs12
= get_shadow_vmcs12(vcpu
);
7091 /* Decode instruction info and find the field to read */
7092 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7093 /* Read the field, zero-extended to a u64 field_value */
7094 if (vmcs12_read_any(vmcs12
, field
, &field_value
) < 0)
7095 return nested_vmx_failValid(vcpu
,
7096 VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7099 * Now copy part of this value to register or memory, as requested.
7100 * Note that the number of bits actually copied is 32 or 64 depending
7101 * on the guest's mode (32 or 64 bit), not on the given field's length.
7103 if (vmx_instruction_info
& (1u << 10)) {
7104 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7107 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7108 vmx_instruction_info
, true, &gva
))
7110 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
7111 kvm_write_guest_virt_system(vcpu
, gva
, &field_value
,
7112 (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7115 return nested_vmx_succeed(vcpu
);
7119 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7121 unsigned long field
;
7123 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7124 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7125 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7127 /* The value to write might be 32 or 64 bits, depending on L1's long
7128 * mode, and eventually we need to write that into a field of several
7129 * possible lengths. The code below first zero-extends the value to 64
7130 * bit (field_value), and then copies only the appropriate number of
7131 * bits into the vmcs12 field.
7133 u64 field_value
= 0;
7134 struct x86_exception e
;
7135 struct vmcs12
*vmcs12
;
7137 if (!nested_vmx_check_permission(vcpu
))
7140 if (vmx
->nested
.current_vmptr
== -1ull)
7141 return nested_vmx_failInvalid(vcpu
);
7143 if (vmx_instruction_info
& (1u << 10))
7144 field_value
= kvm_register_readl(vcpu
,
7145 (((vmx_instruction_info
) >> 3) & 0xf));
7147 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7148 vmx_instruction_info
, false, &gva
))
7150 if (kvm_read_guest_virt(vcpu
, gva
, &field_value
,
7151 (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7152 kvm_inject_page_fault(vcpu
, &e
);
7158 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7160 * If the vCPU supports "VMWRITE to any supported field in the
7161 * VMCS," then the "read-only" fields are actually read/write.
7163 if (vmcs_field_readonly(field
) &&
7164 !nested_cpu_has_vmwrite_any_field(vcpu
))
7165 return nested_vmx_failValid(vcpu
,
7166 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7168 if (!is_guest_mode(vcpu
))
7169 vmcs12
= get_vmcs12(vcpu
);
7172 * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
7173 * to shadowed-field sets the ALU flags for VMfailInvalid.
7175 if (get_vmcs12(vcpu
)->vmcs_link_pointer
== -1ull)
7176 return nested_vmx_failInvalid(vcpu
);
7177 vmcs12
= get_shadow_vmcs12(vcpu
);
7180 if (vmcs12_write_any(vmcs12
, field
, field_value
) < 0)
7181 return nested_vmx_failValid(vcpu
,
7182 VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7185 * Do not track vmcs12 dirty-state if in guest-mode
7186 * as we actually dirty shadow vmcs12 instead of vmcs12.
7188 if (!is_guest_mode(vcpu
)) {
7190 #define SHADOW_FIELD_RW(x) case x:
7191 #include "vmcs_shadow_fields.h"
7193 * The fields that can be updated by L1 without a vmexit are
7194 * always updated in the vmcs02, the others go down the slow
7195 * path of prepare_vmcs02.
7199 vmx
->nested
.dirty_vmcs12
= true;
7204 return nested_vmx_succeed(vcpu
);
7207 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7209 vmx
->nested
.current_vmptr
= vmptr
;
7210 if (enable_shadow_vmcs
) {
7211 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7212 SECONDARY_EXEC_SHADOW_VMCS
);
7213 vmcs_write64(VMCS_LINK_POINTER
,
7214 __pa(vmx
->vmcs01
.shadow_vmcs
));
7215 vmx
->nested
.need_vmcs12_sync
= true;
7217 vmx
->nested
.dirty_vmcs12
= true;
7220 /* Emulate the VMPTRLD instruction */
7221 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7223 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7226 if (!nested_vmx_check_permission(vcpu
))
7229 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7232 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
)))
7233 return nested_vmx_failValid(vcpu
,
7234 VMXERR_VMPTRLD_INVALID_ADDRESS
);
7236 if (vmptr
== vmx
->nested
.vmxon_ptr
)
7237 return nested_vmx_failValid(vcpu
,
7238 VMXERR_VMPTRLD_VMXON_POINTER
);
7240 /* Forbid normal VMPTRLD if Enlightened version was used */
7241 if (vmx
->nested
.hv_evmcs
)
7244 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7245 struct vmcs12
*new_vmcs12
;
7247 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7248 if (is_error_page(page
)) {
7250 * Reads from an unbacked page return all 1s,
7251 * which means that the 32 bits located at the
7252 * given physical address won't match the required
7253 * VMCS12_REVISION identifier.
7255 nested_vmx_failValid(vcpu
,
7256 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7257 return kvm_skip_emulated_instruction(vcpu
);
7259 new_vmcs12
= kmap(page
);
7260 if (new_vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
||
7261 (new_vmcs12
->hdr
.shadow_vmcs
&&
7262 !nested_cpu_has_vmx_shadow_vmcs(vcpu
))) {
7264 kvm_release_page_clean(page
);
7265 return nested_vmx_failValid(vcpu
,
7266 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7269 nested_release_vmcs12(vcpu
);
7272 * Load VMCS12 from guest memory since it is not already
7275 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7277 kvm_release_page_clean(page
);
7279 set_current_vmptr(vmx
, vmptr
);
7282 return nested_vmx_succeed(vcpu
);
7286 * This is an equivalent of the nested hypervisor executing the vmptrld
7289 static int nested_vmx_handle_enlightened_vmptrld(struct kvm_vcpu
*vcpu
,
7292 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7293 struct hv_vp_assist_page assist_page
;
7295 if (likely(!vmx
->nested
.enlightened_vmcs_enabled
))
7298 if (unlikely(!kvm_hv_get_assist_page(vcpu
, &assist_page
)))
7301 if (unlikely(!assist_page
.enlighten_vmentry
))
7304 if (unlikely(assist_page
.current_nested_vmcs
!=
7305 vmx
->nested
.hv_evmcs_vmptr
)) {
7307 if (!vmx
->nested
.hv_evmcs
)
7308 vmx
->nested
.current_vmptr
= -1ull;
7310 nested_release_evmcs(vcpu
);
7312 vmx
->nested
.hv_evmcs_page
= kvm_vcpu_gpa_to_page(
7313 vcpu
, assist_page
.current_nested_vmcs
);
7315 if (unlikely(is_error_page(vmx
->nested
.hv_evmcs_page
)))
7318 vmx
->nested
.hv_evmcs
= kmap(vmx
->nested
.hv_evmcs_page
);
7321 * Currently, KVM only supports eVMCS version 1
7322 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
7323 * value to first u32 field of eVMCS which should specify eVMCS
7326 * Guest should be aware of supported eVMCS versions by host by
7327 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
7328 * expected to set this CPUID leaf according to the value
7329 * returned in vmcs_version from nested_enable_evmcs().
7331 * However, it turns out that Microsoft Hyper-V fails to comply
7332 * to their own invented interface: When Hyper-V use eVMCS, it
7333 * just sets first u32 field of eVMCS to revision_id specified
7334 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
7335 * which is one of the supported versions specified in
7336 * CPUID.0x4000000A.EAX[0:15].
7338 * To overcome Hyper-V bug, we accept here either a supported
7339 * eVMCS version or VMCS12 revision_id as valid values for first
7340 * u32 field of eVMCS.
7342 if ((vmx
->nested
.hv_evmcs
->revision_id
!= KVM_EVMCS_VERSION
) &&
7343 (vmx
->nested
.hv_evmcs
->revision_id
!= VMCS12_REVISION
)) {
7344 nested_release_evmcs(vcpu
);
7348 vmx
->nested
.dirty_vmcs12
= true;
7350 * As we keep L2 state for one guest only 'hv_clean_fields' mask
7351 * can't be used when we switch between them. Reset it here for
7354 vmx
->nested
.hv_evmcs
->hv_clean_fields
&=
7355 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
;
7356 vmx
->nested
.hv_evmcs_vmptr
= assist_page
.current_nested_vmcs
;
7359 * Unlike normal vmcs12, enlightened vmcs12 is not fully
7360 * reloaded from guest's memory (read only fields, fields not
7361 * present in struct hv_enlightened_vmcs, ...). Make sure there
7365 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7366 memset(vmcs12
, 0, sizeof(*vmcs12
));
7367 vmcs12
->hdr
.revision_id
= VMCS12_REVISION
;
7374 /* Emulate the VMPTRST instruction */
7375 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7377 unsigned long exit_qual
= vmcs_readl(EXIT_QUALIFICATION
);
7378 u32 instr_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7379 gpa_t current_vmptr
= to_vmx(vcpu
)->nested
.current_vmptr
;
7380 struct x86_exception e
;
7383 if (!nested_vmx_check_permission(vcpu
))
7386 if (unlikely(to_vmx(vcpu
)->nested
.hv_evmcs
))
7389 if (get_vmx_mem_address(vcpu
, exit_qual
, instr_info
, true, &gva
))
7391 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
7392 if (kvm_write_guest_virt_system(vcpu
, gva
, (void *)¤t_vmptr
,
7393 sizeof(gpa_t
), &e
)) {
7394 kvm_inject_page_fault(vcpu
, &e
);
7397 return nested_vmx_succeed(vcpu
);
7400 /* Emulate the INVEPT instruction */
7401 static int handle_invept(struct kvm_vcpu
*vcpu
)
7403 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7404 u32 vmx_instruction_info
, types
;
7407 struct x86_exception e
;
7412 if (!(vmx
->nested
.msrs
.secondary_ctls_high
&
7413 SECONDARY_EXEC_ENABLE_EPT
) ||
7414 !(vmx
->nested
.msrs
.ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7415 kvm_queue_exception(vcpu
, UD_VECTOR
);
7419 if (!nested_vmx_check_permission(vcpu
))
7422 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7423 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7425 types
= (vmx
->nested
.msrs
.ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7427 if (type
>= 32 || !(types
& (1 << type
)))
7428 return nested_vmx_failValid(vcpu
,
7429 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7431 /* According to the Intel VMX instruction reference, the memory
7432 * operand is read even if it isn't needed (e.g., for type==global)
7434 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7435 vmx_instruction_info
, false, &gva
))
7437 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
7438 kvm_inject_page_fault(vcpu
, &e
);
7443 case VMX_EPT_EXTENT_GLOBAL
:
7445 * TODO: track mappings and invalidate
7446 * single context requests appropriately
7448 case VMX_EPT_EXTENT_CONTEXT
:
7449 kvm_mmu_sync_roots(vcpu
);
7450 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7457 return nested_vmx_succeed(vcpu
);
7460 static u16
nested_get_vpid02(struct kvm_vcpu
*vcpu
)
7462 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7464 return vmx
->nested
.vpid02
? vmx
->nested
.vpid02
: vmx
->vpid
;
7467 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7470 u32 vmx_instruction_info
;
7471 unsigned long type
, types
;
7473 struct x86_exception e
;
7480 if (!(vmx
->nested
.msrs
.secondary_ctls_high
&
7481 SECONDARY_EXEC_ENABLE_VPID
) ||
7482 !(vmx
->nested
.msrs
.vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7483 kvm_queue_exception(vcpu
, UD_VECTOR
);
7487 if (!nested_vmx_check_permission(vcpu
))
7490 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7491 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7493 types
= (vmx
->nested
.msrs
.vpid_caps
&
7494 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7496 if (type
>= 32 || !(types
& (1 << type
)))
7497 return nested_vmx_failValid(vcpu
,
7498 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7500 /* according to the intel vmx instruction reference, the memory
7501 * operand is read even if it isn't needed (e.g., for type==global)
7503 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7504 vmx_instruction_info
, false, &gva
))
7506 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
7507 kvm_inject_page_fault(vcpu
, &e
);
7510 if (operand
.vpid
>> 16)
7511 return nested_vmx_failValid(vcpu
,
7512 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7514 vpid02
= nested_get_vpid02(vcpu
);
7516 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7517 if (!operand
.vpid
||
7518 is_noncanonical_address(operand
.gla
, vcpu
))
7519 return nested_vmx_failValid(vcpu
,
7520 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7521 if (cpu_has_vmx_invvpid_individual_addr()) {
7522 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR
,
7523 vpid02
, operand
.gla
);
7525 __vmx_flush_tlb(vcpu
, vpid02
, false);
7527 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7528 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7530 return nested_vmx_failValid(vcpu
,
7531 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7532 __vmx_flush_tlb(vcpu
, vpid02
, false);
7534 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7535 __vmx_flush_tlb(vcpu
, vpid02
, false);
7539 return kvm_skip_emulated_instruction(vcpu
);
7542 return nested_vmx_succeed(vcpu
);
7545 static int handle_invpcid(struct kvm_vcpu
*vcpu
)
7547 u32 vmx_instruction_info
;
7551 struct x86_exception e
;
7553 unsigned long roots_to_free
= 0;
7559 if (!guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
)) {
7560 kvm_queue_exception(vcpu
, UD_VECTOR
);
7564 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7565 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7568 kvm_inject_gp(vcpu
, 0);
7572 /* According to the Intel instruction reference, the memory operand
7573 * is read even if it isn't needed (e.g., for type==all)
7575 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7576 vmx_instruction_info
, false, &gva
))
7579 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
7580 kvm_inject_page_fault(vcpu
, &e
);
7584 if (operand
.pcid
>> 12 != 0) {
7585 kvm_inject_gp(vcpu
, 0);
7589 pcid_enabled
= kvm_read_cr4_bits(vcpu
, X86_CR4_PCIDE
);
7592 case INVPCID_TYPE_INDIV_ADDR
:
7593 if ((!pcid_enabled
&& (operand
.pcid
!= 0)) ||
7594 is_noncanonical_address(operand
.gla
, vcpu
)) {
7595 kvm_inject_gp(vcpu
, 0);
7598 kvm_mmu_invpcid_gva(vcpu
, operand
.gla
, operand
.pcid
);
7599 return kvm_skip_emulated_instruction(vcpu
);
7601 case INVPCID_TYPE_SINGLE_CTXT
:
7602 if (!pcid_enabled
&& (operand
.pcid
!= 0)) {
7603 kvm_inject_gp(vcpu
, 0);
7607 if (kvm_get_active_pcid(vcpu
) == operand
.pcid
) {
7608 kvm_mmu_sync_roots(vcpu
);
7609 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7612 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
7613 if (kvm_get_pcid(vcpu
, vcpu
->arch
.mmu
->prev_roots
[i
].cr3
)
7615 roots_to_free
|= KVM_MMU_ROOT_PREVIOUS(i
);
7617 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
, roots_to_free
);
7619 * If neither the current cr3 nor any of the prev_roots use the
7620 * given PCID, then nothing needs to be done here because a
7621 * resync will happen anyway before switching to any other CR3.
7624 return kvm_skip_emulated_instruction(vcpu
);
7626 case INVPCID_TYPE_ALL_NON_GLOBAL
:
7628 * Currently, KVM doesn't mark global entries in the shadow
7629 * page tables, so a non-global flush just degenerates to a
7630 * global flush. If needed, we could optimize this later by
7631 * keeping track of global entries in shadow page tables.
7635 case INVPCID_TYPE_ALL_INCL_GLOBAL
:
7636 kvm_mmu_unload(vcpu
);
7637 return kvm_skip_emulated_instruction(vcpu
);
7640 BUG(); /* We have already checked above that type <= 3 */
7644 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7646 unsigned long exit_qualification
;
7648 trace_kvm_pml_full(vcpu
->vcpu_id
);
7650 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7653 * PML buffer FULL happened while executing iret from NMI,
7654 * "blocked by NMI" bit has to be set before next VM entry.
7656 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7658 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7659 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7660 GUEST_INTR_STATE_NMI
);
7663 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7664 * here.., and there's no userspace involvement needed for PML.
7669 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7671 if (!to_vmx(vcpu
)->req_immediate_exit
)
7672 kvm_lapic_expired_hv_timer(vcpu
);
7676 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
7678 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7679 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
7681 /* Check for memory type validity */
7682 switch (address
& VMX_EPTP_MT_MASK
) {
7683 case VMX_EPTP_MT_UC
:
7684 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPTP_UC_BIT
))
7687 case VMX_EPTP_MT_WB
:
7688 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPTP_WB_BIT
))
7695 /* only 4 levels page-walk length are valid */
7696 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
7699 /* Reserved bits should not be set */
7700 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
7703 /* AD, if set, should be supported */
7704 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
7705 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPT_AD_BIT
))
7712 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
7713 struct vmcs12
*vmcs12
)
7715 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7717 bool accessed_dirty
;
7718 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
7720 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
7721 !nested_cpu_has_ept(vmcs12
))
7724 if (index
>= VMFUNC_EPTP_ENTRIES
)
7728 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
7729 &address
, index
* 8, 8))
7732 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
7735 * If the (L2) guest does a vmfunc to the currently
7736 * active ept pointer, we don't have to do anything else
7738 if (vmcs12
->ept_pointer
!= address
) {
7739 if (!valid_ept_address(vcpu
, address
))
7742 kvm_mmu_unload(vcpu
);
7743 mmu
->ept_ad
= accessed_dirty
;
7744 mmu
->mmu_role
.base
.ad_disabled
= !accessed_dirty
;
7745 vmcs12
->ept_pointer
= address
;
7747 * TODO: Check what's the correct approach in case
7748 * mmu reload fails. Currently, we just let the next
7749 * reload potentially fail
7751 kvm_mmu_reload(vcpu
);
7757 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
7759 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7760 struct vmcs12
*vmcs12
;
7761 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
7764 * VMFUNC is only supported for nested guests, but we always enable the
7765 * secondary control for simplicity; for non-nested mode, fake that we
7766 * didn't by injecting #UD.
7768 if (!is_guest_mode(vcpu
)) {
7769 kvm_queue_exception(vcpu
, UD_VECTOR
);
7773 vmcs12
= get_vmcs12(vcpu
);
7774 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
7779 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
7785 return kvm_skip_emulated_instruction(vcpu
);
7788 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
7789 vmcs_read32(VM_EXIT_INTR_INFO
),
7790 vmcs_readl(EXIT_QUALIFICATION
));
7795 * When nested=0, all VMX instruction VM Exits filter here. The handlers
7796 * are overwritten by nested_vmx_setup() when nested=1.
7798 static int handle_vmx_instruction(struct kvm_vcpu
*vcpu
)
7800 kvm_queue_exception(vcpu
, UD_VECTOR
);
7804 static int handle_encls(struct kvm_vcpu
*vcpu
)
7807 * SGX virtualization is not yet supported. There is no software
7808 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
7809 * to prevent the guest from executing ENCLS.
7811 kvm_queue_exception(vcpu
, UD_VECTOR
);
7816 * The exit handlers return 1 if the exit was handled fully and guest execution
7817 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7818 * to be done to userspace and return 0.
7820 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7821 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7822 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7823 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7824 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7825 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7826 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7827 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7828 [EXIT_REASON_CPUID
] = handle_cpuid
,
7829 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7830 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7831 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7832 [EXIT_REASON_HLT
] = handle_halt
,
7833 [EXIT_REASON_INVD
] = handle_invd
,
7834 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7835 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7836 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7837 [EXIT_REASON_VMCLEAR
] = handle_vmx_instruction
,
7838 [EXIT_REASON_VMLAUNCH
] = handle_vmx_instruction
,
7839 [EXIT_REASON_VMPTRLD
] = handle_vmx_instruction
,
7840 [EXIT_REASON_VMPTRST
] = handle_vmx_instruction
,
7841 [EXIT_REASON_VMREAD
] = handle_vmx_instruction
,
7842 [EXIT_REASON_VMRESUME
] = handle_vmx_instruction
,
7843 [EXIT_REASON_VMWRITE
] = handle_vmx_instruction
,
7844 [EXIT_REASON_VMOFF
] = handle_vmx_instruction
,
7845 [EXIT_REASON_VMON
] = handle_vmx_instruction
,
7846 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7847 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7848 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7849 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7850 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7851 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7852 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7853 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7854 [EXIT_REASON_GDTR_IDTR
] = handle_desc
,
7855 [EXIT_REASON_LDTR_TR
] = handle_desc
,
7856 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7857 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7858 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7859 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7860 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7861 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7862 [EXIT_REASON_INVEPT
] = handle_vmx_instruction
,
7863 [EXIT_REASON_INVVPID
] = handle_vmx_instruction
,
7864 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
7865 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
7866 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7867 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7868 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7869 [EXIT_REASON_INVPCID
] = handle_invpcid
,
7870 [EXIT_REASON_VMFUNC
] = handle_vmx_instruction
,
7871 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7872 [EXIT_REASON_ENCLS
] = handle_encls
,
7875 static const int kvm_vmx_max_exit_handlers
=
7876 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7878 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7879 struct vmcs12
*vmcs12
)
7881 unsigned long exit_qualification
;
7882 gpa_t bitmap
, last_bitmap
;
7887 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7888 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7890 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7892 port
= exit_qualification
>> 16;
7893 size
= (exit_qualification
& 7) + 1;
7895 last_bitmap
= (gpa_t
)-1;
7900 bitmap
= vmcs12
->io_bitmap_a
;
7901 else if (port
< 0x10000)
7902 bitmap
= vmcs12
->io_bitmap_b
;
7905 bitmap
+= (port
& 0x7fff) / 8;
7907 if (last_bitmap
!= bitmap
)
7908 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7910 if (b
& (1 << (port
& 7)))
7915 last_bitmap
= bitmap
;
7922 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7923 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7924 * disinterest in the current event (read or write a specific MSR) by using an
7925 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7927 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7928 struct vmcs12
*vmcs12
, u32 exit_reason
)
7930 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7933 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7937 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7938 * for the four combinations of read/write and low/high MSR numbers.
7939 * First we need to figure out which of the four to use:
7941 bitmap
= vmcs12
->msr_bitmap
;
7942 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7944 if (msr_index
>= 0xc0000000) {
7945 msr_index
-= 0xc0000000;
7949 /* Then read the msr_index'th bit from this bitmap: */
7950 if (msr_index
< 1024*8) {
7952 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7954 return 1 & (b
>> (msr_index
& 7));
7956 return true; /* let L1 handle the wrong parameter */
7960 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7961 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7962 * intercept (via guest_host_mask etc.) the current event.
7964 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7965 struct vmcs12
*vmcs12
)
7967 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7968 int cr
= exit_qualification
& 15;
7972 switch ((exit_qualification
>> 4) & 3) {
7973 case 0: /* mov to cr */
7974 reg
= (exit_qualification
>> 8) & 15;
7975 val
= kvm_register_readl(vcpu
, reg
);
7978 if (vmcs12
->cr0_guest_host_mask
&
7979 (val
^ vmcs12
->cr0_read_shadow
))
7983 if ((vmcs12
->cr3_target_count
>= 1 &&
7984 vmcs12
->cr3_target_value0
== val
) ||
7985 (vmcs12
->cr3_target_count
>= 2 &&
7986 vmcs12
->cr3_target_value1
== val
) ||
7987 (vmcs12
->cr3_target_count
>= 3 &&
7988 vmcs12
->cr3_target_value2
== val
) ||
7989 (vmcs12
->cr3_target_count
>= 4 &&
7990 vmcs12
->cr3_target_value3
== val
))
7992 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7996 if (vmcs12
->cr4_guest_host_mask
&
7997 (vmcs12
->cr4_read_shadow
^ val
))
8001 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8007 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8008 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8011 case 1: /* mov from cr */
8014 if (vmcs12
->cpu_based_vm_exec_control
&
8015 CPU_BASED_CR3_STORE_EXITING
)
8019 if (vmcs12
->cpu_based_vm_exec_control
&
8020 CPU_BASED_CR8_STORE_EXITING
)
8027 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8028 * cr0. Other attempted changes are ignored, with no exit.
8030 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8031 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8032 (val
^ vmcs12
->cr0_read_shadow
))
8034 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8035 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8043 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu
*vcpu
,
8044 struct vmcs12
*vmcs12
, gpa_t bitmap
)
8046 u32 vmx_instruction_info
;
8047 unsigned long field
;
8050 if (!nested_cpu_has_shadow_vmcs(vmcs12
))
8053 /* Decode instruction info and find the field to access */
8054 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8055 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
8057 /* Out-of-range fields always cause a VM exit from L2 to L1 */
8061 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ field
/8, &b
, 1))
8064 return 1 & (b
>> (field
& 7));
8068 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8069 * should handle it ourselves in L0 (and then continue L2). Only call this
8070 * when in is_guest_mode (L2).
8072 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8074 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8075 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8076 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8078 if (vmx
->nested
.nested_run_pending
)
8081 if (unlikely(vmx
->fail
)) {
8082 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8083 vmcs_read32(VM_INSTRUCTION_ERROR
));
8088 * The host physical addresses of some pages of guest memory
8089 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8090 * Page). The CPU may write to these pages via their host
8091 * physical address while L2 is running, bypassing any
8092 * address-translation-based dirty tracking (e.g. EPT write
8095 * Mark them dirty on every exit from L2 to prevent them from
8096 * getting out of sync with dirty tracking.
8098 nested_mark_vmcs12_pages_dirty(vcpu
);
8100 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8101 vmcs_readl(EXIT_QUALIFICATION
),
8102 vmx
->idt_vectoring_info
,
8104 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8107 switch (exit_reason
) {
8108 case EXIT_REASON_EXCEPTION_NMI
:
8109 if (is_nmi(intr_info
))
8111 else if (is_page_fault(intr_info
))
8112 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8113 else if (is_debug(intr_info
) &&
8115 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8117 else if (is_breakpoint(intr_info
) &&
8118 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8120 return vmcs12
->exception_bitmap
&
8121 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8122 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8124 case EXIT_REASON_TRIPLE_FAULT
:
8126 case EXIT_REASON_PENDING_INTERRUPT
:
8127 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8128 case EXIT_REASON_NMI_WINDOW
:
8129 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8130 case EXIT_REASON_TASK_SWITCH
:
8132 case EXIT_REASON_CPUID
:
8134 case EXIT_REASON_HLT
:
8135 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8136 case EXIT_REASON_INVD
:
8138 case EXIT_REASON_INVLPG
:
8139 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8140 case EXIT_REASON_RDPMC
:
8141 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8142 case EXIT_REASON_RDRAND
:
8143 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8144 case EXIT_REASON_RDSEED
:
8145 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8146 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8147 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8148 case EXIT_REASON_VMREAD
:
8149 return nested_vmx_exit_handled_vmcs_access(vcpu
, vmcs12
,
8150 vmcs12
->vmread_bitmap
);
8151 case EXIT_REASON_VMWRITE
:
8152 return nested_vmx_exit_handled_vmcs_access(vcpu
, vmcs12
,
8153 vmcs12
->vmwrite_bitmap
);
8154 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8155 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8156 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMRESUME
:
8157 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8158 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8160 * VMX instructions trap unconditionally. This allows L1 to
8161 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8164 case EXIT_REASON_CR_ACCESS
:
8165 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8166 case EXIT_REASON_DR_ACCESS
:
8167 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8168 case EXIT_REASON_IO_INSTRUCTION
:
8169 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8170 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8171 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8172 case EXIT_REASON_MSR_READ
:
8173 case EXIT_REASON_MSR_WRITE
:
8174 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8175 case EXIT_REASON_INVALID_STATE
:
8177 case EXIT_REASON_MWAIT_INSTRUCTION
:
8178 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8179 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8180 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8181 case EXIT_REASON_MONITOR_INSTRUCTION
:
8182 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8183 case EXIT_REASON_PAUSE_INSTRUCTION
:
8184 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8185 nested_cpu_has2(vmcs12
,
8186 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8187 case EXIT_REASON_MCE_DURING_VMENTRY
:
8189 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8190 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8191 case EXIT_REASON_APIC_ACCESS
:
8192 case EXIT_REASON_APIC_WRITE
:
8193 case EXIT_REASON_EOI_INDUCED
:
8195 * The controls for "virtualize APIC accesses," "APIC-
8196 * register virtualization," and "virtual-interrupt
8197 * delivery" only come from vmcs12.
8200 case EXIT_REASON_EPT_VIOLATION
:
8202 * L0 always deals with the EPT violation. If nested EPT is
8203 * used, and the nested mmu code discovers that the address is
8204 * missing in the guest EPT table (EPT12), the EPT violation
8205 * will be injected with nested_ept_inject_page_fault()
8208 case EXIT_REASON_EPT_MISCONFIG
:
8210 * L2 never uses directly L1's EPT, but rather L0's own EPT
8211 * table (shadow on EPT) or a merged EPT table that L0 built
8212 * (EPT on EPT). So any problems with the structure of the
8213 * table is L0's fault.
8216 case EXIT_REASON_INVPCID
:
8218 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8219 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8220 case EXIT_REASON_WBINVD
:
8221 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8222 case EXIT_REASON_XSETBV
:
8224 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8226 * This should never happen, since it is not possible to
8227 * set XSS to a non-zero value---neither in L1 nor in L2.
8228 * If if it were, XSS would have to be checked against
8229 * the XSS exit bitmap in vmcs12.
8231 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8232 case EXIT_REASON_PREEMPTION_TIMER
:
8234 case EXIT_REASON_PML_FULL
:
8235 /* We emulate PML support to L1. */
8237 case EXIT_REASON_VMFUNC
:
8238 /* VM functions are emulated through L2->L0 vmexits. */
8240 case EXIT_REASON_ENCLS
:
8241 /* SGX is never exposed to L1 */
8248 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8250 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8253 * At this point, the exit interruption info in exit_intr_info
8254 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8255 * we need to query the in-kernel LAPIC.
8257 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8258 if ((exit_intr_info
&
8259 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8260 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8261 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8262 vmcs12
->vm_exit_intr_error_code
=
8263 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8266 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8267 vmcs_readl(EXIT_QUALIFICATION
));
8271 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8273 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8274 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8277 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8280 __free_page(vmx
->pml_pg
);
8285 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8287 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8291 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8293 /* Do nothing if PML buffer is empty */
8294 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8297 /* PML index always points to next available PML buffer entity */
8298 if (pml_idx
>= PML_ENTITY_NUM
)
8303 pml_buf
= page_address(vmx
->pml_pg
);
8304 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8307 gpa
= pml_buf
[pml_idx
];
8308 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8309 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8312 /* reset PML index */
8313 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8317 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8318 * Called before reporting dirty_bitmap to userspace.
8320 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8323 struct kvm_vcpu
*vcpu
;
8325 * We only need to kick vcpu out of guest mode here, as PML buffer
8326 * is flushed at beginning of all VMEXITs, and it's obvious that only
8327 * vcpus running in guest are possible to have unflushed GPAs in PML
8330 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8331 kvm_vcpu_kick(vcpu
);
8334 static void vmx_dump_sel(char *name
, uint32_t sel
)
8336 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8337 name
, vmcs_read16(sel
),
8338 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8339 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8340 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8343 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8345 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8346 name
, vmcs_read32(limit
),
8347 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8350 static void dump_vmcs(void)
8352 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8353 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8354 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8355 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8356 u32 secondary_exec_control
= 0;
8357 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8358 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8361 if (cpu_has_secondary_exec_ctrls())
8362 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8364 pr_err("*** Guest State ***\n");
8365 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8366 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8367 vmcs_readl(CR0_GUEST_HOST_MASK
));
8368 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8369 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8370 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8371 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8372 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8374 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8375 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8376 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8377 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8379 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8380 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8381 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8382 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8383 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8384 vmcs_readl(GUEST_SYSENTER_ESP
),
8385 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8386 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8387 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8388 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8389 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8390 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8391 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8392 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8393 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8394 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8395 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8396 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8397 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8398 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8399 efer
, vmcs_read64(GUEST_IA32_PAT
));
8400 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8401 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8402 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8403 if (cpu_has_load_perf_global_ctrl() &&
8404 vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8405 pr_err("PerfGlobCtl = 0x%016llx\n",
8406 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8407 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8408 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8409 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8410 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8411 vmcs_read32(GUEST_ACTIVITY_STATE
));
8412 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8413 pr_err("InterruptStatus = %04x\n",
8414 vmcs_read16(GUEST_INTR_STATUS
));
8416 pr_err("*** Host State ***\n");
8417 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8418 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8419 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8420 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8421 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8422 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8423 vmcs_read16(HOST_TR_SELECTOR
));
8424 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8425 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8426 vmcs_readl(HOST_TR_BASE
));
8427 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8428 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8429 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8430 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8431 vmcs_readl(HOST_CR4
));
8432 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8433 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8434 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8435 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8436 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8437 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8438 vmcs_read64(HOST_IA32_EFER
),
8439 vmcs_read64(HOST_IA32_PAT
));
8440 if (cpu_has_load_perf_global_ctrl() &&
8441 vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8442 pr_err("PerfGlobCtl = 0x%016llx\n",
8443 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8445 pr_err("*** Control State ***\n");
8446 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8447 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8448 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8449 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8450 vmcs_read32(EXCEPTION_BITMAP
),
8451 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8452 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8453 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8454 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8455 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8456 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8457 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8458 vmcs_read32(VM_EXIT_INTR_INFO
),
8459 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8460 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8461 pr_err(" reason=%08x qualification=%016lx\n",
8462 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8463 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8464 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8465 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8466 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8467 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8468 pr_err("TSC Multiplier = 0x%016llx\n",
8469 vmcs_read64(TSC_MULTIPLIER
));
8470 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8471 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8472 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8473 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8474 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8475 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8476 n
= vmcs_read32(CR3_TARGET_COUNT
);
8477 for (i
= 0; i
+ 1 < n
; i
+= 4)
8478 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8479 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8480 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8482 pr_err("CR3 target%u=%016lx\n",
8483 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8484 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8485 pr_err("PLE Gap=%08x Window=%08x\n",
8486 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8487 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8488 pr_err("Virtual processor ID = 0x%04x\n",
8489 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8493 * The guest has exited. See if we can fix it or if we need userspace
8496 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8498 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8499 u32 exit_reason
= vmx
->exit_reason
;
8500 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8502 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8505 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8506 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8507 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8508 * mode as if vcpus is in root mode, the PML buffer must has been
8512 vmx_flush_pml_buffer(vcpu
);
8514 /* If guest state is invalid, start emulating */
8515 if (vmx
->emulation_required
)
8516 return handle_invalid_guest_state(vcpu
);
8518 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8519 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8521 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8523 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8524 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8529 if (unlikely(vmx
->fail
)) {
8530 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8531 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8532 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8538 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8539 * delivery event since it indicates guest is accessing MMIO.
8540 * The vm-exit can be triggered again after return to guest that
8541 * will cause infinite loop.
8543 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8544 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8545 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8546 exit_reason
!= EXIT_REASON_PML_FULL
&&
8547 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8548 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8549 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8550 vcpu
->run
->internal
.ndata
= 3;
8551 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8552 vcpu
->run
->internal
.data
[1] = exit_reason
;
8553 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8554 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8555 vcpu
->run
->internal
.ndata
++;
8556 vcpu
->run
->internal
.data
[3] =
8557 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8562 if (unlikely(!enable_vnmi
&&
8563 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8564 if (vmx_interrupt_allowed(vcpu
)) {
8565 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8566 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8567 vcpu
->arch
.nmi_pending
) {
8569 * This CPU don't support us in finding the end of an
8570 * NMI-blocked window if the guest runs with IRQs
8571 * disabled. So we pull the trigger after 1 s of
8572 * futile waiting, but inform the user about this.
8574 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8575 "state on VCPU %d after 1 s timeout\n",
8576 __func__
, vcpu
->vcpu_id
);
8577 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8581 if (exit_reason
< kvm_vmx_max_exit_handlers
8582 && kvm_vmx_exit_handlers
[exit_reason
])
8583 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8585 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8587 kvm_queue_exception(vcpu
, UD_VECTOR
);
8593 * Software based L1D cache flush which is used when microcode providing
8594 * the cache control MSR is not loaded.
8596 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
8597 * flush it is required to read in 64 KiB because the replacement algorithm
8598 * is not exactly LRU. This could be sized at runtime via topology
8599 * information but as all relevant affected CPUs have 32KiB L1D cache size
8600 * there is no point in doing so.
8602 static void vmx_l1d_flush(struct kvm_vcpu
*vcpu
)
8604 int size
= PAGE_SIZE
<< L1D_CACHE_ORDER
;
8607 * This code is only executed when the the flush mode is 'cond' or
8610 if (static_branch_likely(&vmx_l1d_flush_cond
)) {
8614 * Clear the per-vcpu flush bit, it gets set again
8615 * either from vcpu_run() or from one of the unsafe
8618 flush_l1d
= vcpu
->arch
.l1tf_flush_l1d
;
8619 vcpu
->arch
.l1tf_flush_l1d
= false;
8622 * Clear the per-cpu flush bit, it gets set again from
8623 * the interrupt handlers.
8625 flush_l1d
|= kvm_get_cpu_l1tf_flush_l1d();
8626 kvm_clear_cpu_l1tf_flush_l1d();
8632 vcpu
->stat
.l1d_flush
++;
8634 if (static_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
8635 wrmsrl(MSR_IA32_FLUSH_CMD
, L1D_FLUSH
);
8640 /* First ensure the pages are in the TLB */
8641 "xorl %%eax, %%eax\n"
8642 ".Lpopulate_tlb:\n\t"
8643 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
8644 "addl $4096, %%eax\n\t"
8645 "cmpl %%eax, %[size]\n\t"
8646 "jne .Lpopulate_tlb\n\t"
8647 "xorl %%eax, %%eax\n\t"
8649 /* Now fill the cache */
8650 "xorl %%eax, %%eax\n"
8652 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
8653 "addl $64, %%eax\n\t"
8654 "cmpl %%eax, %[size]\n\t"
8655 "jne .Lfill_cache\n\t"
8657 :: [flush_pages
] "r" (vmx_l1d_flush_pages
),
8659 : "eax", "ebx", "ecx", "edx");
8662 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8664 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8666 if (is_guest_mode(vcpu
) &&
8667 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8670 if (irr
== -1 || tpr
< irr
) {
8671 vmcs_write32(TPR_THRESHOLD
, 0);
8675 vmcs_write32(TPR_THRESHOLD
, irr
);
8678 void vmx_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
8680 u32 sec_exec_control
;
8682 if (!lapic_in_kernel(vcpu
))
8685 if (!flexpriority_enabled
&&
8686 !cpu_has_vmx_virtualize_x2apic_mode())
8689 /* Postpone execution until vmcs01 is the current VMCS. */
8690 if (is_guest_mode(vcpu
)) {
8691 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_apic_mode
= true;
8695 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8696 sec_exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
8697 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
8699 switch (kvm_get_apic_mode(vcpu
)) {
8700 case LAPIC_MODE_INVALID
:
8701 WARN_ONCE(true, "Invalid local APIC state");
8702 case LAPIC_MODE_DISABLED
:
8704 case LAPIC_MODE_XAPIC
:
8705 if (flexpriority_enabled
) {
8707 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8708 vmx_flush_tlb(vcpu
, true);
8711 case LAPIC_MODE_X2APIC
:
8712 if (cpu_has_vmx_virtualize_x2apic_mode())
8714 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8717 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8719 vmx_update_msr_bitmap(vcpu
);
8722 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8724 if (!is_guest_mode(vcpu
)) {
8725 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8726 vmx_flush_tlb(vcpu
, true);
8730 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8738 status
= vmcs_read16(GUEST_INTR_STATUS
);
8740 if (max_isr
!= old
) {
8742 status
|= max_isr
<< 8;
8743 vmcs_write16(GUEST_INTR_STATUS
, status
);
8747 static void vmx_set_rvi(int vector
)
8755 status
= vmcs_read16(GUEST_INTR_STATUS
);
8756 old
= (u8
)status
& 0xff;
8757 if ((u8
)vector
!= old
) {
8759 status
|= (u8
)vector
;
8760 vmcs_write16(GUEST_INTR_STATUS
, status
);
8764 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8767 * When running L2, updating RVI is only relevant when
8768 * vmcs12 virtual-interrupt-delivery enabled.
8769 * However, it can be enabled only when L1 also
8770 * intercepts external-interrupts and in that case
8771 * we should not update vmcs02 RVI but instead intercept
8772 * interrupt. Therefore, do nothing when running L2.
8774 if (!is_guest_mode(vcpu
))
8775 vmx_set_rvi(max_irr
);
8778 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8780 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8782 bool max_irr_updated
;
8784 WARN_ON(!vcpu
->arch
.apicv_active
);
8785 if (pi_test_on(&vmx
->pi_desc
)) {
8786 pi_clear_on(&vmx
->pi_desc
);
8788 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8789 * But on x86 this is just a compiler barrier anyway.
8791 smp_mb__after_atomic();
8793 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
, &max_irr
);
8796 * If we are running L2 and L1 has a new pending interrupt
8797 * which can be injected, we should re-evaluate
8798 * what should be done with this new L1 interrupt.
8799 * If L1 intercepts external-interrupts, we should
8800 * exit from L2 to L1. Otherwise, interrupt should be
8801 * delivered directly to L2.
8803 if (is_guest_mode(vcpu
) && max_irr_updated
) {
8804 if (nested_exit_on_intr(vcpu
))
8805 kvm_vcpu_exiting_guest_mode(vcpu
);
8807 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8810 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8812 vmx_hwapic_irr_update(vcpu
, max_irr
);
8816 static u8
vmx_has_apicv_interrupt(struct kvm_vcpu
*vcpu
)
8818 u8 rvi
= vmx_get_rvi();
8819 u8 vppr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_PROCPRI
);
8821 return ((rvi
& 0xf0) > (vppr
& 0xf0));
8824 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8826 if (!kvm_vcpu_apicv_active(vcpu
))
8829 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8830 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8831 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8832 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8835 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8837 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8839 pi_clear_on(&vmx
->pi_desc
);
8840 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8843 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8845 u32 exit_intr_info
= 0;
8846 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8848 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8849 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8852 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8853 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8854 vmx
->exit_intr_info
= exit_intr_info
;
8856 /* if exit due to PF check for async PF */
8857 if (is_page_fault(exit_intr_info
))
8858 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8860 /* Handle machine checks before interrupts are enabled */
8861 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8862 is_machine_check(exit_intr_info
))
8863 kvm_machine_check();
8865 /* We need to handle NMIs before interrupts are enabled */
8866 if (is_nmi(exit_intr_info
)) {
8867 kvm_before_interrupt(&vmx
->vcpu
);
8869 kvm_after_interrupt(&vmx
->vcpu
);
8873 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8875 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8877 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8878 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8879 unsigned int vector
;
8880 unsigned long entry
;
8882 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8883 #ifdef CONFIG_X86_64
8887 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8888 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8889 entry
= gate_offset(desc
);
8891 #ifdef CONFIG_X86_64
8892 "mov %%" _ASM_SP
", %[sp]\n\t"
8893 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8898 __ASM_SIZE(push
) " $%c[cs]\n\t"
8901 #ifdef CONFIG_X86_64
8906 THUNK_TARGET(entry
),
8907 [ss
]"i"(__KERNEL_DS
),
8908 [cs
]"i"(__KERNEL_CS
)
8912 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8914 static bool vmx_has_emulated_msr(int index
)
8917 case MSR_IA32_SMBASE
:
8919 * We cannot do SMM unless we can run the guest in big
8922 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8923 case MSR_AMD64_VIRT_SPEC_CTRL
:
8924 /* This is AMD only. */
8931 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8936 bool idtv_info_valid
;
8938 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8941 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
8944 * Can't use vmx->exit_intr_info since we're not sure what
8945 * the exit reason is.
8947 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8948 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8949 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8951 * SDM 3: 27.7.1.2 (September 2008)
8952 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8953 * a guest IRET fault.
8954 * SDM 3: 23.2.2 (September 2008)
8955 * Bit 12 is undefined in any of the following cases:
8956 * If the VM exit sets the valid bit in the IDT-vectoring
8957 * information field.
8958 * If the VM exit is due to a double fault.
8960 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8961 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8962 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8963 GUEST_INTR_STATE_NMI
);
8965 vmx
->loaded_vmcs
->nmi_known_unmasked
=
8966 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8967 & GUEST_INTR_STATE_NMI
);
8968 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
8969 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
8970 ktime_to_ns(ktime_sub(ktime_get(),
8971 vmx
->loaded_vmcs
->entry_time
));
8974 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8975 u32 idt_vectoring_info
,
8976 int instr_len_field
,
8977 int error_code_field
)
8981 bool idtv_info_valid
;
8983 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8985 vcpu
->arch
.nmi_injected
= false;
8986 kvm_clear_exception_queue(vcpu
);
8987 kvm_clear_interrupt_queue(vcpu
);
8989 if (!idtv_info_valid
)
8992 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8994 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8995 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8998 case INTR_TYPE_NMI_INTR
:
8999 vcpu
->arch
.nmi_injected
= true;
9001 * SDM 3: 27.7.1.2 (September 2008)
9002 * Clear bit "block by NMI" before VM entry if a NMI
9005 vmx_set_nmi_mask(vcpu
, false);
9007 case INTR_TYPE_SOFT_EXCEPTION
:
9008 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9010 case INTR_TYPE_HARD_EXCEPTION
:
9011 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9012 u32 err
= vmcs_read32(error_code_field
);
9013 kvm_requeue_exception_e(vcpu
, vector
, err
);
9015 kvm_requeue_exception(vcpu
, vector
);
9017 case INTR_TYPE_SOFT_INTR
:
9018 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9020 case INTR_TYPE_EXT_INTR
:
9021 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9028 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9030 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9031 VM_EXIT_INSTRUCTION_LEN
,
9032 IDT_VECTORING_ERROR_CODE
);
9035 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9037 __vmx_complete_interrupts(vcpu
,
9038 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9039 VM_ENTRY_INSTRUCTION_LEN
,
9040 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9042 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9045 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9048 struct perf_guest_switch_msr
*msrs
;
9050 msrs
= perf_guest_get_msrs(&nr_msrs
);
9055 for (i
= 0; i
< nr_msrs
; i
++)
9056 if (msrs
[i
].host
== msrs
[i
].guest
)
9057 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9059 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9060 msrs
[i
].host
, false);
9063 static void vmx_arm_hv_timer(struct vcpu_vmx
*vmx
, u32 val
)
9065 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, val
);
9066 if (!vmx
->loaded_vmcs
->hv_timer_armed
)
9067 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
9068 PIN_BASED_VMX_PREEMPTION_TIMER
);
9069 vmx
->loaded_vmcs
->hv_timer_armed
= true;
9072 static void vmx_update_hv_timer(struct kvm_vcpu
*vcpu
)
9074 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9078 if (vmx
->req_immediate_exit
) {
9079 vmx_arm_hv_timer(vmx
, 0);
9083 if (vmx
->hv_deadline_tsc
!= -1) {
9085 if (vmx
->hv_deadline_tsc
> tscl
)
9086 /* set_hv_timer ensures the delta fits in 32-bits */
9087 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9088 cpu_preemption_timer_multi
);
9092 vmx_arm_hv_timer(vmx
, delta_tsc
);
9096 if (vmx
->loaded_vmcs
->hv_timer_armed
)
9097 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
9098 PIN_BASED_VMX_PREEMPTION_TIMER
);
9099 vmx
->loaded_vmcs
->hv_timer_armed
= false;
9102 static void nested_sync_from_vmcs12(struct kvm_vcpu
*vcpu
)
9104 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9107 * hv_evmcs may end up being not mapped after migration (when
9108 * L2 was running), map it here to make sure vmcs12 changes are
9109 * properly reflected.
9111 if (vmx
->nested
.enlightened_vmcs_enabled
&& !vmx
->nested
.hv_evmcs
)
9112 nested_vmx_handle_enlightened_vmptrld(vcpu
, false);
9114 if (vmx
->nested
.hv_evmcs
) {
9115 copy_vmcs12_to_enlightened(vmx
);
9116 /* All fields are clean */
9117 vmx
->nested
.hv_evmcs
->hv_clean_fields
|=
9118 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
;
9120 copy_vmcs12_to_shadow(vmx
);
9123 vmx
->nested
.need_vmcs12_sync
= false;
9126 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9129 unsigned long cr3
, cr4
, evmcs_rsp
;
9131 /* Record the guest's net vcpu time for enforced NMI injections. */
9132 if (unlikely(!enable_vnmi
&&
9133 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9134 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9136 /* Don't enter VMX if guest state is invalid, let the exit handler
9137 start emulation until we arrive back to a valid state */
9138 if (vmx
->emulation_required
)
9141 if (vmx
->ple_window_dirty
) {
9142 vmx
->ple_window_dirty
= false;
9143 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9146 if (vmx
->nested
.need_vmcs12_sync
)
9147 nested_sync_from_vmcs12(vcpu
);
9149 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9150 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9151 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9152 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9154 cr3
= __get_current_cr3_fast();
9155 if (unlikely(cr3
!= vmx
->loaded_vmcs
->host_state
.cr3
)) {
9156 vmcs_writel(HOST_CR3
, cr3
);
9157 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
9160 cr4
= cr4_read_shadow();
9161 if (unlikely(cr4
!= vmx
->loaded_vmcs
->host_state
.cr4
)) {
9162 vmcs_writel(HOST_CR4
, cr4
);
9163 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
9166 /* When single-stepping over STI and MOV SS, we must clear the
9167 * corresponding interruptibility bits in the guest state. Otherwise
9168 * vmentry fails as it then expects bit 14 (BS) in pending debug
9169 * exceptions being set, but that's not correct for the guest debugging
9171 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9172 vmx_set_interrupt_shadow(vcpu
, 0);
9174 if (static_cpu_has(X86_FEATURE_PKU
) &&
9175 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9176 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9177 __write_pkru(vcpu
->arch
.pkru
);
9179 atomic_switch_perf_msrs(vmx
);
9181 vmx_update_hv_timer(vcpu
);
9184 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9185 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9186 * is no need to worry about the conditional branch over the wrmsr
9187 * being speculatively taken.
9189 x86_spec_ctrl_set_guest(vmx
->spec_ctrl
, 0);
9191 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9193 evmcs_rsp
= static_branch_unlikely(&enable_evmcs
) ?
9194 (unsigned long)¤t_evmcs
->host_rsp
: 0;
9196 if (static_branch_unlikely(&vmx_l1d_should_flush
))
9197 vmx_l1d_flush(vcpu
);
9200 /* Store host registers */
9201 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9202 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9203 "push %%" _ASM_CX
" \n\t"
9204 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9206 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9207 /* Avoid VMWRITE when Enlightened VMCS is in use */
9208 "test %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
9210 "mov %%" _ASM_SP
", (%%" _ASM_SI
") \n\t"
9213 __ex("vmwrite %%" _ASM_SP
", %%" _ASM_DX
) "\n\t"
9215 /* Reload cr2 if changed */
9216 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9217 "mov %%cr2, %%" _ASM_DX
" \n\t"
9218 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9220 "mov %%" _ASM_AX
", %%cr2 \n\t"
9222 /* Check if vmlaunch or vmresume is needed */
9223 "cmpl $0, %c[launched](%0) \n\t"
9224 /* Load guest registers. Don't clobber flags. */
9225 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9226 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9227 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9228 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9229 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9230 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9231 #ifdef CONFIG_X86_64
9232 "mov %c[r8](%0), %%r8 \n\t"
9233 "mov %c[r9](%0), %%r9 \n\t"
9234 "mov %c[r10](%0), %%r10 \n\t"
9235 "mov %c[r11](%0), %%r11 \n\t"
9236 "mov %c[r12](%0), %%r12 \n\t"
9237 "mov %c[r13](%0), %%r13 \n\t"
9238 "mov %c[r14](%0), %%r14 \n\t"
9239 "mov %c[r15](%0), %%r15 \n\t"
9241 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9243 /* Enter guest mode */
9245 __ex("vmlaunch") "\n\t"
9247 "1: " __ex("vmresume") "\n\t"
9249 /* Save guest registers, load host registers, keep flags */
9250 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9252 "setbe %c[fail](%0)\n\t"
9253 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9254 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9255 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9256 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9257 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9258 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9259 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9260 #ifdef CONFIG_X86_64
9261 "mov %%r8, %c[r8](%0) \n\t"
9262 "mov %%r9, %c[r9](%0) \n\t"
9263 "mov %%r10, %c[r10](%0) \n\t"
9264 "mov %%r11, %c[r11](%0) \n\t"
9265 "mov %%r12, %c[r12](%0) \n\t"
9266 "mov %%r13, %c[r13](%0) \n\t"
9267 "mov %%r14, %c[r14](%0) \n\t"
9268 "mov %%r15, %c[r15](%0) \n\t"
9270 * Clear host registers marked as clobbered to prevent
9273 "xor %%r8d, %%r8d \n\t"
9274 "xor %%r9d, %%r9d \n\t"
9275 "xor %%r10d, %%r10d \n\t"
9276 "xor %%r11d, %%r11d \n\t"
9277 "xor %%r12d, %%r12d \n\t"
9278 "xor %%r13d, %%r13d \n\t"
9279 "xor %%r14d, %%r14d \n\t"
9280 "xor %%r15d, %%r15d \n\t"
9282 "mov %%cr2, %%" _ASM_AX
" \n\t"
9283 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9285 "xor %%eax, %%eax \n\t"
9286 "xor %%ebx, %%ebx \n\t"
9287 "xor %%esi, %%esi \n\t"
9288 "xor %%edi, %%edi \n\t"
9289 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9290 ".pushsection .rodata \n\t"
9291 ".global vmx_return \n\t"
9292 "vmx_return: " _ASM_PTR
" 2b \n\t"
9294 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
), "S"(evmcs_rsp
),
9295 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9296 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9297 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9298 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9299 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9300 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9301 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9302 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9303 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9304 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9305 #ifdef CONFIG_X86_64
9306 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9307 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9308 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9309 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9310 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9311 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9312 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9313 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9315 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9316 [wordsize
]"i"(sizeof(ulong
))
9318 #ifdef CONFIG_X86_64
9319 , "rax", "rbx", "rdi"
9320 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9322 , "eax", "ebx", "edi"
9327 * We do not use IBRS in the kernel. If this vCPU has used the
9328 * SPEC_CTRL MSR it may have left it on; save the value and
9329 * turn it off. This is much more efficient than blindly adding
9330 * it to the atomic save/restore list. Especially as the former
9331 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9333 * For non-nested case:
9334 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9338 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9341 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
9342 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
9344 x86_spec_ctrl_restore_host(vmx
->spec_ctrl
, 0);
9346 /* Eliminate branch target predictions from guest mode */
9349 /* All fields are clean at this point */
9350 if (static_branch_unlikely(&enable_evmcs
))
9351 current_evmcs
->hv_clean_fields
|=
9352 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
;
9354 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9355 if (vmx
->host_debugctlmsr
)
9356 update_debugctlmsr(vmx
->host_debugctlmsr
);
9358 #ifndef CONFIG_X86_64
9360 * The sysexit path does not restore ds/es, so we must set them to
9361 * a reasonable value ourselves.
9363 * We can't defer this to vmx_prepare_switch_to_host() since that
9364 * function may be executed in interrupt context, which saves and
9365 * restore segments around it, nullifying its effect.
9367 loadsegment(ds
, __USER_DS
);
9368 loadsegment(es
, __USER_DS
);
9371 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9372 | (1 << VCPU_EXREG_RFLAGS
)
9373 | (1 << VCPU_EXREG_PDPTR
)
9374 | (1 << VCPU_EXREG_SEGMENTS
)
9375 | (1 << VCPU_EXREG_CR3
));
9376 vcpu
->arch
.regs_dirty
= 0;
9379 * eager fpu is enabled if PKEY is supported and CR4 is switched
9380 * back on host, so it is safe to read guest PKRU from current
9383 if (static_cpu_has(X86_FEATURE_PKU
) &&
9384 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9385 vcpu
->arch
.pkru
= __read_pkru();
9386 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9387 __write_pkru(vmx
->host_pkru
);
9390 vmx
->nested
.nested_run_pending
= 0;
9391 vmx
->idt_vectoring_info
= 0;
9393 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9394 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9397 vmx
->loaded_vmcs
->launched
= 1;
9398 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9400 vmx_complete_atomic_exit(vmx
);
9401 vmx_recover_nmi_blocking(vmx
);
9402 vmx_complete_interrupts(vmx
);
9404 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9406 static struct kvm
*vmx_vm_alloc(void)
9408 struct kvm_vmx
*kvm_vmx
= vzalloc(sizeof(struct kvm_vmx
));
9409 return &kvm_vmx
->kvm
;
9412 static void vmx_vm_free(struct kvm
*kvm
)
9414 vfree(to_kvm_vmx(kvm
));
9417 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9419 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9422 if (vmx
->loaded_vmcs
== vmcs
)
9427 vmx
->loaded_vmcs
= vmcs
;
9428 vmx_vcpu_load(vcpu
, cpu
);
9431 vm_entry_controls_reset_shadow(vmx
);
9432 vm_exit_controls_reset_shadow(vmx
);
9433 vmx_segment_cache_clear(vmx
);
9437 * Ensure that the current vmcs of the logical processor is the
9438 * vmcs01 of the vcpu before calling free_nested().
9440 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9443 vmx_switch_vmcs(vcpu
, &to_vmx(vcpu
)->vmcs01
);
9448 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9450 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9453 vmx_destroy_pml_buffer(vmx
);
9454 free_vpid(vmx
->vpid
);
9455 leave_guest_mode(vcpu
);
9456 vmx_free_vcpu_nested(vcpu
);
9457 free_loaded_vmcs(vmx
->loaded_vmcs
);
9458 kfree(vmx
->guest_msrs
);
9459 kvm_vcpu_uninit(vcpu
);
9460 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9463 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9466 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9467 unsigned long *msr_bitmap
;
9471 return ERR_PTR(-ENOMEM
);
9473 vmx
->vpid
= allocate_vpid();
9475 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9482 * If PML is turned on, failure on enabling PML just results in failure
9483 * of creating the vcpu, therefore we can simplify PML logic (by
9484 * avoiding dealing with cases, such as enabling PML partially on vcpus
9485 * for the guest, etc.
9488 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9493 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9494 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9497 if (!vmx
->guest_msrs
)
9500 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
9504 msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
9505 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_FS_BASE
, MSR_TYPE_RW
);
9506 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_GS_BASE
, MSR_TYPE_RW
);
9507 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
9508 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
9509 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
9510 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
9511 vmx
->msr_bitmap_mode
= 0;
9513 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9515 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9516 vmx
->vcpu
.cpu
= cpu
;
9517 vmx_vcpu_setup(vmx
);
9518 vmx_vcpu_put(&vmx
->vcpu
);
9520 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9521 err
= alloc_apic_access_page(kvm
);
9526 if (enable_ept
&& !enable_unrestricted_guest
) {
9527 err
= init_rmode_identity_map(kvm
);
9533 nested_vmx_setup_ctls_msrs(&vmx
->nested
.msrs
,
9535 kvm_vcpu_apicv_active(&vmx
->vcpu
));
9537 memset(&vmx
->nested
.msrs
, 0, sizeof(vmx
->nested
.msrs
));
9539 vmx
->nested
.posted_intr_nv
= -1;
9540 vmx
->nested
.current_vmptr
= -1ull;
9542 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9545 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9546 * or POSTED_INTR_WAKEUP_VECTOR.
9548 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9549 vmx
->pi_desc
.sn
= 1;
9554 free_loaded_vmcs(vmx
->loaded_vmcs
);
9556 kfree(vmx
->guest_msrs
);
9558 vmx_destroy_pml_buffer(vmx
);
9560 kvm_vcpu_uninit(&vmx
->vcpu
);
9562 free_vpid(vmx
->vpid
);
9563 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9564 return ERR_PTR(err
);
9567 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
9568 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
9570 static int vmx_vm_init(struct kvm
*kvm
)
9572 spin_lock_init(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
9575 kvm
->arch
.pause_in_guest
= true;
9577 if (boot_cpu_has(X86_BUG_L1TF
) && enable_ept
) {
9578 switch (l1tf_mitigation
) {
9579 case L1TF_MITIGATION_OFF
:
9580 case L1TF_MITIGATION_FLUSH_NOWARN
:
9581 /* 'I explicitly don't care' is set */
9583 case L1TF_MITIGATION_FLUSH
:
9584 case L1TF_MITIGATION_FLUSH_NOSMT
:
9585 case L1TF_MITIGATION_FULL
:
9587 * Warn upon starting the first VM in a potentially
9588 * insecure environment.
9590 if (cpu_smt_control
== CPU_SMT_ENABLED
)
9591 pr_warn_once(L1TF_MSG_SMT
);
9592 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
)
9593 pr_warn_once(L1TF_MSG_L1D
);
9595 case L1TF_MITIGATION_FULL_FORCE
:
9596 /* Flush is enforced */
9603 static void __init
vmx_check_processor_compat(void *rtn
)
9605 struct vmcs_config vmcs_conf
;
9606 struct vmx_capability vmx_cap
;
9609 if (setup_vmcs_config(&vmcs_conf
, &vmx_cap
) < 0)
9612 nested_vmx_setup_ctls_msrs(&vmcs_conf
.nested
, vmx_cap
.ept
,
9614 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9615 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9616 smp_processor_id());
9621 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9626 /* For VT-d and EPT combination
9627 * 1. MMIO: always map as UC
9629 * a. VT-d without snooping control feature: can't guarantee the
9630 * result, try to trust guest.
9631 * b. VT-d with snooping control feature: snooping control feature of
9632 * VT-d engine can guarantee the cache correctness. Just set it
9633 * to WB to keep consistent with host. So the same as item 3.
9634 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9635 * consistent with host MTRR
9638 cache
= MTRR_TYPE_UNCACHABLE
;
9642 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9643 ipat
= VMX_EPT_IPAT_BIT
;
9644 cache
= MTRR_TYPE_WRBACK
;
9648 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9649 ipat
= VMX_EPT_IPAT_BIT
;
9650 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9651 cache
= MTRR_TYPE_WRBACK
;
9653 cache
= MTRR_TYPE_UNCACHABLE
;
9657 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9660 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9663 static int vmx_get_lpage_level(void)
9665 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9666 return PT_DIRECTORY_LEVEL
;
9668 /* For shadow and EPT supported 1GB page */
9669 return PT_PDPE_LEVEL
;
9672 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9675 * These bits in the secondary execution controls field
9676 * are dynamic, the others are mostly based on the hypervisor
9677 * architecture and the guest's CPUID. Do not touch the
9681 SECONDARY_EXEC_SHADOW_VMCS
|
9682 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9683 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9684 SECONDARY_EXEC_DESC
;
9686 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9688 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9689 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9693 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9694 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9696 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9698 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9699 struct kvm_cpuid_entry2
*entry
;
9701 vmx
->nested
.msrs
.cr0_fixed1
= 0xffffffff;
9702 vmx
->nested
.msrs
.cr4_fixed1
= X86_CR4_PCE
;
9704 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9705 if (entry && (entry->_reg & (_cpuid_mask))) \
9706 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
9709 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9710 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9711 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9712 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9713 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9714 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9715 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9716 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9717 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9718 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9719 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9720 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9721 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9722 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9723 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9725 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9726 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9727 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9728 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9729 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9730 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9732 #undef cr4_fixed1_update
9735 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu
*vcpu
)
9737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9739 if (kvm_mpx_supported()) {
9740 bool mpx_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_MPX
);
9743 vmx
->nested
.msrs
.entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
9744 vmx
->nested
.msrs
.exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
9746 vmx
->nested
.msrs
.entry_ctls_high
&= ~VM_ENTRY_LOAD_BNDCFGS
;
9747 vmx
->nested
.msrs
.exit_ctls_high
&= ~VM_EXIT_CLEAR_BNDCFGS
;
9752 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9754 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9756 if (cpu_has_secondary_exec_ctrls()) {
9757 vmx_compute_secondary_exec_control(vmx
);
9758 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9761 if (nested_vmx_allowed(vcpu
))
9762 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9763 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9765 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9766 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9768 if (nested_vmx_allowed(vcpu
)) {
9769 nested_vmx_cr_fixed1_bits_update(vcpu
);
9770 nested_vmx_entry_exit_ctls_update(vcpu
);
9774 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9776 if (func
== 1 && nested
)
9777 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9780 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9781 struct x86_exception
*fault
)
9783 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9784 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9786 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9788 if (vmx
->nested
.pml_full
) {
9789 exit_reason
= EXIT_REASON_PML_FULL
;
9790 vmx
->nested
.pml_full
= false;
9791 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9792 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9793 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9795 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9797 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9798 vmcs12
->guest_physical_address
= fault
->address
;
9801 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9803 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9806 /* Callbacks for nested_ept_init_mmu_context: */
9808 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9810 /* return the page table to be shadowed - in our case, EPT12 */
9811 return get_vmcs12(vcpu
)->ept_pointer
;
9814 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9816 WARN_ON(mmu_is_nested(vcpu
));
9818 vcpu
->arch
.mmu
= &vcpu
->arch
.guest_mmu
;
9819 kvm_init_shadow_ept_mmu(vcpu
,
9820 to_vmx(vcpu
)->nested
.msrs
.ept_caps
&
9821 VMX_EPT_EXECUTE_ONLY_BIT
,
9822 nested_ept_ad_enabled(vcpu
),
9823 nested_ept_get_cr3(vcpu
));
9824 vcpu
->arch
.mmu
->set_cr3
= vmx_set_cr3
;
9825 vcpu
->arch
.mmu
->get_cr3
= nested_ept_get_cr3
;
9826 vcpu
->arch
.mmu
->inject_page_fault
= nested_ept_inject_page_fault
;
9827 vcpu
->arch
.mmu
->get_pdptr
= kvm_pdptr_read
;
9829 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9832 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9834 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
9835 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
9838 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9841 bool inequality
, bit
;
9843 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9845 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9846 vmcs12
->page_fault_error_code_match
;
9847 return inequality
^ bit
;
9850 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9851 struct x86_exception
*fault
)
9853 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9855 WARN_ON(!is_guest_mode(vcpu
));
9857 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9858 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9859 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9860 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9861 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9862 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9865 kvm_inject_page_fault(vcpu
, fault
);
9869 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
9870 struct vmcs12
*vmcs12
);
9872 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
)
9874 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9875 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9879 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9881 * Translate L1 physical address to host physical
9882 * address for vmcs02. Keep the page pinned, so this
9883 * physical address remains valid. We keep a reference
9884 * to it so we can release it later.
9886 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9887 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9888 vmx
->nested
.apic_access_page
= NULL
;
9890 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9892 * If translation failed, no matter: This feature asks
9893 * to exit when accessing the given address, and if it
9894 * can never be accessed, this feature won't do
9897 if (!is_error_page(page
)) {
9898 vmx
->nested
.apic_access_page
= page
;
9899 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9900 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9902 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9903 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9907 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9908 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9909 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9910 vmx
->nested
.virtual_apic_page
= NULL
;
9912 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9915 * If translation failed, VM entry will fail because
9916 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9917 * Failing the vm entry is _not_ what the processor
9918 * does but it's basically the only possibility we
9919 * have. We could still enter the guest if CR8 load
9920 * exits are enabled, CR8 store exits are enabled, and
9921 * virtualize APIC access is disabled; in this case
9922 * the processor would never use the TPR shadow and we
9923 * could simply clear the bit from the execution
9924 * control. But such a configuration is useless, so
9925 * let's keep the code simple.
9927 if (!is_error_page(page
)) {
9928 vmx
->nested
.virtual_apic_page
= page
;
9929 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9930 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9934 if (nested_cpu_has_posted_intr(vmcs12
)) {
9935 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9936 kunmap(vmx
->nested
.pi_desc_page
);
9937 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9938 vmx
->nested
.pi_desc_page
= NULL
;
9940 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9941 if (is_error_page(page
))
9943 vmx
->nested
.pi_desc_page
= page
;
9944 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9945 vmx
->nested
.pi_desc
=
9946 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9947 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9949 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9950 page_to_phys(vmx
->nested
.pi_desc_page
) +
9951 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9954 if (nested_vmx_prepare_msr_bitmap(vcpu
, vmcs12
))
9955 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
9956 CPU_BASED_USE_MSR_BITMAPS
);
9958 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9959 CPU_BASED_USE_MSR_BITMAPS
);
9962 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9964 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9965 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9968 * A timer value of zero is architecturally guaranteed to cause
9969 * a VMExit prior to executing any instructions in the guest.
9971 if (preemption_timeout
== 0) {
9972 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9976 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9979 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9980 preemption_timeout
*= 1000000;
9981 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9982 hrtimer_start(&vmx
->nested
.preemption_timer
,
9983 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9986 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9987 struct vmcs12
*vmcs12
)
9989 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9992 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9993 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9999 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10000 struct vmcs12
*vmcs12
)
10002 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10005 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10011 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10012 struct vmcs12
*vmcs12
)
10014 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10017 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10024 * Merge L0's and L1's MSR bitmap, return false to indicate that
10025 * we do not use the hardware.
10027 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
10028 struct vmcs12
*vmcs12
)
10032 unsigned long *msr_bitmap_l1
;
10033 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.vmcs02
.msr_bitmap
;
10035 * pred_cmd & spec_ctrl are trying to verify two things:
10037 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10038 * ensures that we do not accidentally generate an L02 MSR bitmap
10039 * from the L12 MSR bitmap that is too permissive.
10040 * 2. That L1 or L2s have actually used the MSR. This avoids
10041 * unnecessarily merging of the bitmap if the MSR is unused. This
10042 * works properly because we only update the L01 MSR bitmap lazily.
10043 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10044 * updated to reflect this when L1 (or its L2s) actually write to
10047 bool pred_cmd
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_PRED_CMD
);
10048 bool spec_ctrl
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_SPEC_CTRL
);
10050 /* Nothing to do if the MSR bitmap is not in use. */
10051 if (!cpu_has_vmx_msr_bitmap() ||
10052 !nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10055 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10056 !pred_cmd
&& !spec_ctrl
)
10059 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10060 if (is_error_page(page
))
10063 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10064 if (nested_cpu_has_apic_reg_virt(vmcs12
)) {
10066 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10067 * just lets the processor take the value from the virtual-APIC page;
10068 * take those 256 bits directly from the L1 bitmap.
10070 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
10071 unsigned word
= msr
/ BITS_PER_LONG
;
10072 msr_bitmap_l0
[word
] = msr_bitmap_l1
[word
];
10073 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
10076 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
10077 unsigned word
= msr
/ BITS_PER_LONG
;
10078 msr_bitmap_l0
[word
] = ~0;
10079 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
10083 nested_vmx_disable_intercept_for_msr(
10084 msr_bitmap_l1
, msr_bitmap_l0
,
10085 X2APIC_MSR(APIC_TASKPRI
),
10088 if (nested_cpu_has_vid(vmcs12
)) {
10089 nested_vmx_disable_intercept_for_msr(
10090 msr_bitmap_l1
, msr_bitmap_l0
,
10091 X2APIC_MSR(APIC_EOI
),
10093 nested_vmx_disable_intercept_for_msr(
10094 msr_bitmap_l1
, msr_bitmap_l0
,
10095 X2APIC_MSR(APIC_SELF_IPI
),
10100 nested_vmx_disable_intercept_for_msr(
10101 msr_bitmap_l1
, msr_bitmap_l0
,
10102 MSR_IA32_SPEC_CTRL
,
10103 MSR_TYPE_R
| MSR_TYPE_W
);
10106 nested_vmx_disable_intercept_for_msr(
10107 msr_bitmap_l1
, msr_bitmap_l0
,
10112 kvm_release_page_clean(page
);
10117 static void nested_cache_shadow_vmcs12(struct kvm_vcpu
*vcpu
,
10118 struct vmcs12
*vmcs12
)
10120 struct vmcs12
*shadow
;
10123 if (!nested_cpu_has_shadow_vmcs(vmcs12
) ||
10124 vmcs12
->vmcs_link_pointer
== -1ull)
10127 shadow
= get_shadow_vmcs12(vcpu
);
10128 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->vmcs_link_pointer
);
10130 memcpy(shadow
, kmap(page
), VMCS12_SIZE
);
10133 kvm_release_page_clean(page
);
10136 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu
*vcpu
,
10137 struct vmcs12
*vmcs12
)
10139 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10141 if (!nested_cpu_has_shadow_vmcs(vmcs12
) ||
10142 vmcs12
->vmcs_link_pointer
== -1ull)
10145 kvm_write_guest(vmx
->vcpu
.kvm
, vmcs12
->vmcs_link_pointer
,
10146 get_shadow_vmcs12(vcpu
), VMCS12_SIZE
);
10149 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu
*vcpu
,
10150 struct vmcs12
*vmcs12
)
10152 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
10153 !page_address_valid(vcpu
, vmcs12
->apic_access_addr
))
10159 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10160 struct vmcs12
*vmcs12
)
10162 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10163 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10164 !nested_cpu_has_vid(vmcs12
) &&
10165 !nested_cpu_has_posted_intr(vmcs12
))
10169 * If virtualize x2apic mode is enabled,
10170 * virtualize apic access must be disabled.
10172 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10173 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10177 * If virtual interrupt delivery is enabled,
10178 * we must exit on external interrupts.
10180 if (nested_cpu_has_vid(vmcs12
) &&
10181 !nested_exit_on_intr(vcpu
))
10185 * bits 15:8 should be zero in posted_intr_nv,
10186 * the descriptor address has been already checked
10187 * in nested_get_vmcs12_pages.
10189 * bits 5:0 of posted_intr_desc_addr should be zero.
10191 if (nested_cpu_has_posted_intr(vmcs12
) &&
10192 (!nested_cpu_has_vid(vmcs12
) ||
10193 !nested_exit_intr_ack_set(vcpu
) ||
10194 (vmcs12
->posted_intr_nv
& 0xff00) ||
10195 (vmcs12
->posted_intr_desc_addr
& 0x3f) ||
10196 (vmcs12
->posted_intr_desc_addr
>> cpuid_maxphyaddr(vcpu
))))
10199 /* tpr shadow is needed by all apicv features. */
10200 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10206 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10207 unsigned long count_field
,
10208 unsigned long addr_field
)
10210 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10214 if (vmcs12_read_any(vmcs12
, count_field
, &count
) ||
10215 vmcs12_read_any(vmcs12
, addr_field
, &addr
)) {
10221 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10222 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10223 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10224 pr_debug_ratelimited(
10225 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10226 addr_field
, maxphyaddr
, count
, addr
);
10232 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10233 struct vmcs12
*vmcs12
)
10235 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10236 vmcs12
->vm_exit_msr_store_count
== 0 &&
10237 vmcs12
->vm_entry_msr_load_count
== 0)
10238 return 0; /* Fast path */
10239 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10240 VM_EXIT_MSR_LOAD_ADDR
) ||
10241 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10242 VM_EXIT_MSR_STORE_ADDR
) ||
10243 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10244 VM_ENTRY_MSR_LOAD_ADDR
))
10249 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10250 struct vmcs12
*vmcs12
)
10252 if (!nested_cpu_has_pml(vmcs12
))
10255 if (!nested_cpu_has_ept(vmcs12
) ||
10256 !page_address_valid(vcpu
, vmcs12
->pml_address
))
10262 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu
*vcpu
,
10263 struct vmcs12
*vmcs12
)
10265 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
) &&
10266 !nested_cpu_has_ept(vmcs12
))
10271 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu
*vcpu
,
10272 struct vmcs12
*vmcs12
)
10274 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_MODE_BASED_EPT_EXEC
) &&
10275 !nested_cpu_has_ept(vmcs12
))
10280 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu
*vcpu
,
10281 struct vmcs12
*vmcs12
)
10283 if (!nested_cpu_has_shadow_vmcs(vmcs12
))
10286 if (!page_address_valid(vcpu
, vmcs12
->vmread_bitmap
) ||
10287 !page_address_valid(vcpu
, vmcs12
->vmwrite_bitmap
))
10293 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10294 struct vmx_msr_entry
*e
)
10296 /* x2APIC MSR accesses are not allowed */
10297 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10299 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10300 e
->index
== MSR_IA32_UCODE_REV
)
10302 if (e
->reserved
!= 0)
10307 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10308 struct vmx_msr_entry
*e
)
10310 if (e
->index
== MSR_FS_BASE
||
10311 e
->index
== MSR_GS_BASE
||
10312 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10313 nested_vmx_msr_check_common(vcpu
, e
))
10318 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10319 struct vmx_msr_entry
*e
)
10321 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10322 nested_vmx_msr_check_common(vcpu
, e
))
10328 * Load guest's/host's msr at nested entry/exit.
10329 * return 0 for success, entry index for failure.
10331 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10334 struct vmx_msr_entry e
;
10335 struct msr_data msr
;
10337 msr
.host_initiated
= false;
10338 for (i
= 0; i
< count
; i
++) {
10339 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10341 pr_debug_ratelimited(
10342 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10343 __func__
, i
, gpa
+ i
* sizeof(e
));
10346 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10347 pr_debug_ratelimited(
10348 "%s check failed (%u, 0x%x, 0x%x)\n",
10349 __func__
, i
, e
.index
, e
.reserved
);
10352 msr
.index
= e
.index
;
10353 msr
.data
= e
.value
;
10354 if (kvm_set_msr(vcpu
, &msr
)) {
10355 pr_debug_ratelimited(
10356 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10357 __func__
, i
, e
.index
, e
.value
);
10366 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10369 struct vmx_msr_entry e
;
10371 for (i
= 0; i
< count
; i
++) {
10372 struct msr_data msr_info
;
10373 if (kvm_vcpu_read_guest(vcpu
,
10374 gpa
+ i
* sizeof(e
),
10375 &e
, 2 * sizeof(u32
))) {
10376 pr_debug_ratelimited(
10377 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10378 __func__
, i
, gpa
+ i
* sizeof(e
));
10381 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10382 pr_debug_ratelimited(
10383 "%s check failed (%u, 0x%x, 0x%x)\n",
10384 __func__
, i
, e
.index
, e
.reserved
);
10387 msr_info
.host_initiated
= false;
10388 msr_info
.index
= e
.index
;
10389 if (kvm_get_msr(vcpu
, &msr_info
)) {
10390 pr_debug_ratelimited(
10391 "%s cannot read MSR (%u, 0x%x)\n",
10392 __func__
, i
, e
.index
);
10395 if (kvm_vcpu_write_guest(vcpu
,
10396 gpa
+ i
* sizeof(e
) +
10397 offsetof(struct vmx_msr_entry
, value
),
10398 &msr_info
.data
, sizeof(msr_info
.data
))) {
10399 pr_debug_ratelimited(
10400 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10401 __func__
, i
, e
.index
, msr_info
.data
);
10408 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10410 unsigned long invalid_mask
;
10412 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10413 return (val
& invalid_mask
) == 0;
10417 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10418 * emulating VM entry into a guest with EPT enabled.
10419 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10420 * is assigned to entry_failure_code on failure.
10422 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10423 u32
*entry_failure_code
)
10425 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10426 if (!nested_cr3_valid(vcpu
, cr3
)) {
10427 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10432 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10433 * must not be dereferenced.
10435 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10437 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10438 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10445 kvm_mmu_new_cr3(vcpu
, cr3
, false);
10447 vcpu
->arch
.cr3
= cr3
;
10448 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10450 kvm_init_mmu(vcpu
, false);
10456 * Returns if KVM is able to config CPU to tag TLB entries
10457 * populated by L2 differently than TLB entries populated
10460 * If L1 uses EPT, then TLB entries are tagged with different EPTP.
10462 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
10463 * with different VPID (L1 entries are tagged with vmx->vpid
10464 * while L2 entries are tagged with vmx->nested.vpid02).
10466 static bool nested_has_guest_tlb_tag(struct kvm_vcpu
*vcpu
)
10468 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10470 return nested_cpu_has_ept(vmcs12
) ||
10471 (nested_cpu_has_vpid(vmcs12
) && to_vmx(vcpu
)->nested
.vpid02
);
10474 static u64
nested_vmx_calc_efer(struct vcpu_vmx
*vmx
, struct vmcs12
*vmcs12
)
10476 if (vmx
->nested
.nested_run_pending
&&
10477 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10478 return vmcs12
->guest_ia32_efer
;
10479 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10480 return vmx
->vcpu
.arch
.efer
| (EFER_LMA
| EFER_LME
);
10482 return vmx
->vcpu
.arch
.efer
& ~(EFER_LMA
| EFER_LME
);
10485 static void prepare_vmcs02_constant_state(struct vcpu_vmx
*vmx
)
10488 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
10489 * according to L0's settings (vmcs12 is irrelevant here). Host
10490 * fields that come from L0 and are not constant, e.g. HOST_CR3,
10491 * will be set as needed prior to VMLAUNCH/VMRESUME.
10493 if (vmx
->nested
.vmcs02_initialized
)
10495 vmx
->nested
.vmcs02_initialized
= true;
10498 * We don't care what the EPTP value is we just need to guarantee
10499 * it's valid so we don't get a false positive when doing early
10500 * consistency checks.
10502 if (enable_ept
&& nested_early_check
)
10503 vmcs_write64(EPT_POINTER
, construct_eptp(&vmx
->vcpu
, 0));
10505 /* All VMFUNCs are currently emulated through L0 vmexits. */
10506 if (cpu_has_vmx_vmfunc())
10507 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10509 if (cpu_has_vmx_posted_intr())
10510 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10512 if (cpu_has_vmx_msr_bitmap())
10513 vmcs_write64(MSR_BITMAP
, __pa(vmx
->nested
.vmcs02
.msr_bitmap
));
10516 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10519 * Set the MSR load/store lists to match L0's settings. Only the
10520 * addresses are constant (for vmcs02), the counts can change based
10521 * on L2's behavior, e.g. switching to/from long mode.
10523 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10524 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
.val
));
10525 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
.val
));
10527 vmx_set_constant_host_state(vmx
);
10530 static void prepare_vmcs02_early_full(struct vcpu_vmx
*vmx
,
10531 struct vmcs12
*vmcs12
)
10533 prepare_vmcs02_constant_state(vmx
);
10535 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10538 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
)
10539 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10541 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10545 static void prepare_vmcs02_early(struct vcpu_vmx
*vmx
, struct vmcs12
*vmcs12
)
10547 u32 exec_control
, vmcs12_exec_ctrl
;
10548 u64 guest_efer
= nested_vmx_calc_efer(vmx
, vmcs12
);
10550 if (vmx
->nested
.dirty_vmcs12
|| vmx
->nested
.hv_evmcs
)
10551 prepare_vmcs02_early_full(vmx
, vmcs12
);
10554 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10555 * entry, but only if the current (host) sp changed from the value
10556 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10557 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10558 * here we just force the write to happen on entry. host_rsp will
10559 * also be written unconditionally by nested_vmx_check_vmentry_hw()
10560 * if we are doing early consistency checks via hardware.
10567 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10569 /* Preemption timer setting is computed directly in vmx_vcpu_run. */
10570 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10571 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10572 vmx
->loaded_vmcs
->hv_timer_armed
= false;
10574 /* Posted interrupts setting is only taken from vmcs12. */
10575 if (nested_cpu_has_posted_intr(vmcs12
)) {
10576 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10577 vmx
->nested
.pi_pending
= false;
10579 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10581 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10586 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10587 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10588 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10589 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10590 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10593 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10594 * nested_get_vmcs12_pages can't fix it up, the illegal value
10595 * will result in a VM entry failure.
10597 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10598 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10599 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10601 #ifdef CONFIG_X86_64
10602 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10603 CPU_BASED_CR8_STORE_EXITING
;
10608 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
10609 * for I/O port accesses.
10611 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10612 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10613 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10616 * SECONDARY EXEC CONTROLS
10618 if (cpu_has_secondary_exec_ctrls()) {
10619 exec_control
= vmx
->secondary_exec_control
;
10621 /* Take the following fields only from vmcs12 */
10622 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10623 SECONDARY_EXEC_ENABLE_INVPCID
|
10624 SECONDARY_EXEC_RDTSCP
|
10625 SECONDARY_EXEC_XSAVES
|
10626 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10627 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10628 SECONDARY_EXEC_ENABLE_VMFUNC
);
10629 if (nested_cpu_has(vmcs12
,
10630 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10631 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10632 ~SECONDARY_EXEC_ENABLE_PML
;
10633 exec_control
|= vmcs12_exec_ctrl
;
10636 /* VMCS shadowing for L2 is emulated for now */
10637 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
10639 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
10640 vmcs_write16(GUEST_INTR_STATUS
,
10641 vmcs12
->guest_intr_status
);
10644 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10645 * nested_get_vmcs12_pages will either fix it up or
10646 * remove the VM execution control.
10648 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10649 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10651 if (exec_control
& SECONDARY_EXEC_ENCLS_EXITING
)
10652 vmcs_write64(ENCLS_EXITING_BITMAP
, -1ull);
10654 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10660 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
10661 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
10662 * on the related bits (if supported by the CPU) in the hope that
10663 * we can avoid VMWrites during vmx_set_efer().
10665 exec_control
= (vmcs12
->vm_entry_controls
| vmx_vmentry_ctrl()) &
10666 ~VM_ENTRY_IA32E_MODE
& ~VM_ENTRY_LOAD_IA32_EFER
;
10667 if (cpu_has_load_ia32_efer()) {
10668 if (guest_efer
& EFER_LMA
)
10669 exec_control
|= VM_ENTRY_IA32E_MODE
;
10670 if (guest_efer
!= host_efer
)
10671 exec_control
|= VM_ENTRY_LOAD_IA32_EFER
;
10673 vm_entry_controls_init(vmx
, exec_control
);
10678 * L2->L1 exit controls are emulated - the hardware exit is to L0 so
10679 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10680 * bits may be modified by vmx_set_efer() in prepare_vmcs02().
10682 exec_control
= vmx_vmexit_ctrl();
10683 if (cpu_has_load_ia32_efer() && guest_efer
!= host_efer
)
10684 exec_control
|= VM_EXIT_LOAD_IA32_EFER
;
10685 vm_exit_controls_init(vmx
, exec_control
);
10688 * Conceptually we want to copy the PML address and index from
10689 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10690 * since we always flush the log on each vmexit and never change
10691 * the PML address (once set), this happens to be equivalent to
10692 * simply resetting the index in vmcs02.
10695 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10698 * Interrupt/Exception Fields
10700 if (vmx
->nested
.nested_run_pending
) {
10701 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10702 vmcs12
->vm_entry_intr_info_field
);
10703 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10704 vmcs12
->vm_entry_exception_error_code
);
10705 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10706 vmcs12
->vm_entry_instruction_len
);
10707 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10708 vmcs12
->guest_interruptibility_info
);
10709 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10710 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10712 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10716 static void prepare_vmcs02_full(struct vcpu_vmx
*vmx
, struct vmcs12
*vmcs12
)
10718 struct hv_enlightened_vmcs
*hv_evmcs
= vmx
->nested
.hv_evmcs
;
10720 if (!hv_evmcs
|| !(hv_evmcs
->hv_clean_fields
&
10721 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2
)) {
10722 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10723 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10724 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10725 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10726 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10727 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10728 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10729 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10730 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10731 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10732 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10733 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10734 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10735 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10736 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10737 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10738 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10739 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10740 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10741 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10742 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10743 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10744 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10745 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10746 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10747 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10748 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10749 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10750 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10751 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10752 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10753 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10754 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10755 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10758 if (!hv_evmcs
|| !(hv_evmcs
->hv_clean_fields
&
10759 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1
)) {
10760 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10761 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10762 vmcs12
->guest_pending_dbg_exceptions
);
10763 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10764 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10767 * L1 may access the L2's PDPTR, so save them to construct
10771 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10772 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10773 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10774 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10778 if (nested_cpu_has_xsaves(vmcs12
))
10779 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10782 * Whether page-faults are trapped is determined by a combination of
10783 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10784 * If enable_ept, L0 doesn't care about page faults and we should
10785 * set all of these to L1's desires. However, if !enable_ept, L0 does
10786 * care about (at least some) page faults, and because it is not easy
10787 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10788 * to exit on each and every L2 page fault. This is done by setting
10789 * MASK=MATCH=0 and (see below) EB.PF=1.
10790 * Note that below we don't need special code to set EB.PF beyond the
10791 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10792 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10793 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10795 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10796 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10797 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10798 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10800 if (cpu_has_vmx_apicv()) {
10801 vmcs_write64(EOI_EXIT_BITMAP0
, vmcs12
->eoi_exit_bitmap0
);
10802 vmcs_write64(EOI_EXIT_BITMAP1
, vmcs12
->eoi_exit_bitmap1
);
10803 vmcs_write64(EOI_EXIT_BITMAP2
, vmcs12
->eoi_exit_bitmap2
);
10804 vmcs_write64(EOI_EXIT_BITMAP3
, vmcs12
->eoi_exit_bitmap3
);
10807 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.host
.nr
);
10808 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.guest
.nr
);
10810 set_cr4_guest_host_mask(vmx
);
10812 if (kvm_mpx_supported()) {
10813 if (vmx
->nested
.nested_run_pending
&&
10814 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
))
10815 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10817 vmcs_write64(GUEST_BNDCFGS
, vmx
->nested
.vmcs01_guest_bndcfgs
);
10822 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10823 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10824 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10825 * guest in a way that will both be appropriate to L1's requests, and our
10826 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10827 * function also has additional necessary side-effects, like setting various
10828 * vcpu->arch fields.
10829 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10830 * is assigned to entry_failure_code on failure.
10832 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10833 u32
*entry_failure_code
)
10835 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10836 struct hv_enlightened_vmcs
*hv_evmcs
= vmx
->nested
.hv_evmcs
;
10838 if (vmx
->nested
.dirty_vmcs12
|| vmx
->nested
.hv_evmcs
) {
10839 prepare_vmcs02_full(vmx
, vmcs12
);
10840 vmx
->nested
.dirty_vmcs12
= false;
10844 * First, the fields that are shadowed. This must be kept in sync
10845 * with vmcs_shadow_fields.h.
10847 if (!hv_evmcs
|| !(hv_evmcs
->hv_clean_fields
&
10848 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2
)) {
10849 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10850 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10853 if (vmx
->nested
.nested_run_pending
&&
10854 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10855 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10856 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10858 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10859 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10861 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10863 vmx
->nested
.preemption_timer_expired
= false;
10864 if (nested_cpu_has_preemption_timer(vmcs12
))
10865 vmx_start_preemption_timer(vcpu
);
10867 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10868 * bitwise-or of what L1 wants to trap for L2, and what we want to
10869 * trap. Note that CR0.TS also needs updating - we do this later.
10871 update_exception_bitmap(vcpu
);
10872 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10873 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10875 if (vmx
->nested
.nested_run_pending
&&
10876 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10877 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10878 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10879 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10880 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10883 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10885 if (kvm_has_tsc_control
)
10886 decache_tsc_multiplier(vmx
);
10890 * There is no direct mapping between vpid02 and vpid12, the
10891 * vpid02 is per-vCPU for L0 and reused while the value of
10892 * vpid12 is changed w/ one invvpid during nested vmentry.
10893 * The vpid12 is allocated by L1 for L2, so it will not
10894 * influence global bitmap(for vpid01 and vpid02 allocation)
10895 * even if spawn a lot of nested vCPUs.
10897 if (nested_cpu_has_vpid(vmcs12
) && nested_has_guest_tlb_tag(vcpu
)) {
10898 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10899 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10900 __vmx_flush_tlb(vcpu
, nested_get_vpid02(vcpu
), false);
10904 * If L1 use EPT, then L0 needs to execute INVEPT on
10905 * EPTP02 instead of EPTP01. Therefore, delay TLB
10906 * flush until vmcs02->eptp is fully updated by
10907 * KVM_REQ_LOAD_CR3. Note that this assumes
10908 * KVM_REQ_TLB_FLUSH is evaluated after
10909 * KVM_REQ_LOAD_CR3 in vcpu_enter_guest().
10911 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
10915 if (nested_cpu_has_ept(vmcs12
))
10916 nested_ept_init_mmu_context(vcpu
);
10917 else if (nested_cpu_has2(vmcs12
,
10918 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10919 vmx_flush_tlb(vcpu
, true);
10922 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10923 * bits which we consider mandatory enabled.
10924 * The CR0_READ_SHADOW is what L2 should have expected to read given
10925 * the specifications by L1; It's not enough to take
10926 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10927 * have more bits than L1 expected.
10929 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10930 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10932 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10933 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10935 vcpu
->arch
.efer
= nested_vmx_calc_efer(vmx
, vmcs12
);
10936 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10937 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10940 * Guest state is invalid and unrestricted guest is disabled,
10941 * which means L1 attempted VMEntry to L2 with invalid state.
10942 * Fail the VMEntry.
10944 if (vmx
->emulation_required
) {
10945 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10949 /* Shadow page tables on either EPT or shadow page tables. */
10950 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10951 entry_failure_code
))
10955 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10957 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10958 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10962 static int nested_vmx_check_nmi_controls(struct vmcs12
*vmcs12
)
10964 if (!nested_cpu_has_nmi_exiting(vmcs12
) &&
10965 nested_cpu_has_virtual_nmis(vmcs12
))
10968 if (!nested_cpu_has_virtual_nmis(vmcs12
) &&
10969 nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
))
10975 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10977 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10980 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10981 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10982 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10984 if (nested_cpu_has_vpid(vmcs12
) && !vmcs12
->virtual_processor_id
)
10985 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10987 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10988 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10990 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10991 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10993 if (nested_vmx_check_apic_access_controls(vcpu
, vmcs12
))
10994 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10996 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10997 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10999 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
11000 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11002 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
11003 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11005 if (!nested_cpu_has_preemption_timer(vmcs12
) &&
11006 nested_cpu_has_save_preemption_timer(vmcs12
))
11007 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11009 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
11010 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11012 if (nested_vmx_check_unrestricted_guest_controls(vcpu
, vmcs12
))
11013 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11015 if (nested_vmx_check_mode_based_ept_exec_controls(vcpu
, vmcs12
))
11016 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11018 if (nested_vmx_check_shadow_vmcs_controls(vcpu
, vmcs12
))
11019 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11021 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
11022 vmx
->nested
.msrs
.procbased_ctls_low
,
11023 vmx
->nested
.msrs
.procbased_ctls_high
) ||
11024 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
11025 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
11026 vmx
->nested
.msrs
.secondary_ctls_low
,
11027 vmx
->nested
.msrs
.secondary_ctls_high
)) ||
11028 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
11029 vmx
->nested
.msrs
.pinbased_ctls_low
,
11030 vmx
->nested
.msrs
.pinbased_ctls_high
) ||
11031 !vmx_control_verify(vmcs12
->vm_exit_controls
,
11032 vmx
->nested
.msrs
.exit_ctls_low
,
11033 vmx
->nested
.msrs
.exit_ctls_high
) ||
11034 !vmx_control_verify(vmcs12
->vm_entry_controls
,
11035 vmx
->nested
.msrs
.entry_ctls_low
,
11036 vmx
->nested
.msrs
.entry_ctls_high
))
11037 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11039 if (nested_vmx_check_nmi_controls(vmcs12
))
11040 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11042 if (nested_cpu_has_vmfunc(vmcs12
)) {
11043 if (vmcs12
->vm_function_control
&
11044 ~vmx
->nested
.msrs
.vmfunc_controls
)
11045 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11047 if (nested_cpu_has_eptp_switching(vmcs12
)) {
11048 if (!nested_cpu_has_ept(vmcs12
) ||
11049 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
11050 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11054 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
11055 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11057 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
11058 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
11059 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
11060 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
11063 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11064 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11065 * the values of the LMA and LME bits in the field must each be that of
11066 * the host address-space size VM-exit control.
11068 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
11069 ia32e
= (vmcs12
->vm_exit_controls
&
11070 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
11071 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
11072 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
11073 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
11074 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
11078 * From the Intel SDM, volume 3:
11079 * Fields relevant to VM-entry event injection must be set properly.
11080 * These fields are the VM-entry interruption-information field, the
11081 * VM-entry exception error code, and the VM-entry instruction length.
11083 if (vmcs12
->vm_entry_intr_info_field
& INTR_INFO_VALID_MASK
) {
11084 u32 intr_info
= vmcs12
->vm_entry_intr_info_field
;
11085 u8 vector
= intr_info
& INTR_INFO_VECTOR_MASK
;
11086 u32 intr_type
= intr_info
& INTR_INFO_INTR_TYPE_MASK
;
11087 bool has_error_code
= intr_info
& INTR_INFO_DELIVER_CODE_MASK
;
11088 bool should_have_error_code
;
11089 bool urg
= nested_cpu_has2(vmcs12
,
11090 SECONDARY_EXEC_UNRESTRICTED_GUEST
);
11091 bool prot_mode
= !urg
|| vmcs12
->guest_cr0
& X86_CR0_PE
;
11093 /* VM-entry interruption-info field: interruption type */
11094 if (intr_type
== INTR_TYPE_RESERVED
||
11095 (intr_type
== INTR_TYPE_OTHER_EVENT
&&
11096 !nested_cpu_supports_monitor_trap_flag(vcpu
)))
11097 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11099 /* VM-entry interruption-info field: vector */
11100 if ((intr_type
== INTR_TYPE_NMI_INTR
&& vector
!= NMI_VECTOR
) ||
11101 (intr_type
== INTR_TYPE_HARD_EXCEPTION
&& vector
> 31) ||
11102 (intr_type
== INTR_TYPE_OTHER_EVENT
&& vector
!= 0))
11103 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11105 /* VM-entry interruption-info field: deliver error code */
11106 should_have_error_code
=
11107 intr_type
== INTR_TYPE_HARD_EXCEPTION
&& prot_mode
&&
11108 x86_exception_has_error_code(vector
);
11109 if (has_error_code
!= should_have_error_code
)
11110 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11112 /* VM-entry exception error code */
11113 if (has_error_code
&&
11114 vmcs12
->vm_entry_exception_error_code
& GENMASK(31, 15))
11115 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11117 /* VM-entry interruption-info field: reserved bits */
11118 if (intr_info
& INTR_INFO_RESVD_BITS_MASK
)
11119 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11121 /* VM-entry instruction length */
11122 switch (intr_type
) {
11123 case INTR_TYPE_SOFT_EXCEPTION
:
11124 case INTR_TYPE_SOFT_INTR
:
11125 case INTR_TYPE_PRIV_SW_EXCEPTION
:
11126 if ((vmcs12
->vm_entry_instruction_len
> 15) ||
11127 (vmcs12
->vm_entry_instruction_len
== 0 &&
11128 !nested_cpu_has_zero_length_injection(vcpu
)))
11129 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11133 if (nested_cpu_has_ept(vmcs12
) &&
11134 !valid_ept_address(vcpu
, vmcs12
->ept_pointer
))
11135 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11140 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu
*vcpu
,
11141 struct vmcs12
*vmcs12
)
11145 struct vmcs12
*shadow
;
11147 if (vmcs12
->vmcs_link_pointer
== -1ull)
11150 if (!page_address_valid(vcpu
, vmcs12
->vmcs_link_pointer
))
11153 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->vmcs_link_pointer
);
11154 if (is_error_page(page
))
11158 shadow
= kmap(page
);
11159 if (shadow
->hdr
.revision_id
!= VMCS12_REVISION
||
11160 shadow
->hdr
.shadow_vmcs
!= nested_cpu_has_shadow_vmcs(vmcs12
))
11163 kvm_release_page_clean(page
);
11167 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11172 *exit_qual
= ENTRY_FAIL_DEFAULT
;
11174 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
11175 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
11178 if (nested_vmx_check_vmcs_link_ptr(vcpu
, vmcs12
)) {
11179 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
11184 * If the load IA32_EFER VM-entry control is 1, the following checks
11185 * are performed on the field for the IA32_EFER MSR:
11186 * - Bits reserved in the IA32_EFER MSR must be 0.
11187 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11188 * the IA-32e mode guest VM-exit control. It must also be identical
11189 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11192 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
11193 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
11194 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
11195 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
11196 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
11197 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
11198 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
11202 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
11203 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
11204 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
11210 static int __noclone
nested_vmx_check_vmentry_hw(struct kvm_vcpu
*vcpu
)
11212 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11213 unsigned long cr3
, cr4
;
11215 if (!nested_early_check
)
11218 if (vmx
->msr_autoload
.host
.nr
)
11219 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
11220 if (vmx
->msr_autoload
.guest
.nr
)
11221 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
11225 vmx_prepare_switch_to_guest(vcpu
);
11228 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
11229 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to
11230 * be written (by preparve_vmcs02()) before the "real" VMEnter, i.e.
11231 * there is no need to preserve other bits or save/restore the field.
11233 vmcs_writel(GUEST_RFLAGS
, 0);
11235 vmcs_writel(HOST_RIP
, vmx_early_consistency_check_return
);
11237 cr3
= __get_current_cr3_fast();
11238 if (unlikely(cr3
!= vmx
->loaded_vmcs
->host_state
.cr3
)) {
11239 vmcs_writel(HOST_CR3
, cr3
);
11240 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
11243 cr4
= cr4_read_shadow();
11244 if (unlikely(cr4
!= vmx
->loaded_vmcs
->host_state
.cr4
)) {
11245 vmcs_writel(HOST_CR4
, cr4
);
11246 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
11249 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
11253 __ex("vmwrite %%" _ASM_SP
", %%" _ASM_DX
) "\n\t"
11254 "mov %%" _ASM_SP
", %c[host_rsp](%0)\n\t"
11256 /* Check if vmlaunch or vmresume is needed */
11257 "cmpl $0, %c[launched](%0)\n\t"
11259 __ex("vmlaunch") "\n\t"
11261 "1: " __ex("vmresume") "\n\t"
11263 /* Set vmx->fail accordingly */
11264 "setbe %c[fail](%0)\n\t"
11266 ".pushsection .rodata\n\t"
11267 ".global vmx_early_consistency_check_return\n\t"
11268 "vmx_early_consistency_check_return: " _ASM_PTR
" 2b\n\t"
11271 : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
11272 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
11273 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
11274 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
))
11275 : "rax", "cc", "memory"
11278 vmcs_writel(HOST_RIP
, vmx_return
);
11282 if (vmx
->msr_autoload
.host
.nr
)
11283 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.host
.nr
);
11284 if (vmx
->msr_autoload
.guest
.nr
)
11285 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.guest
.nr
);
11288 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11289 VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11295 * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
11297 local_irq_enable();
11298 if (hw_breakpoint_active())
11299 set_debugreg(__this_cpu_read(cpu_dr7
), 7);
11302 * A non-failing VMEntry means we somehow entered guest mode with
11303 * an illegal RIP, and that's just the tip of the iceberg. There
11304 * is no telling what memory has been modified or what state has
11305 * been exposed to unknown code. Hitting this all but guarantees
11306 * a (very critical) hardware issue.
11308 WARN_ON(!(vmcs_read32(VM_EXIT_REASON
) &
11309 VMX_EXIT_REASONS_FAILED_VMENTRY
));
11313 STACK_FRAME_NON_STANDARD(nested_vmx_check_vmentry_hw
);
11315 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11316 struct vmcs12
*vmcs12
);
11319 * If from_vmentry is false, this is being called from state restore (either RSM
11320 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
11323 + * 0 - success, i.e. proceed with actual VMEnter
11324 + * 1 - consistency check VMExit
11325 + * -1 - consistency check VMFail
11327 static int nested_vmx_enter_non_root_mode(struct kvm_vcpu
*vcpu
,
11330 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11331 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11332 bool evaluate_pending_interrupts
;
11333 u32 exit_reason
= EXIT_REASON_INVALID_STATE
;
11336 evaluate_pending_interrupts
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
11337 (CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_VIRTUAL_NMI_PENDING
);
11338 if (likely(!evaluate_pending_interrupts
) && kvm_vcpu_apicv_active(vcpu
))
11339 evaluate_pending_interrupts
|= vmx_has_apicv_interrupt(vcpu
);
11341 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
11342 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11343 if (kvm_mpx_supported() &&
11344 !(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
))
11345 vmx
->nested
.vmcs01_guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11347 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
11349 prepare_vmcs02_early(vmx
, vmcs12
);
11351 if (from_vmentry
) {
11352 nested_get_vmcs12_pages(vcpu
);
11354 if (nested_vmx_check_vmentry_hw(vcpu
)) {
11355 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11359 if (check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
))
11360 goto vmentry_fail_vmexit
;
11363 enter_guest_mode(vcpu
);
11364 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
11365 vcpu
->arch
.tsc_offset
+= vmcs12
->tsc_offset
;
11367 if (prepare_vmcs02(vcpu
, vmcs12
, &exit_qual
))
11368 goto vmentry_fail_vmexit_guest_mode
;
11370 if (from_vmentry
) {
11371 exit_reason
= EXIT_REASON_MSR_LOAD_FAIL
;
11372 exit_qual
= nested_vmx_load_msr(vcpu
,
11373 vmcs12
->vm_entry_msr_load_addr
,
11374 vmcs12
->vm_entry_msr_load_count
);
11376 goto vmentry_fail_vmexit_guest_mode
;
11379 * The MMU is not initialized to point at the right entities yet and
11380 * "get pages" would need to read data from the guest (i.e. we will
11381 * need to perform gpa to hpa translation). Request a call
11382 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
11383 * have already been set at vmentry time and should not be reset.
11385 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES
, vcpu
);
11389 * If L1 had a pending IRQ/NMI until it executed
11390 * VMLAUNCH/VMRESUME which wasn't delivered because it was
11391 * disallowed (e.g. interrupts disabled), L0 needs to
11392 * evaluate if this pending event should cause an exit from L2
11393 * to L1 or delivered directly to L2 (e.g. In case L1 don't
11394 * intercept EXTERNAL_INTERRUPT).
11396 * Usually this would be handled by the processor noticing an
11397 * IRQ/NMI window request, or checking RVI during evaluation of
11398 * pending virtual interrupts. However, this setting was done
11399 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
11400 * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
11402 if (unlikely(evaluate_pending_interrupts
))
11403 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
11406 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11407 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11408 * returned as far as L1 is concerned. It will only return (and set
11409 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11414 * A failed consistency check that leads to a VMExit during L1's
11415 * VMEnter to L2 is a variation of a normal VMexit, as explained in
11416 * 26.7 "VM-entry failures during or after loading guest state".
11418 vmentry_fail_vmexit_guest_mode
:
11419 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
11420 vcpu
->arch
.tsc_offset
-= vmcs12
->tsc_offset
;
11421 leave_guest_mode(vcpu
);
11423 vmentry_fail_vmexit
:
11424 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11429 load_vmcs12_host_state(vcpu
, vmcs12
);
11430 vmcs12
->vm_exit_reason
= exit_reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11431 vmcs12
->exit_qualification
= exit_qual
;
11432 if (enable_shadow_vmcs
|| vmx
->nested
.hv_evmcs
)
11433 vmx
->nested
.need_vmcs12_sync
= true;
11438 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11439 * for running an L2 nested guest.
11441 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
11443 struct vmcs12
*vmcs12
;
11444 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11445 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
11448 if (!nested_vmx_check_permission(vcpu
))
11451 if (!nested_vmx_handle_enlightened_vmptrld(vcpu
, true))
11454 if (!vmx
->nested
.hv_evmcs
&& vmx
->nested
.current_vmptr
== -1ull)
11455 return nested_vmx_failInvalid(vcpu
);
11457 vmcs12
= get_vmcs12(vcpu
);
11460 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
11461 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
11462 * rather than RFLAGS.ZF, and no error number is stored to the
11463 * VM-instruction error field.
11465 if (vmcs12
->hdr
.shadow_vmcs
)
11466 return nested_vmx_failInvalid(vcpu
);
11468 if (vmx
->nested
.hv_evmcs
) {
11469 copy_enlightened_to_vmcs12(vmx
);
11470 /* Enlightened VMCS doesn't have launch state */
11471 vmcs12
->launch_state
= !launch
;
11472 } else if (enable_shadow_vmcs
) {
11473 copy_shadow_to_vmcs12(vmx
);
11477 * The nested entry process starts with enforcing various prerequisites
11478 * on vmcs12 as required by the Intel SDM, and act appropriately when
11479 * they fail: As the SDM explains, some conditions should cause the
11480 * instruction to fail, while others will cause the instruction to seem
11481 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11482 * To speed up the normal (success) code path, we should avoid checking
11483 * for misconfigurations which will anyway be caught by the processor
11484 * when using the merged vmcs02.
11486 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
)
11487 return nested_vmx_failValid(vcpu
,
11488 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
11490 if (vmcs12
->launch_state
== launch
)
11491 return nested_vmx_failValid(vcpu
,
11492 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11493 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
11495 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
11497 return nested_vmx_failValid(vcpu
, ret
);
11500 * We're finally done with prerequisite checking, and can start with
11501 * the nested entry.
11503 vmx
->nested
.nested_run_pending
= 1;
11504 ret
= nested_vmx_enter_non_root_mode(vcpu
, true);
11505 vmx
->nested
.nested_run_pending
= !ret
;
11509 return nested_vmx_failValid(vcpu
,
11510 VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11512 /* Hide L1D cache contents from the nested guest. */
11513 vmx
->vcpu
.arch
.l1tf_flush_l1d
= true;
11516 * Must happen outside of nested_vmx_enter_non_root_mode() as it will
11517 * also be used as part of restoring nVMX state for
11518 * snapshot restore (migration).
11520 * In this flow, it is assumed that vmcs12 cache was
11521 * trasferred as part of captured nVMX state and should
11522 * therefore not be read from guest memory (which may not
11523 * exist on destination host yet).
11525 nested_cache_shadow_vmcs12(vcpu
, vmcs12
);
11528 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11529 * by event injection, halt vcpu.
11531 if ((vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
) &&
11532 !(vmcs12
->vm_entry_intr_info_field
& INTR_INFO_VALID_MASK
)) {
11533 vmx
->nested
.nested_run_pending
= 0;
11534 return kvm_vcpu_halt(vcpu
);
11540 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11541 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11542 * This function returns the new value we should put in vmcs12.guest_cr0.
11543 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11544 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11545 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11546 * didn't trap the bit, because if L1 did, so would L0).
11547 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11548 * been modified by L2, and L1 knows it. So just leave the old value of
11549 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11550 * isn't relevant, because if L0 traps this bit it can set it to anything.
11551 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11552 * changed these bits, and therefore they need to be updated, but L0
11553 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11554 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11556 static inline unsigned long
11557 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11560 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11561 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11562 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11563 vcpu
->arch
.cr0_guest_owned_bits
));
11566 static inline unsigned long
11567 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11570 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11571 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11572 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11573 vcpu
->arch
.cr4_guest_owned_bits
));
11576 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11577 struct vmcs12
*vmcs12
)
11582 if (vcpu
->arch
.exception
.injected
) {
11583 nr
= vcpu
->arch
.exception
.nr
;
11584 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11586 if (kvm_exception_is_soft(nr
)) {
11587 vmcs12
->vm_exit_instruction_len
=
11588 vcpu
->arch
.event_exit_inst_len
;
11589 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11591 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11593 if (vcpu
->arch
.exception
.has_error_code
) {
11594 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11595 vmcs12
->idt_vectoring_error_code
=
11596 vcpu
->arch
.exception
.error_code
;
11599 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11600 } else if (vcpu
->arch
.nmi_injected
) {
11601 vmcs12
->idt_vectoring_info_field
=
11602 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11603 } else if (vcpu
->arch
.interrupt
.injected
) {
11604 nr
= vcpu
->arch
.interrupt
.nr
;
11605 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11607 if (vcpu
->arch
.interrupt
.soft
) {
11608 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11609 vmcs12
->vm_entry_instruction_len
=
11610 vcpu
->arch
.event_exit_inst_len
;
11612 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11614 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11618 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11620 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11621 unsigned long exit_qual
;
11622 bool block_nested_events
=
11623 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11625 if (vcpu
->arch
.exception
.pending
&&
11626 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11627 if (block_nested_events
)
11629 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11633 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11634 vmx
->nested
.preemption_timer_expired
) {
11635 if (block_nested_events
)
11637 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11641 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11642 if (block_nested_events
)
11644 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11645 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11646 INTR_INFO_VALID_MASK
, 0);
11648 * The NMI-triggered VM exit counts as injection:
11649 * clear this one and block further NMIs.
11651 vcpu
->arch
.nmi_pending
= 0;
11652 vmx_set_nmi_mask(vcpu
, true);
11656 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11657 nested_exit_on_intr(vcpu
)) {
11658 if (block_nested_events
)
11660 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11664 vmx_complete_nested_posted_interrupt(vcpu
);
11668 static void vmx_request_immediate_exit(struct kvm_vcpu
*vcpu
)
11670 to_vmx(vcpu
)->req_immediate_exit
= true;
11673 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11675 ktime_t remaining
=
11676 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11679 if (ktime_to_ns(remaining
) <= 0)
11682 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11683 do_div(value
, 1000000);
11684 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11688 * Update the guest state fields of vmcs12 to reflect changes that
11689 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11690 * VM-entry controls is also updated, since this is really a guest
11693 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11695 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11696 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11698 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11699 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11700 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11702 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11703 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11704 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11705 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11706 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11707 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11708 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11709 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11710 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11711 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11712 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11713 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11714 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11715 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11716 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11717 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11718 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11719 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11720 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11721 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11722 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11723 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11724 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11725 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11726 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11727 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11728 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11729 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11730 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11731 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11732 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11733 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11734 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11735 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11736 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11737 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11739 vmcs12
->guest_interruptibility_info
=
11740 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11741 vmcs12
->guest_pending_dbg_exceptions
=
11742 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11743 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11744 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11746 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11748 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11749 if (vmcs12
->vm_exit_controls
&
11750 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11751 vmcs12
->vmx_preemption_timer_value
=
11752 vmx_get_preemption_timer_value(vcpu
);
11753 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11757 * In some cases (usually, nested EPT), L2 is allowed to change its
11758 * own CR3 without exiting. If it has changed it, we must keep it.
11759 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11760 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11762 * Additionally, restore L2's PDPTR to vmcs12.
11765 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11766 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11767 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11768 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11769 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11772 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11774 if (nested_cpu_has_vid(vmcs12
))
11775 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11777 vmcs12
->vm_entry_controls
=
11778 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11779 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11781 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11782 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11783 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11786 /* TODO: These cannot have changed unless we have MSR bitmaps and
11787 * the relevant bit asks not to trap the change */
11788 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11789 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11790 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11791 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11792 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11793 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11794 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11795 if (kvm_mpx_supported())
11796 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11800 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11801 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11802 * and this function updates it to reflect the changes to the guest state while
11803 * L2 was running (and perhaps made some exits which were handled directly by L0
11804 * without going back to L1), and to reflect the exit reason.
11805 * Note that we do not have to copy here all VMCS fields, just those that
11806 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11807 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11808 * which already writes to vmcs12 directly.
11810 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11811 u32 exit_reason
, u32 exit_intr_info
,
11812 unsigned long exit_qualification
)
11814 /* update guest state fields: */
11815 sync_vmcs12(vcpu
, vmcs12
);
11817 /* update exit information fields: */
11819 vmcs12
->vm_exit_reason
= exit_reason
;
11820 vmcs12
->exit_qualification
= exit_qualification
;
11821 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11823 vmcs12
->idt_vectoring_info_field
= 0;
11824 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11825 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11827 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11828 vmcs12
->launch_state
= 1;
11830 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11831 * instead of reading the real value. */
11832 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11835 * Transfer the event that L0 or L1 may wanted to inject into
11836 * L2 to IDT_VECTORING_INFO_FIELD.
11838 vmcs12_save_pending_event(vcpu
, vmcs12
);
11842 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11843 * preserved above and would only end up incorrectly in L1.
11845 vcpu
->arch
.nmi_injected
= false;
11846 kvm_clear_exception_queue(vcpu
);
11847 kvm_clear_interrupt_queue(vcpu
);
11851 * A part of what we need to when the nested L2 guest exits and we want to
11852 * run its L1 parent, is to reset L1's guest state to the host state specified
11854 * This function is to be called not only on normal nested exit, but also on
11855 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11856 * Failures During or After Loading Guest State").
11857 * This function should be called when the active VMCS is L1's (vmcs01).
11859 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11860 struct vmcs12
*vmcs12
)
11862 struct kvm_segment seg
;
11863 u32 entry_failure_code
;
11865 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11866 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11867 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11868 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11870 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11871 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11873 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11874 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11875 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11876 vmx_set_interrupt_shadow(vcpu
, 0);
11879 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11880 * actually changed, because vmx_set_cr0 refers to efer set above.
11882 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11883 * (KVM doesn't change it);
11885 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11886 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11888 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11889 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11890 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11892 nested_ept_uninit_mmu_context(vcpu
);
11895 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11896 * couldn't have changed.
11898 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11899 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11902 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11905 * If vmcs01 doesn't use VPID, CPU flushes TLB on every
11906 * VMEntry/VMExit. Thus, no need to flush TLB.
11908 * If vmcs12 doesn't use VPID, L1 expects TLB to be
11909 * flushed on every VMEntry/VMExit.
11911 * Otherwise, we can preserve TLB entries as long as we are
11912 * able to tag L1 TLB entries differently than L2 TLB entries.
11914 * If vmcs12 uses EPT, we need to execute this flush on EPTP01
11915 * and therefore we request the TLB flush to happen only after VMCS EPTP
11916 * has been set by KVM_REQ_LOAD_CR3.
11919 (!nested_cpu_has_vpid(vmcs12
) || !nested_has_guest_tlb_tag(vcpu
))) {
11920 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
11923 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11924 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11925 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11926 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11927 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11928 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11929 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11931 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11932 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11933 vmcs_write64(GUEST_BNDCFGS
, 0);
11935 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11936 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11937 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11939 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11940 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11941 vmcs12
->host_ia32_perf_global_ctrl
);
11943 /* Set L1 segment info according to Intel SDM
11944 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11945 seg
= (struct kvm_segment
) {
11947 .limit
= 0xFFFFFFFF,
11948 .selector
= vmcs12
->host_cs_selector
,
11954 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11958 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11959 seg
= (struct kvm_segment
) {
11961 .limit
= 0xFFFFFFFF,
11968 seg
.selector
= vmcs12
->host_ds_selector
;
11969 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11970 seg
.selector
= vmcs12
->host_es_selector
;
11971 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11972 seg
.selector
= vmcs12
->host_ss_selector
;
11973 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11974 seg
.selector
= vmcs12
->host_fs_selector
;
11975 seg
.base
= vmcs12
->host_fs_base
;
11976 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11977 seg
.selector
= vmcs12
->host_gs_selector
;
11978 seg
.base
= vmcs12
->host_gs_base
;
11979 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11980 seg
= (struct kvm_segment
) {
11981 .base
= vmcs12
->host_tr_base
,
11983 .selector
= vmcs12
->host_tr_selector
,
11987 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11989 kvm_set_dr(vcpu
, 7, 0x400);
11990 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11992 if (cpu_has_vmx_msr_bitmap())
11993 vmx_update_msr_bitmap(vcpu
);
11995 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11996 vmcs12
->vm_exit_msr_load_count
))
11997 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
12000 static inline u64
nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx
*vmx
)
12002 struct shared_msr_entry
*efer_msr
;
12005 if (vm_entry_controls_get(vmx
) & VM_ENTRY_LOAD_IA32_EFER
)
12006 return vmcs_read64(GUEST_IA32_EFER
);
12008 if (cpu_has_load_ia32_efer())
12011 for (i
= 0; i
< vmx
->msr_autoload
.guest
.nr
; ++i
) {
12012 if (vmx
->msr_autoload
.guest
.val
[i
].index
== MSR_EFER
)
12013 return vmx
->msr_autoload
.guest
.val
[i
].value
;
12016 efer_msr
= find_msr_entry(vmx
, MSR_EFER
);
12018 return efer_msr
->data
;
12023 static void nested_vmx_restore_host_state(struct kvm_vcpu
*vcpu
)
12025 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
12026 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12027 struct vmx_msr_entry g
, h
;
12028 struct msr_data msr
;
12032 vcpu
->arch
.pat
= vmcs_read64(GUEST_IA32_PAT
);
12034 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
12036 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
12037 * as vmcs01.GUEST_DR7 contains a userspace defined value
12038 * and vcpu->arch.dr7 is not squirreled away before the
12039 * nested VMENTER (not worth adding a variable in nested_vmx).
12041 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
12042 kvm_set_dr(vcpu
, 7, DR7_FIXED_1
);
12044 WARN_ON(kvm_set_dr(vcpu
, 7, vmcs_readl(GUEST_DR7
)));
12048 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
12049 * handle a variety of side effects to KVM's software model.
12051 vmx_set_efer(vcpu
, nested_vmx_get_vmcs01_guest_efer(vmx
));
12053 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
12054 vmx_set_cr0(vcpu
, vmcs_readl(CR0_READ_SHADOW
));
12056 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
12057 vmx_set_cr4(vcpu
, vmcs_readl(CR4_READ_SHADOW
));
12059 nested_ept_uninit_mmu_context(vcpu
);
12060 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
12061 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
12064 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
12065 * from vmcs01 (if necessary). The PDPTRs are not loaded on
12066 * VMFail, like everything else we just need to ensure our
12067 * software model is up-to-date.
12069 ept_save_pdptrs(vcpu
);
12071 kvm_mmu_reset_context(vcpu
);
12073 if (cpu_has_vmx_msr_bitmap())
12074 vmx_update_msr_bitmap(vcpu
);
12077 * This nasty bit of open coding is a compromise between blindly
12078 * loading L1's MSRs using the exit load lists (incorrect emulation
12079 * of VMFail), leaving the nested VM's MSRs in the software model
12080 * (incorrect behavior) and snapshotting the modified MSRs (too
12081 * expensive since the lists are unbound by hardware). For each
12082 * MSR that was (prematurely) loaded from the nested VMEntry load
12083 * list, reload it from the exit load list if it exists and differs
12084 * from the guest value. The intent is to stuff host state as
12085 * silently as possible, not to fully process the exit load list.
12087 msr
.host_initiated
= false;
12088 for (i
= 0; i
< vmcs12
->vm_entry_msr_load_count
; i
++) {
12089 gpa
= vmcs12
->vm_entry_msr_load_addr
+ (i
* sizeof(g
));
12090 if (kvm_vcpu_read_guest(vcpu
, gpa
, &g
, sizeof(g
))) {
12091 pr_debug_ratelimited(
12092 "%s read MSR index failed (%u, 0x%08llx)\n",
12097 for (j
= 0; j
< vmcs12
->vm_exit_msr_load_count
; j
++) {
12098 gpa
= vmcs12
->vm_exit_msr_load_addr
+ (j
* sizeof(h
));
12099 if (kvm_vcpu_read_guest(vcpu
, gpa
, &h
, sizeof(h
))) {
12100 pr_debug_ratelimited(
12101 "%s read MSR failed (%u, 0x%08llx)\n",
12105 if (h
.index
!= g
.index
)
12107 if (h
.value
== g
.value
)
12110 if (nested_vmx_load_msr_check(vcpu
, &h
)) {
12111 pr_debug_ratelimited(
12112 "%s check failed (%u, 0x%x, 0x%x)\n",
12113 __func__
, j
, h
.index
, h
.reserved
);
12117 msr
.index
= h
.index
;
12118 msr
.data
= h
.value
;
12119 if (kvm_set_msr(vcpu
, &msr
)) {
12120 pr_debug_ratelimited(
12121 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
12122 __func__
, j
, h
.index
, h
.value
);
12131 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
12135 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12136 * and modify vmcs12 to make it see what it would expect to see there if
12137 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12139 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
12140 u32 exit_intr_info
,
12141 unsigned long exit_qualification
)
12143 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12144 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
12146 /* trying to cancel vmlaunch/vmresume is a bug */
12147 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
12149 leave_guest_mode(vcpu
);
12151 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
12152 vcpu
->arch
.tsc_offset
-= vmcs12
->tsc_offset
;
12154 if (likely(!vmx
->fail
)) {
12155 if (exit_reason
== -1)
12156 sync_vmcs12(vcpu
, vmcs12
);
12158 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
12159 exit_qualification
);
12162 * Must happen outside of sync_vmcs12() as it will
12163 * also be used to capture vmcs12 cache as part of
12164 * capturing nVMX state for snapshot (migration).
12166 * Otherwise, this flush will dirty guest memory at a
12167 * point it is already assumed by user-space to be
12170 nested_flush_cached_shadow_vmcs12(vcpu
, vmcs12
);
12172 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
12173 vmcs12
->vm_exit_msr_store_count
))
12174 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
12177 * The only expected VM-instruction error is "VM entry with
12178 * invalid control field(s)." Anything else indicates a
12179 * problem with L0. And we should never get here with a
12180 * VMFail of any type if early consistency checks are enabled.
12182 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR
) !=
12183 VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
12184 WARN_ON_ONCE(nested_early_check
);
12187 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
12189 /* Update any VMCS fields that might have changed while L2 ran */
12190 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.host
.nr
);
12191 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.guest
.nr
);
12192 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
12194 if (kvm_has_tsc_control
)
12195 decache_tsc_multiplier(vmx
);
12197 if (vmx
->nested
.change_vmcs01_virtual_apic_mode
) {
12198 vmx
->nested
.change_vmcs01_virtual_apic_mode
= false;
12199 vmx_set_virtual_apic_mode(vcpu
);
12200 } else if (!nested_cpu_has_ept(vmcs12
) &&
12201 nested_cpu_has2(vmcs12
,
12202 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
12203 vmx_flush_tlb(vcpu
, true);
12206 /* This is needed for same reason as it was needed in prepare_vmcs02 */
12209 /* Unpin physical memory we referred to in vmcs02 */
12210 if (vmx
->nested
.apic_access_page
) {
12211 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
12212 vmx
->nested
.apic_access_page
= NULL
;
12214 if (vmx
->nested
.virtual_apic_page
) {
12215 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
12216 vmx
->nested
.virtual_apic_page
= NULL
;
12218 if (vmx
->nested
.pi_desc_page
) {
12219 kunmap(vmx
->nested
.pi_desc_page
);
12220 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
12221 vmx
->nested
.pi_desc_page
= NULL
;
12222 vmx
->nested
.pi_desc
= NULL
;
12226 * We are now running in L2, mmu_notifier will force to reload the
12227 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12229 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
12231 if ((exit_reason
!= -1) && (enable_shadow_vmcs
|| vmx
->nested
.hv_evmcs
))
12232 vmx
->nested
.need_vmcs12_sync
= true;
12234 /* in case we halted in L2 */
12235 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
12237 if (likely(!vmx
->fail
)) {
12239 * TODO: SDM says that with acknowledge interrupt on
12240 * exit, bit 31 of the VM-exit interrupt information
12241 * (valid interrupt) is always set to 1 on
12242 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12243 * need kvm_cpu_has_interrupt(). See the commit
12244 * message for details.
12246 if (nested_exit_intr_ack_set(vcpu
) &&
12247 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
12248 kvm_cpu_has_interrupt(vcpu
)) {
12249 int irq
= kvm_cpu_get_interrupt(vcpu
);
12251 vmcs12
->vm_exit_intr_info
= irq
|
12252 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
12255 if (exit_reason
!= -1)
12256 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
12257 vmcs12
->exit_qualification
,
12258 vmcs12
->idt_vectoring_info_field
,
12259 vmcs12
->vm_exit_intr_info
,
12260 vmcs12
->vm_exit_intr_error_code
,
12263 load_vmcs12_host_state(vcpu
, vmcs12
);
12269 * After an early L2 VM-entry failure, we're now back
12270 * in L1 which thinks it just finished a VMLAUNCH or
12271 * VMRESUME instruction, so we need to set the failure
12272 * flag and the VM-instruction error field of the VMCS
12273 * accordingly, and skip the emulated instruction.
12275 (void)nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
12278 * Restore L1's host state to KVM's software model. We're here
12279 * because a consistency check was caught by hardware, which
12280 * means some amount of guest state has been propagated to KVM's
12281 * model and needs to be unwound to the host's state.
12283 nested_vmx_restore_host_state(vcpu
);
12289 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12291 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
12293 if (is_guest_mode(vcpu
)) {
12294 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
12295 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12300 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
12301 struct x86_instruction_info
*info
,
12302 enum x86_intercept_stage stage
)
12304 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
12305 struct x86_emulate_ctxt
*ctxt
= &vcpu
->arch
.emulate_ctxt
;
12308 * RDPID causes #UD if disabled through secondary execution controls.
12309 * Because it is marked as EmulateOnUD, we need to intercept it here.
12311 if (info
->intercept
== x86_intercept_rdtscp
&&
12312 !nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDTSCP
)) {
12313 ctxt
->exception
.vector
= UD_VECTOR
;
12314 ctxt
->exception
.error_code_valid
= false;
12315 return X86EMUL_PROPAGATE_FAULT
;
12318 /* TODO: check more intercepts... */
12319 return X86EMUL_CONTINUE
;
12322 #ifdef CONFIG_X86_64
12323 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12324 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
12325 u64 divisor
, u64
*result
)
12327 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
12329 /* To avoid the overflow on divq */
12330 if (high
>= divisor
)
12333 /* Low hold the result, high hold rem which is discarded */
12334 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
12335 "rm" (divisor
), "0" (low
), "1" (high
));
12341 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
12343 struct vcpu_vmx
*vmx
;
12344 u64 tscl
, guest_tscl
, delta_tsc
, lapic_timer_advance_cycles
;
12346 if (kvm_mwait_in_guest(vcpu
->kvm
))
12347 return -EOPNOTSUPP
;
12349 vmx
= to_vmx(vcpu
);
12351 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
12352 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
12353 lapic_timer_advance_cycles
= nsec_to_cycles(vcpu
, lapic_timer_advance_ns
);
12355 if (delta_tsc
> lapic_timer_advance_cycles
)
12356 delta_tsc
-= lapic_timer_advance_cycles
;
12360 /* Convert to host delta tsc if tsc scaling is enabled */
12361 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
12362 u64_shl_div_u64(delta_tsc
,
12363 kvm_tsc_scaling_ratio_frac_bits
,
12364 vcpu
->arch
.tsc_scaling_ratio
,
12369 * If the delta tsc can't fit in the 32 bit after the multi shift,
12370 * we can't use the preemption timer.
12371 * It's possible that it fits on later vmentries, but checking
12372 * on every vmentry is costly so we just use an hrtimer.
12374 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
12377 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
12378 return delta_tsc
== 0;
12381 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
12383 to_vmx(vcpu
)->hv_deadline_tsc
= -1;
12387 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
12389 if (!kvm_pause_in_guest(vcpu
->kvm
))
12390 shrink_ple_window(vcpu
);
12393 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
12394 struct kvm_memory_slot
*slot
)
12396 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
12397 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
12400 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
12401 struct kvm_memory_slot
*slot
)
12403 kvm_mmu_slot_set_dirty(kvm
, slot
);
12406 static void vmx_flush_log_dirty(struct kvm
*kvm
)
12408 kvm_flush_pml_buffers(kvm
);
12411 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
12413 struct vmcs12
*vmcs12
;
12414 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12416 struct page
*page
= NULL
;
12419 if (is_guest_mode(vcpu
)) {
12420 WARN_ON_ONCE(vmx
->nested
.pml_full
);
12423 * Check if PML is enabled for the nested guest.
12424 * Whether eptp bit 6 is set is already checked
12425 * as part of A/D emulation.
12427 vmcs12
= get_vmcs12(vcpu
);
12428 if (!nested_cpu_has_pml(vmcs12
))
12431 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
12432 vmx
->nested
.pml_full
= true;
12436 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
12438 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
12439 if (is_error_page(page
))
12442 pml_address
= kmap(page
);
12443 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
12445 kvm_release_page_clean(page
);
12451 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
12452 struct kvm_memory_slot
*memslot
,
12453 gfn_t offset
, unsigned long mask
)
12455 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
12458 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
12460 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12461 struct pi_desc old
, new;
12465 old
.control
= new.control
= pi_desc
->control
;
12466 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
12467 "Wakeup handler not enabled while the VCPU is blocked\n");
12469 dest
= cpu_physical_id(vcpu
->cpu
);
12471 if (x2apic_enabled())
12474 new.ndst
= (dest
<< 8) & 0xFF00;
12476 /* set 'NV' to 'notification vector' */
12477 new.nv
= POSTED_INTR_VECTOR
;
12478 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12479 new.control
) != old
.control
);
12481 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
12482 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12483 list_del(&vcpu
->blocked_vcpu_list
);
12484 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12485 vcpu
->pre_pcpu
= -1;
12490 * This routine does the following things for vCPU which is going
12491 * to be blocked if VT-d PI is enabled.
12492 * - Store the vCPU to the wakeup list, so when interrupts happen
12493 * we can find the right vCPU to wake up.
12494 * - Change the Posted-interrupt descriptor as below:
12495 * 'NDST' <-- vcpu->pre_pcpu
12496 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12497 * - If 'ON' is set during this process, which means at least one
12498 * interrupt is posted for this vCPU, we cannot block it, in
12499 * this case, return 1, otherwise, return 0.
12502 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
12505 struct pi_desc old
, new;
12506 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12508 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
12509 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12510 !kvm_vcpu_apicv_active(vcpu
))
12513 WARN_ON(irqs_disabled());
12514 local_irq_disable();
12515 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
12516 vcpu
->pre_pcpu
= vcpu
->cpu
;
12517 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12518 list_add_tail(&vcpu
->blocked_vcpu_list
,
12519 &per_cpu(blocked_vcpu_on_cpu
,
12521 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12525 old
.control
= new.control
= pi_desc
->control
;
12527 WARN((pi_desc
->sn
== 1),
12528 "Warning: SN field of posted-interrupts "
12529 "is set before blocking\n");
12532 * Since vCPU can be preempted during this process,
12533 * vcpu->cpu could be different with pre_pcpu, we
12534 * need to set pre_pcpu as the destination of wakeup
12535 * notification event, then we can find the right vCPU
12536 * to wakeup in wakeup handler if interrupts happen
12537 * when the vCPU is in blocked state.
12539 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
12541 if (x2apic_enabled())
12544 new.ndst
= (dest
<< 8) & 0xFF00;
12546 /* set 'NV' to 'wakeup vector' */
12547 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
12548 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12549 new.control
) != old
.control
);
12551 /* We should not block the vCPU if an interrupt is posted for it. */
12552 if (pi_test_on(pi_desc
) == 1)
12553 __pi_post_block(vcpu
);
12555 local_irq_enable();
12556 return (vcpu
->pre_pcpu
== -1);
12559 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
12561 if (pi_pre_block(vcpu
))
12564 if (kvm_lapic_hv_timer_in_use(vcpu
))
12565 kvm_lapic_switch_to_sw_timer(vcpu
);
12570 static void pi_post_block(struct kvm_vcpu
*vcpu
)
12572 if (vcpu
->pre_pcpu
== -1)
12575 WARN_ON(irqs_disabled());
12576 local_irq_disable();
12577 __pi_post_block(vcpu
);
12578 local_irq_enable();
12581 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
12583 if (kvm_x86_ops
->set_hv_timer
)
12584 kvm_lapic_switch_to_hv_timer(vcpu
);
12586 pi_post_block(vcpu
);
12590 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12593 * @host_irq: host irq of the interrupt
12594 * @guest_irq: gsi of the interrupt
12595 * @set: set or unset PI
12596 * returns 0 on success, < 0 on failure
12598 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
12599 uint32_t guest_irq
, bool set
)
12601 struct kvm_kernel_irq_routing_entry
*e
;
12602 struct kvm_irq_routing_table
*irq_rt
;
12603 struct kvm_lapic_irq irq
;
12604 struct kvm_vcpu
*vcpu
;
12605 struct vcpu_data vcpu_info
;
12608 if (!kvm_arch_has_assigned_device(kvm
) ||
12609 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12610 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
12613 idx
= srcu_read_lock(&kvm
->irq_srcu
);
12614 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
12615 if (guest_irq
>= irq_rt
->nr_rt_entries
||
12616 hlist_empty(&irq_rt
->map
[guest_irq
])) {
12617 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12618 guest_irq
, irq_rt
->nr_rt_entries
);
12622 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
12623 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
12626 * VT-d PI cannot support posting multicast/broadcast
12627 * interrupts to a vCPU, we still use interrupt remapping
12628 * for these kind of interrupts.
12630 * For lowest-priority interrupts, we only support
12631 * those with single CPU as the destination, e.g. user
12632 * configures the interrupts via /proc/irq or uses
12633 * irqbalance to make the interrupts single-CPU.
12635 * We will support full lowest-priority interrupt later.
12638 kvm_set_msi_irq(kvm
, e
, &irq
);
12639 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
12641 * Make sure the IRTE is in remapped mode if
12642 * we don't handle it in posted mode.
12644 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12647 "failed to back to remapped mode, irq: %u\n",
12655 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
12656 vcpu_info
.vector
= irq
.vector
;
12658 trace_kvm_pi_irte_update(host_irq
, vcpu
->vcpu_id
, e
->gsi
,
12659 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
12662 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
12664 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12667 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12675 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12679 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12681 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12682 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12683 FEATURE_CONTROL_LMCE
;
12685 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12686 ~FEATURE_CONTROL_LMCE
;
12689 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12691 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12692 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12697 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12699 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12701 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12702 if (vmx
->nested
.smm
.guest_mode
)
12703 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12705 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12706 vmx
->nested
.vmxon
= false;
12707 vmx_clear_hlt(vcpu
);
12711 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12713 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12716 if (vmx
->nested
.smm
.vmxon
) {
12717 vmx
->nested
.vmxon
= true;
12718 vmx
->nested
.smm
.vmxon
= false;
12721 if (vmx
->nested
.smm
.guest_mode
) {
12722 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12723 ret
= nested_vmx_enter_non_root_mode(vcpu
, false);
12724 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12728 vmx
->nested
.smm
.guest_mode
= false;
12733 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12738 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu
*vcpu
)
12740 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12743 * In case we do two consecutive get/set_nested_state()s while L2 was
12744 * running hv_evmcs may end up not being mapped (we map it from
12745 * nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always
12746 * have vmcs12 if it is true.
12748 return is_guest_mode(vcpu
) || vmx
->nested
.current_vmptr
!= -1ull ||
12749 vmx
->nested
.hv_evmcs
;
12752 static int vmx_get_nested_state(struct kvm_vcpu
*vcpu
,
12753 struct kvm_nested_state __user
*user_kvm_nested_state
,
12754 u32 user_data_size
)
12756 struct vcpu_vmx
*vmx
;
12757 struct vmcs12
*vmcs12
;
12758 struct kvm_nested_state kvm_state
= {
12761 .size
= sizeof(kvm_state
),
12762 .vmx
.vmxon_pa
= -1ull,
12763 .vmx
.vmcs_pa
= -1ull,
12767 return kvm_state
.size
+ 2 * VMCS12_SIZE
;
12769 vmx
= to_vmx(vcpu
);
12770 vmcs12
= get_vmcs12(vcpu
);
12772 if (nested_vmx_allowed(vcpu
) && vmx
->nested
.enlightened_vmcs_enabled
)
12773 kvm_state
.flags
|= KVM_STATE_NESTED_EVMCS
;
12775 if (nested_vmx_allowed(vcpu
) &&
12776 (vmx
->nested
.vmxon
|| vmx
->nested
.smm
.vmxon
)) {
12777 kvm_state
.vmx
.vmxon_pa
= vmx
->nested
.vmxon_ptr
;
12778 kvm_state
.vmx
.vmcs_pa
= vmx
->nested
.current_vmptr
;
12780 if (vmx_has_valid_vmcs12(vcpu
)) {
12781 kvm_state
.size
+= VMCS12_SIZE
;
12783 if (is_guest_mode(vcpu
) &&
12784 nested_cpu_has_shadow_vmcs(vmcs12
) &&
12785 vmcs12
->vmcs_link_pointer
!= -1ull)
12786 kvm_state
.size
+= VMCS12_SIZE
;
12789 if (vmx
->nested
.smm
.vmxon
)
12790 kvm_state
.vmx
.smm
.flags
|= KVM_STATE_NESTED_SMM_VMXON
;
12792 if (vmx
->nested
.smm
.guest_mode
)
12793 kvm_state
.vmx
.smm
.flags
|= KVM_STATE_NESTED_SMM_GUEST_MODE
;
12795 if (is_guest_mode(vcpu
)) {
12796 kvm_state
.flags
|= KVM_STATE_NESTED_GUEST_MODE
;
12798 if (vmx
->nested
.nested_run_pending
)
12799 kvm_state
.flags
|= KVM_STATE_NESTED_RUN_PENDING
;
12803 if (user_data_size
< kvm_state
.size
)
12806 if (copy_to_user(user_kvm_nested_state
, &kvm_state
, sizeof(kvm_state
)))
12809 if (!vmx_has_valid_vmcs12(vcpu
))
12813 * When running L2, the authoritative vmcs12 state is in the
12814 * vmcs02. When running L1, the authoritative vmcs12 state is
12815 * in the shadow or enlightened vmcs linked to vmcs01, unless
12816 * need_vmcs12_sync is set, in which case, the authoritative
12817 * vmcs12 state is in the vmcs12 already.
12819 if (is_guest_mode(vcpu
)) {
12820 sync_vmcs12(vcpu
, vmcs12
);
12821 } else if (!vmx
->nested
.need_vmcs12_sync
) {
12822 if (vmx
->nested
.hv_evmcs
)
12823 copy_enlightened_to_vmcs12(vmx
);
12824 else if (enable_shadow_vmcs
)
12825 copy_shadow_to_vmcs12(vmx
);
12828 if (copy_to_user(user_kvm_nested_state
->data
, vmcs12
, sizeof(*vmcs12
)))
12831 if (nested_cpu_has_shadow_vmcs(vmcs12
) &&
12832 vmcs12
->vmcs_link_pointer
!= -1ull) {
12833 if (copy_to_user(user_kvm_nested_state
->data
+ VMCS12_SIZE
,
12834 get_shadow_vmcs12(vcpu
), sizeof(*vmcs12
)))
12839 return kvm_state
.size
;
12842 static int vmx_set_nested_state(struct kvm_vcpu
*vcpu
,
12843 struct kvm_nested_state __user
*user_kvm_nested_state
,
12844 struct kvm_nested_state
*kvm_state
)
12846 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12847 struct vmcs12
*vmcs12
;
12851 if (kvm_state
->format
!= 0)
12854 if (kvm_state
->flags
& KVM_STATE_NESTED_EVMCS
)
12855 nested_enable_evmcs(vcpu
, NULL
);
12857 if (!nested_vmx_allowed(vcpu
))
12858 return kvm_state
->vmx
.vmxon_pa
== -1ull ? 0 : -EINVAL
;
12860 if (kvm_state
->vmx
.vmxon_pa
== -1ull) {
12861 if (kvm_state
->vmx
.smm
.flags
)
12864 if (kvm_state
->vmx
.vmcs_pa
!= -1ull)
12867 vmx_leave_nested(vcpu
);
12871 if (!page_address_valid(vcpu
, kvm_state
->vmx
.vmxon_pa
))
12874 if ((kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
) &&
12875 (kvm_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
))
12878 if (kvm_state
->vmx
.smm
.flags
&
12879 ~(KVM_STATE_NESTED_SMM_GUEST_MODE
| KVM_STATE_NESTED_SMM_VMXON
))
12883 * SMM temporarily disables VMX, so we cannot be in guest mode,
12884 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
12887 if (is_smm(vcpu
) ? kvm_state
->flags
: kvm_state
->vmx
.smm
.flags
)
12890 if ((kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
) &&
12891 !(kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_VMXON
))
12894 vmx_leave_nested(vcpu
);
12895 if (kvm_state
->vmx
.vmxon_pa
== -1ull)
12898 vmx
->nested
.vmxon_ptr
= kvm_state
->vmx
.vmxon_pa
;
12899 ret
= enter_vmx_operation(vcpu
);
12903 /* Empty 'VMXON' state is permitted */
12904 if (kvm_state
->size
< sizeof(kvm_state
) + sizeof(*vmcs12
))
12907 if (kvm_state
->vmx
.vmcs_pa
!= -1ull) {
12908 if (kvm_state
->vmx
.vmcs_pa
== kvm_state
->vmx
.vmxon_pa
||
12909 !page_address_valid(vcpu
, kvm_state
->vmx
.vmcs_pa
))
12912 set_current_vmptr(vmx
, kvm_state
->vmx
.vmcs_pa
);
12913 } else if (kvm_state
->flags
& KVM_STATE_NESTED_EVMCS
) {
12915 * Sync eVMCS upon entry as we may not have
12916 * HV_X64_MSR_VP_ASSIST_PAGE set up yet.
12918 vmx
->nested
.need_vmcs12_sync
= true;
12923 if (kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_VMXON
) {
12924 vmx
->nested
.smm
.vmxon
= true;
12925 vmx
->nested
.vmxon
= false;
12927 if (kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
)
12928 vmx
->nested
.smm
.guest_mode
= true;
12931 vmcs12
= get_vmcs12(vcpu
);
12932 if (copy_from_user(vmcs12
, user_kvm_nested_state
->data
, sizeof(*vmcs12
)))
12935 if (vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
)
12938 if (!(kvm_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
))
12941 vmx
->nested
.nested_run_pending
=
12942 !!(kvm_state
->flags
& KVM_STATE_NESTED_RUN_PENDING
);
12944 if (nested_cpu_has_shadow_vmcs(vmcs12
) &&
12945 vmcs12
->vmcs_link_pointer
!= -1ull) {
12946 struct vmcs12
*shadow_vmcs12
= get_shadow_vmcs12(vcpu
);
12947 if (kvm_state
->size
< sizeof(kvm_state
) + 2 * sizeof(*vmcs12
))
12950 if (copy_from_user(shadow_vmcs12
,
12951 user_kvm_nested_state
->data
+ VMCS12_SIZE
,
12955 if (shadow_vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
||
12956 !shadow_vmcs12
->hdr
.shadow_vmcs
)
12960 if (check_vmentry_prereqs(vcpu
, vmcs12
) ||
12961 check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
))
12964 vmx
->nested
.dirty_vmcs12
= true;
12965 ret
= nested_vmx_enter_non_root_mode(vcpu
, false);
12972 static __exit
void nested_vmx_hardware_unsetup(void)
12976 if (enable_shadow_vmcs
) {
12977 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
12978 free_page((unsigned long)vmx_bitmap
[i
]);
12982 static __init
int nested_vmx_hardware_setup(int (*exit_handlers
[])(struct kvm_vcpu
*))
12986 if (enable_shadow_vmcs
) {
12987 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
12988 vmx_bitmap
[i
] = (unsigned long *)
12989 __get_free_page(GFP_KERNEL
);
12990 if (!vmx_bitmap
[i
]) {
12991 nested_vmx_hardware_unsetup();
12996 init_vmcs_shadow_fields();
12999 exit_handlers
[EXIT_REASON_VMCLEAR
] = handle_vmclear
,
13000 exit_handlers
[EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
13001 exit_handlers
[EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
13002 exit_handlers
[EXIT_REASON_VMPTRST
] = handle_vmptrst
,
13003 exit_handlers
[EXIT_REASON_VMREAD
] = handle_vmread
,
13004 exit_handlers
[EXIT_REASON_VMRESUME
] = handle_vmresume
,
13005 exit_handlers
[EXIT_REASON_VMWRITE
] = handle_vmwrite
,
13006 exit_handlers
[EXIT_REASON_VMOFF
] = handle_vmoff
,
13007 exit_handlers
[EXIT_REASON_VMON
] = handle_vmon
,
13008 exit_handlers
[EXIT_REASON_INVEPT
] = handle_invept
,
13009 exit_handlers
[EXIT_REASON_INVVPID
] = handle_invvpid
,
13010 exit_handlers
[EXIT_REASON_VMFUNC
] = handle_vmfunc
,
13012 kvm_x86_ops
->check_nested_events
= vmx_check_nested_events
;
13013 kvm_x86_ops
->get_nested_state
= vmx_get_nested_state
;
13014 kvm_x86_ops
->set_nested_state
= vmx_set_nested_state
;
13015 kvm_x86_ops
->get_vmcs12_pages
= nested_get_vmcs12_pages
,
13016 kvm_x86_ops
->nested_enable_evmcs
= nested_enable_evmcs
;
13021 static __init
int hardware_setup(void)
13023 unsigned long host_bndcfgs
;
13026 rdmsrl_safe(MSR_EFER
, &host_efer
);
13028 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
13029 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
13031 if (setup_vmcs_config(&vmcs_config
, &vmx_capability
) < 0)
13034 if (boot_cpu_has(X86_FEATURE_NX
))
13035 kvm_enable_efer_bits(EFER_NX
);
13037 if (boot_cpu_has(X86_FEATURE_MPX
)) {
13038 rdmsrl(MSR_IA32_BNDCFGS
, host_bndcfgs
);
13039 WARN_ONCE(host_bndcfgs
, "KVM: BNDCFGS in host will be lost");
13042 if (boot_cpu_has(X86_FEATURE_XSAVES
))
13043 rdmsrl(MSR_IA32_XSS
, host_xss
);
13045 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
13046 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
13049 if (!cpu_has_vmx_ept() ||
13050 !cpu_has_vmx_ept_4levels() ||
13051 !cpu_has_vmx_ept_mt_wb() ||
13052 !cpu_has_vmx_invept_global())
13055 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
13056 enable_ept_ad_bits
= 0;
13058 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
13059 enable_unrestricted_guest
= 0;
13061 if (!cpu_has_vmx_flexpriority())
13062 flexpriority_enabled
= 0;
13064 if (!cpu_has_virtual_nmis())
13068 * set_apic_access_page_addr() is used to reload apic access
13069 * page upon invalidation. No need to do anything if not
13070 * using the APIC_ACCESS_ADDR VMCS field.
13072 if (!flexpriority_enabled
)
13073 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
13075 if (!cpu_has_vmx_tpr_shadow())
13076 kvm_x86_ops
->update_cr8_intercept
= NULL
;
13078 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
13079 kvm_disable_largepages();
13081 #if IS_ENABLED(CONFIG_HYPERV)
13082 if (ms_hyperv
.nested_features
& HV_X64_NESTED_GUEST_MAPPING_FLUSH
13084 kvm_x86_ops
->tlb_remote_flush
= vmx_hv_remote_flush_tlb
;
13087 if (!cpu_has_vmx_ple()) {
13090 ple_window_grow
= 0;
13091 ple_window_max
= 0;
13092 ple_window_shrink
= 0;
13095 if (!cpu_has_vmx_apicv()) {
13097 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
13100 if (cpu_has_vmx_tsc_scaling()) {
13101 kvm_has_tsc_control
= true;
13102 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
13103 kvm_tsc_scaling_ratio_frac_bits
= 48;
13106 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
13114 * Only enable PML when hardware supports PML feature, and both EPT
13115 * and EPT A/D bit features are enabled -- PML depends on them to work.
13117 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
13121 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
13122 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
13123 kvm_x86_ops
->flush_log_dirty
= NULL
;
13124 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
13127 if (!cpu_has_vmx_preemption_timer())
13128 kvm_x86_ops
->request_immediate_exit
= __kvm_request_immediate_exit
;
13130 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
13133 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
13134 cpu_preemption_timer_multi
=
13135 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
13137 kvm_x86_ops
->set_hv_timer
= NULL
;
13138 kvm_x86_ops
->cancel_hv_timer
= NULL
;
13141 if (!cpu_has_vmx_shadow_vmcs() || !nested
)
13142 enable_shadow_vmcs
= 0;
13144 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
13146 kvm_mce_cap_supported
|= MCG_LMCE_P
;
13149 nested_vmx_setup_ctls_msrs(&vmcs_config
.nested
,
13150 vmx_capability
.ept
, enable_apicv
);
13152 r
= nested_vmx_hardware_setup(kvm_vmx_exit_handlers
);
13157 r
= alloc_kvm_area();
13159 nested_vmx_hardware_unsetup();
13163 static __exit
void hardware_unsetup(void)
13166 nested_vmx_hardware_unsetup();
13171 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
13172 .cpu_has_kvm_support
= cpu_has_kvm_support
,
13173 .disabled_by_bios
= vmx_disabled_by_bios
,
13174 .hardware_setup
= hardware_setup
,
13175 .hardware_unsetup
= hardware_unsetup
,
13176 .check_processor_compatibility
= vmx_check_processor_compat
,
13177 .hardware_enable
= hardware_enable
,
13178 .hardware_disable
= hardware_disable
,
13179 .cpu_has_accelerated_tpr
= report_flexpriority
,
13180 .has_emulated_msr
= vmx_has_emulated_msr
,
13182 .vm_init
= vmx_vm_init
,
13183 .vm_alloc
= vmx_vm_alloc
,
13184 .vm_free
= vmx_vm_free
,
13186 .vcpu_create
= vmx_create_vcpu
,
13187 .vcpu_free
= vmx_free_vcpu
,
13188 .vcpu_reset
= vmx_vcpu_reset
,
13190 .prepare_guest_switch
= vmx_prepare_switch_to_guest
,
13191 .vcpu_load
= vmx_vcpu_load
,
13192 .vcpu_put
= vmx_vcpu_put
,
13194 .update_bp_intercept
= update_exception_bitmap
,
13195 .get_msr_feature
= vmx_get_msr_feature
,
13196 .get_msr
= vmx_get_msr
,
13197 .set_msr
= vmx_set_msr
,
13198 .get_segment_base
= vmx_get_segment_base
,
13199 .get_segment
= vmx_get_segment
,
13200 .set_segment
= vmx_set_segment
,
13201 .get_cpl
= vmx_get_cpl
,
13202 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
13203 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
13204 .decache_cr3
= vmx_decache_cr3
,
13205 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
13206 .set_cr0
= vmx_set_cr0
,
13207 .set_cr3
= vmx_set_cr3
,
13208 .set_cr4
= vmx_set_cr4
,
13209 .set_efer
= vmx_set_efer
,
13210 .get_idt
= vmx_get_idt
,
13211 .set_idt
= vmx_set_idt
,
13212 .get_gdt
= vmx_get_gdt
,
13213 .set_gdt
= vmx_set_gdt
,
13214 .get_dr6
= vmx_get_dr6
,
13215 .set_dr6
= vmx_set_dr6
,
13216 .set_dr7
= vmx_set_dr7
,
13217 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
13218 .cache_reg
= vmx_cache_reg
,
13219 .get_rflags
= vmx_get_rflags
,
13220 .set_rflags
= vmx_set_rflags
,
13222 .tlb_flush
= vmx_flush_tlb
,
13223 .tlb_flush_gva
= vmx_flush_tlb_gva
,
13225 .run
= vmx_vcpu_run
,
13226 .handle_exit
= vmx_handle_exit
,
13227 .skip_emulated_instruction
= skip_emulated_instruction
,
13228 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
13229 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
13230 .patch_hypercall
= vmx_patch_hypercall
,
13231 .set_irq
= vmx_inject_irq
,
13232 .set_nmi
= vmx_inject_nmi
,
13233 .queue_exception
= vmx_queue_exception
,
13234 .cancel_injection
= vmx_cancel_injection
,
13235 .interrupt_allowed
= vmx_interrupt_allowed
,
13236 .nmi_allowed
= vmx_nmi_allowed
,
13237 .get_nmi_mask
= vmx_get_nmi_mask
,
13238 .set_nmi_mask
= vmx_set_nmi_mask
,
13239 .enable_nmi_window
= enable_nmi_window
,
13240 .enable_irq_window
= enable_irq_window
,
13241 .update_cr8_intercept
= update_cr8_intercept
,
13242 .set_virtual_apic_mode
= vmx_set_virtual_apic_mode
,
13243 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
13244 .get_enable_apicv
= vmx_get_enable_apicv
,
13245 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
13246 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
13247 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
13248 .hwapic_irr_update
= vmx_hwapic_irr_update
,
13249 .hwapic_isr_update
= vmx_hwapic_isr_update
,
13250 .guest_apic_has_interrupt
= vmx_guest_apic_has_interrupt
,
13251 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
13252 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
13254 .set_tss_addr
= vmx_set_tss_addr
,
13255 .set_identity_map_addr
= vmx_set_identity_map_addr
,
13256 .get_tdp_level
= get_ept_level
,
13257 .get_mt_mask
= vmx_get_mt_mask
,
13259 .get_exit_info
= vmx_get_exit_info
,
13261 .get_lpage_level
= vmx_get_lpage_level
,
13263 .cpuid_update
= vmx_cpuid_update
,
13265 .rdtscp_supported
= vmx_rdtscp_supported
,
13266 .invpcid_supported
= vmx_invpcid_supported
,
13268 .set_supported_cpuid
= vmx_set_supported_cpuid
,
13270 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
13272 .read_l1_tsc_offset
= vmx_read_l1_tsc_offset
,
13273 .write_l1_tsc_offset
= vmx_write_l1_tsc_offset
,
13275 .set_tdp_cr3
= vmx_set_cr3
,
13277 .check_intercept
= vmx_check_intercept
,
13278 .handle_external_intr
= vmx_handle_external_intr
,
13279 .mpx_supported
= vmx_mpx_supported
,
13280 .xsaves_supported
= vmx_xsaves_supported
,
13281 .umip_emulated
= vmx_umip_emulated
,
13283 .request_immediate_exit
= vmx_request_immediate_exit
,
13285 .sched_in
= vmx_sched_in
,
13287 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
13288 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
13289 .flush_log_dirty
= vmx_flush_log_dirty
,
13290 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
13291 .write_log_dirty
= vmx_write_pml_buffer
,
13293 .pre_block
= vmx_pre_block
,
13294 .post_block
= vmx_post_block
,
13296 .pmu_ops
= &intel_pmu_ops
,
13298 .update_pi_irte
= vmx_update_pi_irte
,
13300 #ifdef CONFIG_X86_64
13301 .set_hv_timer
= vmx_set_hv_timer
,
13302 .cancel_hv_timer
= vmx_cancel_hv_timer
,
13305 .setup_mce
= vmx_setup_mce
,
13307 .smi_allowed
= vmx_smi_allowed
,
13308 .pre_enter_smm
= vmx_pre_enter_smm
,
13309 .pre_leave_smm
= vmx_pre_leave_smm
,
13310 .enable_smi_window
= enable_smi_window
,
13312 .check_nested_events
= NULL
,
13313 .get_nested_state
= NULL
,
13314 .set_nested_state
= NULL
,
13315 .get_vmcs12_pages
= NULL
,
13316 .nested_enable_evmcs
= NULL
,
13319 static void vmx_cleanup_l1d_flush(void)
13321 if (vmx_l1d_flush_pages
) {
13322 free_pages((unsigned long)vmx_l1d_flush_pages
, L1D_CACHE_ORDER
);
13323 vmx_l1d_flush_pages
= NULL
;
13325 /* Restore state so sysfs ignores VMX */
13326 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
13329 static void vmx_exit(void)
13331 #ifdef CONFIG_KEXEC_CORE
13332 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
13338 #if IS_ENABLED(CONFIG_HYPERV)
13339 if (static_branch_unlikely(&enable_evmcs
)) {
13341 struct hv_vp_assist_page
*vp_ap
;
13343 * Reset everything to support using non-enlightened VMCS
13344 * access later (e.g. when we reload the module with
13345 * enlightened_vmcs=0)
13347 for_each_online_cpu(cpu
) {
13348 vp_ap
= hv_get_vp_assist_page(cpu
);
13353 vp_ap
->current_nested_vmcs
= 0;
13354 vp_ap
->enlighten_vmentry
= 0;
13357 static_branch_disable(&enable_evmcs
);
13360 vmx_cleanup_l1d_flush();
13362 module_exit(vmx_exit
);
13364 static int __init
vmx_init(void)
13368 #if IS_ENABLED(CONFIG_HYPERV)
13370 * Enlightened VMCS usage should be recommended and the host needs
13371 * to support eVMCS v1 or above. We can also disable eVMCS support
13372 * with module parameter.
13374 if (enlightened_vmcs
&&
13375 ms_hyperv
.hints
& HV_X64_ENLIGHTENED_VMCS_RECOMMENDED
&&
13376 (ms_hyperv
.nested_features
& HV_X64_ENLIGHTENED_VMCS_VERSION
) >=
13377 KVM_EVMCS_VERSION
) {
13380 /* Check that we have assist pages on all online CPUs */
13381 for_each_online_cpu(cpu
) {
13382 if (!hv_get_vp_assist_page(cpu
)) {
13383 enlightened_vmcs
= false;
13388 if (enlightened_vmcs
) {
13389 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13390 static_branch_enable(&enable_evmcs
);
13393 enlightened_vmcs
= false;
13397 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
13398 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
13403 * Must be called after kvm_init() so enable_ept is properly set
13404 * up. Hand the parameter mitigation value in which was stored in
13405 * the pre module init parser. If no parameter was given, it will
13406 * contain 'auto' which will be turned into the default 'cond'
13409 if (boot_cpu_has(X86_BUG_L1TF
)) {
13410 r
= vmx_setup_l1d_flush(vmentry_l1d_flush_param
);
13417 #ifdef CONFIG_KEXEC_CORE
13418 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
13419 crash_vmclear_local_loaded_vmcss
);
13421 vmx_check_vmcs12_offsets();
13425 module_init(vmx_init
);