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gpu: host1x: Use SMMU on Tegra124 and Tegra210
[thirdparty/linux.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "mmu.h"
22 #include "i8254.h"
23 #include "tss.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
26 #include "x86.h"
27 #include "cpuid.h"
28 #include "pmu.h"
29 #include "hyperv.h"
30 #include "lapic.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/export.h>
38 #include <linux/moduleparam.h>
39 #include <linux/mman.h>
40 #include <linux/highmem.h>
41 #include <linux/iommu.h>
42 #include <linux/intel-iommu.h>
43 #include <linux/cpufreq.h>
44 #include <linux/user-return-notifier.h>
45 #include <linux/srcu.h>
46 #include <linux/slab.h>
47 #include <linux/perf_event.h>
48 #include <linux/uaccess.h>
49 #include <linux/hash.h>
50 #include <linux/pci.h>
51 #include <linux/timekeeper_internal.h>
52 #include <linux/pvclock_gtod.h>
53 #include <linux/kvm_irqfd.h>
54 #include <linux/irqbypass.h>
55 #include <linux/sched/stat.h>
56 #include <linux/sched/isolation.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
73 #include <asm/emulate_prefix.h>
74 #include <clocksource/hyperv_timer.h>
75
76 #define CREATE_TRACE_POINTS
77 #include "trace.h"
78
79 #define MAX_IO_MSRS 256
80 #define KVM_MAX_MCE_BANKS 32
81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
83
84 #define emul_to_vcpu(ctxt) \
85 ((struct kvm_vcpu *)(ctxt)->vcpu)
86
87 /* EFER defaults:
88 * - enable syscall per default because its emulated by KVM
89 * - enable LME and LMA per default on 64 bit KVM
90 */
91 #ifdef CONFIG_X86_64
92 static
93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
94 #else
95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
96 #endif
97
98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
99
100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void enter_smm(struct kvm_vcpu *vcpu);
109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
110 static void store_regs(struct kvm_vcpu *vcpu);
111 static int sync_regs(struct kvm_vcpu *vcpu);
112
113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
115
116 static bool __read_mostly ignore_msrs = 0;
117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
118
119 static bool __read_mostly report_ignored_msrs = true;
120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
121
122 unsigned int min_timer_period_us = 200;
123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
124
125 static bool __read_mostly kvmclock_periodic_sync = true;
126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
127
128 bool __read_mostly kvm_has_tsc_control;
129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
130 u32 __read_mostly kvm_max_guest_tsc_khz;
131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
134 u64 __read_mostly kvm_max_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
138
139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
140 static u32 __read_mostly tsc_tolerance_ppm = 250;
141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
142
143 /*
144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
145 * adaptive tuning starting from default advancment of 1000ns. '0' disables
146 * advancement entirely. Any other value is used as-is and disables adaptive
147 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
148 */
149 static int __read_mostly lapic_timer_advance_ns = -1;
150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
151
152 static bool __read_mostly vector_hashing = true;
153 module_param(vector_hashing, bool, S_IRUGO);
154
155 bool __read_mostly enable_vmware_backdoor = false;
156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
158
159 static bool __read_mostly force_emulation_prefix = false;
160 module_param(force_emulation_prefix, bool, S_IRUGO);
161
162 int __read_mostly pi_inject_timer = -1;
163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
164
165 #define KVM_NR_SHARED_MSRS 16
166
167 struct kvm_shared_msrs_global {
168 int nr;
169 u32 msrs[KVM_NR_SHARED_MSRS];
170 };
171
172 struct kvm_shared_msrs {
173 struct user_return_notifier urn;
174 bool registered;
175 struct kvm_shared_msr_values {
176 u64 host;
177 u64 curr;
178 } values[KVM_NR_SHARED_MSRS];
179 };
180
181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
182 static struct kvm_shared_msrs __percpu *shared_msrs;
183
184 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
185 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
186 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
187 | XFEATURE_MASK_PKRU)
188
189 u64 __read_mostly host_efer;
190 EXPORT_SYMBOL_GPL(host_efer);
191
192 static u64 __read_mostly host_xss;
193 u64 __read_mostly supported_xss;
194 EXPORT_SYMBOL_GPL(supported_xss);
195
196 struct kvm_stats_debugfs_item debugfs_entries[] = {
197 { "pf_fixed", VCPU_STAT(pf_fixed) },
198 { "pf_guest", VCPU_STAT(pf_guest) },
199 { "tlb_flush", VCPU_STAT(tlb_flush) },
200 { "invlpg", VCPU_STAT(invlpg) },
201 { "exits", VCPU_STAT(exits) },
202 { "io_exits", VCPU_STAT(io_exits) },
203 { "mmio_exits", VCPU_STAT(mmio_exits) },
204 { "signal_exits", VCPU_STAT(signal_exits) },
205 { "irq_window", VCPU_STAT(irq_window_exits) },
206 { "nmi_window", VCPU_STAT(nmi_window_exits) },
207 { "halt_exits", VCPU_STAT(halt_exits) },
208 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
209 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
210 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
211 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
212 { "hypercalls", VCPU_STAT(hypercalls) },
213 { "request_irq", VCPU_STAT(request_irq_exits) },
214 { "irq_exits", VCPU_STAT(irq_exits) },
215 { "host_state_reload", VCPU_STAT(host_state_reload) },
216 { "fpu_reload", VCPU_STAT(fpu_reload) },
217 { "insn_emulation", VCPU_STAT(insn_emulation) },
218 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
219 { "irq_injections", VCPU_STAT(irq_injections) },
220 { "nmi_injections", VCPU_STAT(nmi_injections) },
221 { "req_event", VCPU_STAT(req_event) },
222 { "l1d_flush", VCPU_STAT(l1d_flush) },
223 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
224 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
225 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
226 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
227 { "mmu_flooded", VM_STAT(mmu_flooded) },
228 { "mmu_recycled", VM_STAT(mmu_recycled) },
229 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
230 { "mmu_unsync", VM_STAT(mmu_unsync) },
231 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
232 { "largepages", VM_STAT(lpages, .mode = 0444) },
233 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
234 { "max_mmu_page_hash_collisions",
235 VM_STAT(max_mmu_page_hash_collisions) },
236 { NULL }
237 };
238
239 u64 __read_mostly host_xcr0;
240 u64 __read_mostly supported_xcr0;
241 EXPORT_SYMBOL_GPL(supported_xcr0);
242
243 struct kmem_cache *x86_fpu_cache;
244 EXPORT_SYMBOL_GPL(x86_fpu_cache);
245
246 static struct kmem_cache *x86_emulator_cache;
247
248 static struct kmem_cache *kvm_alloc_emulator_cache(void)
249 {
250 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
251 unsigned int size = sizeof(struct x86_emulate_ctxt);
252
253 return kmem_cache_create_usercopy("x86_emulator", size,
254 __alignof__(struct x86_emulate_ctxt),
255 SLAB_ACCOUNT, useroffset,
256 size - useroffset, NULL);
257 }
258
259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
260
261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
262 {
263 int i;
264 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
265 vcpu->arch.apf.gfns[i] = ~0;
266 }
267
268 static void kvm_on_user_return(struct user_return_notifier *urn)
269 {
270 unsigned slot;
271 struct kvm_shared_msrs *locals
272 = container_of(urn, struct kvm_shared_msrs, urn);
273 struct kvm_shared_msr_values *values;
274 unsigned long flags;
275
276 /*
277 * Disabling irqs at this point since the following code could be
278 * interrupted and executed through kvm_arch_hardware_disable()
279 */
280 local_irq_save(flags);
281 if (locals->registered) {
282 locals->registered = false;
283 user_return_notifier_unregister(urn);
284 }
285 local_irq_restore(flags);
286 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
287 values = &locals->values[slot];
288 if (values->host != values->curr) {
289 wrmsrl(shared_msrs_global.msrs[slot], values->host);
290 values->curr = values->host;
291 }
292 }
293 }
294
295 void kvm_define_shared_msr(unsigned slot, u32 msr)
296 {
297 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
298 shared_msrs_global.msrs[slot] = msr;
299 if (slot >= shared_msrs_global.nr)
300 shared_msrs_global.nr = slot + 1;
301 }
302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
303
304 static void kvm_shared_msr_cpu_online(void)
305 {
306 unsigned int cpu = smp_processor_id();
307 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
308 u64 value;
309 int i;
310
311 for (i = 0; i < shared_msrs_global.nr; ++i) {
312 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
313 smsr->values[i].host = value;
314 smsr->values[i].curr = value;
315 }
316 }
317
318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
319 {
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
322 int err;
323
324 value = (value & mask) | (smsr->values[slot].host & ~mask);
325 if (value == smsr->values[slot].curr)
326 return 0;
327 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
328 if (err)
329 return 1;
330
331 smsr->values[slot].curr = value;
332 if (!smsr->registered) {
333 smsr->urn.on_user_return = kvm_on_user_return;
334 user_return_notifier_register(&smsr->urn);
335 smsr->registered = true;
336 }
337 return 0;
338 }
339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
340
341 static void drop_user_return_notifiers(void)
342 {
343 unsigned int cpu = smp_processor_id();
344 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
345
346 if (smsr->registered)
347 kvm_on_user_return(&smsr->urn);
348 }
349
350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
351 {
352 return vcpu->arch.apic_base;
353 }
354 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
355
356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
357 {
358 return kvm_apic_mode(kvm_get_apic_base(vcpu));
359 }
360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
361
362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
363 {
364 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
365 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
366 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
367 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
368
369 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
370 return 1;
371 if (!msr_info->host_initiated) {
372 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
373 return 1;
374 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
375 return 1;
376 }
377
378 kvm_lapic_set_base(vcpu, msr_info->data);
379 kvm_recalculate_apic_map(vcpu->kvm);
380 return 0;
381 }
382 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
383
384 asmlinkage __visible void kvm_spurious_fault(void)
385 {
386 /* Fault while not rebooting. We want the trace. */
387 BUG_ON(!kvm_rebooting);
388 }
389 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
390
391 #define EXCPT_BENIGN 0
392 #define EXCPT_CONTRIBUTORY 1
393 #define EXCPT_PF 2
394
395 static int exception_class(int vector)
396 {
397 switch (vector) {
398 case PF_VECTOR:
399 return EXCPT_PF;
400 case DE_VECTOR:
401 case TS_VECTOR:
402 case NP_VECTOR:
403 case SS_VECTOR:
404 case GP_VECTOR:
405 return EXCPT_CONTRIBUTORY;
406 default:
407 break;
408 }
409 return EXCPT_BENIGN;
410 }
411
412 #define EXCPT_FAULT 0
413 #define EXCPT_TRAP 1
414 #define EXCPT_ABORT 2
415 #define EXCPT_INTERRUPT 3
416
417 static int exception_type(int vector)
418 {
419 unsigned int mask;
420
421 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
422 return EXCPT_INTERRUPT;
423
424 mask = 1 << vector;
425
426 /* #DB is trap, as instruction watchpoints are handled elsewhere */
427 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
428 return EXCPT_TRAP;
429
430 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
431 return EXCPT_ABORT;
432
433 /* Reserved exceptions will result in fault */
434 return EXCPT_FAULT;
435 }
436
437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
438 {
439 unsigned nr = vcpu->arch.exception.nr;
440 bool has_payload = vcpu->arch.exception.has_payload;
441 unsigned long payload = vcpu->arch.exception.payload;
442
443 if (!has_payload)
444 return;
445
446 switch (nr) {
447 case DB_VECTOR:
448 /*
449 * "Certain debug exceptions may clear bit 0-3. The
450 * remaining contents of the DR6 register are never
451 * cleared by the processor".
452 */
453 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
454 /*
455 * DR6.RTM is set by all #DB exceptions that don't clear it.
456 */
457 vcpu->arch.dr6 |= DR6_RTM;
458 vcpu->arch.dr6 |= payload;
459 /*
460 * Bit 16 should be set in the payload whenever the #DB
461 * exception should clear DR6.RTM. This makes the payload
462 * compatible with the pending debug exceptions under VMX.
463 * Though not currently documented in the SDM, this also
464 * makes the payload compatible with the exit qualification
465 * for #DB exceptions under VMX.
466 */
467 vcpu->arch.dr6 ^= payload & DR6_RTM;
468
469 /*
470 * The #DB payload is defined as compatible with the 'pending
471 * debug exceptions' field under VMX, not DR6. While bit 12 is
472 * defined in the 'pending debug exceptions' field (enabled
473 * breakpoint), it is reserved and must be zero in DR6.
474 */
475 vcpu->arch.dr6 &= ~BIT(12);
476 break;
477 case PF_VECTOR:
478 vcpu->arch.cr2 = payload;
479 break;
480 }
481
482 vcpu->arch.exception.has_payload = false;
483 vcpu->arch.exception.payload = 0;
484 }
485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
486
487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
488 unsigned nr, bool has_error, u32 error_code,
489 bool has_payload, unsigned long payload, bool reinject)
490 {
491 u32 prev_nr;
492 int class1, class2;
493
494 kvm_make_request(KVM_REQ_EVENT, vcpu);
495
496 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
497 queue:
498 if (has_error && !is_protmode(vcpu))
499 has_error = false;
500 if (reinject) {
501 /*
502 * On vmentry, vcpu->arch.exception.pending is only
503 * true if an event injection was blocked by
504 * nested_run_pending. In that case, however,
505 * vcpu_enter_guest requests an immediate exit,
506 * and the guest shouldn't proceed far enough to
507 * need reinjection.
508 */
509 WARN_ON_ONCE(vcpu->arch.exception.pending);
510 vcpu->arch.exception.injected = true;
511 if (WARN_ON_ONCE(has_payload)) {
512 /*
513 * A reinjected event has already
514 * delivered its payload.
515 */
516 has_payload = false;
517 payload = 0;
518 }
519 } else {
520 vcpu->arch.exception.pending = true;
521 vcpu->arch.exception.injected = false;
522 }
523 vcpu->arch.exception.has_error_code = has_error;
524 vcpu->arch.exception.nr = nr;
525 vcpu->arch.exception.error_code = error_code;
526 vcpu->arch.exception.has_payload = has_payload;
527 vcpu->arch.exception.payload = payload;
528 if (!is_guest_mode(vcpu))
529 kvm_deliver_exception_payload(vcpu);
530 return;
531 }
532
533 /* to check exception */
534 prev_nr = vcpu->arch.exception.nr;
535 if (prev_nr == DF_VECTOR) {
536 /* triple fault -> shutdown */
537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
538 return;
539 }
540 class1 = exception_class(prev_nr);
541 class2 = exception_class(nr);
542 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
543 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
544 /*
545 * Generate double fault per SDM Table 5-5. Set
546 * exception.pending = true so that the double fault
547 * can trigger a nested vmexit.
548 */
549 vcpu->arch.exception.pending = true;
550 vcpu->arch.exception.injected = false;
551 vcpu->arch.exception.has_error_code = true;
552 vcpu->arch.exception.nr = DF_VECTOR;
553 vcpu->arch.exception.error_code = 0;
554 vcpu->arch.exception.has_payload = false;
555 vcpu->arch.exception.payload = 0;
556 } else
557 /* replace previous exception with a new one in a hope
558 that instruction re-execution will regenerate lost
559 exception */
560 goto queue;
561 }
562
563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
564 {
565 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
566 }
567 EXPORT_SYMBOL_GPL(kvm_queue_exception);
568
569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
570 {
571 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
572 }
573 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
574
575 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
576 unsigned long payload)
577 {
578 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
579 }
580
581 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
582 u32 error_code, unsigned long payload)
583 {
584 kvm_multiple_exception(vcpu, nr, true, error_code,
585 true, payload, false);
586 }
587
588 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
589 {
590 if (err)
591 kvm_inject_gp(vcpu, 0);
592 else
593 return kvm_skip_emulated_instruction(vcpu);
594
595 return 1;
596 }
597 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
598
599 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
600 {
601 ++vcpu->stat.pf_guest;
602 vcpu->arch.exception.nested_apf =
603 is_guest_mode(vcpu) && fault->async_page_fault;
604 if (vcpu->arch.exception.nested_apf) {
605 vcpu->arch.apf.nested_apf_token = fault->address;
606 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
607 } else {
608 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
609 fault->address);
610 }
611 }
612 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
613
614 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
615 {
616 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
617 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
618 else
619 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
620
621 return fault->nested_page_fault;
622 }
623
624 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
625 {
626 atomic_inc(&vcpu->arch.nmi_queued);
627 kvm_make_request(KVM_REQ_NMI, vcpu);
628 }
629 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
630
631 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
632 {
633 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
634 }
635 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
636
637 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
638 {
639 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
640 }
641 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
642
643 /*
644 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
645 * a #GP and return false.
646 */
647 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
648 {
649 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
650 return true;
651 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
652 return false;
653 }
654 EXPORT_SYMBOL_GPL(kvm_require_cpl);
655
656 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
657 {
658 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
659 return true;
660
661 kvm_queue_exception(vcpu, UD_VECTOR);
662 return false;
663 }
664 EXPORT_SYMBOL_GPL(kvm_require_dr);
665
666 /*
667 * This function will be used to read from the physical memory of the currently
668 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
669 * can read from guest physical or from the guest's guest physical memory.
670 */
671 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
672 gfn_t ngfn, void *data, int offset, int len,
673 u32 access)
674 {
675 struct x86_exception exception;
676 gfn_t real_gfn;
677 gpa_t ngpa;
678
679 ngpa = gfn_to_gpa(ngfn);
680 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
681 if (real_gfn == UNMAPPED_GVA)
682 return -EFAULT;
683
684 real_gfn = gpa_to_gfn(real_gfn);
685
686 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
687 }
688 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
689
690 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
691 void *data, int offset, int len, u32 access)
692 {
693 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
694 data, offset, len, access);
695 }
696
697 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
698 {
699 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
700 rsvd_bits(1, 2);
701 }
702
703 /*
704 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
705 */
706 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
707 {
708 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
709 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
710 int i;
711 int ret;
712 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
713
714 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
715 offset * sizeof(u64), sizeof(pdpte),
716 PFERR_USER_MASK|PFERR_WRITE_MASK);
717 if (ret < 0) {
718 ret = 0;
719 goto out;
720 }
721 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
722 if ((pdpte[i] & PT_PRESENT_MASK) &&
723 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
724 ret = 0;
725 goto out;
726 }
727 }
728 ret = 1;
729
730 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
731 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
732
733 out:
734
735 return ret;
736 }
737 EXPORT_SYMBOL_GPL(load_pdptrs);
738
739 bool pdptrs_changed(struct kvm_vcpu *vcpu)
740 {
741 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
742 int offset;
743 gfn_t gfn;
744 int r;
745
746 if (!is_pae_paging(vcpu))
747 return false;
748
749 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
750 return true;
751
752 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
753 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
754 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
755 PFERR_USER_MASK | PFERR_WRITE_MASK);
756 if (r < 0)
757 return true;
758
759 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
760 }
761 EXPORT_SYMBOL_GPL(pdptrs_changed);
762
763 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
764 {
765 unsigned long old_cr0 = kvm_read_cr0(vcpu);
766 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
767
768 cr0 |= X86_CR0_ET;
769
770 #ifdef CONFIG_X86_64
771 if (cr0 & 0xffffffff00000000UL)
772 return 1;
773 #endif
774
775 cr0 &= ~CR0_RESERVED_BITS;
776
777 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
778 return 1;
779
780 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
781 return 1;
782
783 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
784 #ifdef CONFIG_X86_64
785 if ((vcpu->arch.efer & EFER_LME)) {
786 int cs_db, cs_l;
787
788 if (!is_pae(vcpu))
789 return 1;
790 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
791 if (cs_l)
792 return 1;
793 } else
794 #endif
795 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
796 kvm_read_cr3(vcpu)))
797 return 1;
798 }
799
800 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
801 return 1;
802
803 kvm_x86_ops.set_cr0(vcpu, cr0);
804
805 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
806 kvm_clear_async_pf_completion_queue(vcpu);
807 kvm_async_pf_hash_reset(vcpu);
808 }
809
810 if ((cr0 ^ old_cr0) & update_bits)
811 kvm_mmu_reset_context(vcpu);
812
813 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
814 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
815 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
816 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
817
818 return 0;
819 }
820 EXPORT_SYMBOL_GPL(kvm_set_cr0);
821
822 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
823 {
824 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
825 }
826 EXPORT_SYMBOL_GPL(kvm_lmsw);
827
828 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
829 {
830 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
831
832 if (vcpu->arch.xcr0 != host_xcr0)
833 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
834
835 if (vcpu->arch.xsaves_enabled &&
836 vcpu->arch.ia32_xss != host_xss)
837 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
838 }
839 }
840 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
841
842 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
843 {
844 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
845
846 if (vcpu->arch.xcr0 != host_xcr0)
847 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
848
849 if (vcpu->arch.xsaves_enabled &&
850 vcpu->arch.ia32_xss != host_xss)
851 wrmsrl(MSR_IA32_XSS, host_xss);
852 }
853
854 }
855 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
856
857 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
858 {
859 u64 xcr0 = xcr;
860 u64 old_xcr0 = vcpu->arch.xcr0;
861 u64 valid_bits;
862
863 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
864 if (index != XCR_XFEATURE_ENABLED_MASK)
865 return 1;
866 if (!(xcr0 & XFEATURE_MASK_FP))
867 return 1;
868 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
869 return 1;
870
871 /*
872 * Do not allow the guest to set bits that we do not support
873 * saving. However, xcr0 bit 0 is always set, even if the
874 * emulated CPU does not support XSAVE (see fx_init).
875 */
876 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
877 if (xcr0 & ~valid_bits)
878 return 1;
879
880 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
881 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
882 return 1;
883
884 if (xcr0 & XFEATURE_MASK_AVX512) {
885 if (!(xcr0 & XFEATURE_MASK_YMM))
886 return 1;
887 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
888 return 1;
889 }
890 vcpu->arch.xcr0 = xcr0;
891
892 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
893 kvm_update_cpuid(vcpu);
894 return 0;
895 }
896
897 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
898 {
899 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
900 __kvm_set_xcr(vcpu, index, xcr)) {
901 kvm_inject_gp(vcpu, 0);
902 return 1;
903 }
904 return 0;
905 }
906 EXPORT_SYMBOL_GPL(kvm_set_xcr);
907
908 #define __cr4_reserved_bits(__cpu_has, __c) \
909 ({ \
910 u64 __reserved_bits = CR4_RESERVED_BITS; \
911 \
912 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
913 __reserved_bits |= X86_CR4_OSXSAVE; \
914 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
915 __reserved_bits |= X86_CR4_SMEP; \
916 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
917 __reserved_bits |= X86_CR4_SMAP; \
918 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
919 __reserved_bits |= X86_CR4_FSGSBASE; \
920 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
921 __reserved_bits |= X86_CR4_PKE; \
922 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
923 __reserved_bits |= X86_CR4_LA57; \
924 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
925 __reserved_bits |= X86_CR4_UMIP; \
926 __reserved_bits; \
927 })
928
929 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
930 {
931 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
932
933 if (kvm_cpu_cap_has(X86_FEATURE_LA57))
934 reserved_bits &= ~X86_CR4_LA57;
935
936 if (kvm_cpu_cap_has(X86_FEATURE_UMIP))
937 reserved_bits &= ~X86_CR4_UMIP;
938
939 return reserved_bits;
940 }
941
942 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
943 {
944 if (cr4 & cr4_reserved_bits)
945 return -EINVAL;
946
947 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
948 return -EINVAL;
949
950 return 0;
951 }
952
953 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
954 {
955 unsigned long old_cr4 = kvm_read_cr4(vcpu);
956 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
957 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
958
959 if (kvm_valid_cr4(vcpu, cr4))
960 return 1;
961
962 if (is_long_mode(vcpu)) {
963 if (!(cr4 & X86_CR4_PAE))
964 return 1;
965 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
966 && ((cr4 ^ old_cr4) & pdptr_bits)
967 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
968 kvm_read_cr3(vcpu)))
969 return 1;
970
971 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
972 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
973 return 1;
974
975 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
976 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
977 return 1;
978 }
979
980 if (kvm_x86_ops.set_cr4(vcpu, cr4))
981 return 1;
982
983 if (((cr4 ^ old_cr4) & pdptr_bits) ||
984 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
985 kvm_mmu_reset_context(vcpu);
986
987 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
988 kvm_update_cpuid(vcpu);
989
990 return 0;
991 }
992 EXPORT_SYMBOL_GPL(kvm_set_cr4);
993
994 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
995 {
996 bool skip_tlb_flush = false;
997 #ifdef CONFIG_X86_64
998 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
999
1000 if (pcid_enabled) {
1001 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1002 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1003 }
1004 #endif
1005
1006 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1007 if (!skip_tlb_flush) {
1008 kvm_mmu_sync_roots(vcpu);
1009 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1010 }
1011 return 0;
1012 }
1013
1014 if (is_long_mode(vcpu) &&
1015 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1016 return 1;
1017 else if (is_pae_paging(vcpu) &&
1018 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1019 return 1;
1020
1021 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
1022 vcpu->arch.cr3 = cr3;
1023 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1024
1025 return 0;
1026 }
1027 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1028
1029 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1030 {
1031 if (cr8 & CR8_RESERVED_BITS)
1032 return 1;
1033 if (lapic_in_kernel(vcpu))
1034 kvm_lapic_set_tpr(vcpu, cr8);
1035 else
1036 vcpu->arch.cr8 = cr8;
1037 return 0;
1038 }
1039 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1040
1041 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1042 {
1043 if (lapic_in_kernel(vcpu))
1044 return kvm_lapic_get_cr8(vcpu);
1045 else
1046 return vcpu->arch.cr8;
1047 }
1048 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1049
1050 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1051 {
1052 int i;
1053
1054 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1055 for (i = 0; i < KVM_NR_DB_REGS; i++)
1056 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1057 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1058 }
1059 }
1060
1061 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1062 {
1063 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1064 kvm_x86_ops.set_dr6(vcpu, vcpu->arch.dr6);
1065 }
1066
1067 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1068 {
1069 unsigned long dr7;
1070
1071 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1072 dr7 = vcpu->arch.guest_debug_dr7;
1073 else
1074 dr7 = vcpu->arch.dr7;
1075 kvm_x86_ops.set_dr7(vcpu, dr7);
1076 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1077 if (dr7 & DR7_BP_EN_MASK)
1078 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1079 }
1080
1081 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1082 {
1083 u64 fixed = DR6_FIXED_1;
1084
1085 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1086 fixed |= DR6_RTM;
1087 return fixed;
1088 }
1089
1090 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1091 {
1092 size_t size = ARRAY_SIZE(vcpu->arch.db);
1093
1094 switch (dr) {
1095 case 0 ... 3:
1096 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1097 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1098 vcpu->arch.eff_db[dr] = val;
1099 break;
1100 case 4:
1101 /* fall through */
1102 case 6:
1103 if (val & 0xffffffff00000000ULL)
1104 return -1; /* #GP */
1105 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1106 kvm_update_dr6(vcpu);
1107 break;
1108 case 5:
1109 /* fall through */
1110 default: /* 7 */
1111 if (!kvm_dr7_valid(val))
1112 return -1; /* #GP */
1113 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1114 kvm_update_dr7(vcpu);
1115 break;
1116 }
1117
1118 return 0;
1119 }
1120
1121 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1122 {
1123 if (__kvm_set_dr(vcpu, dr, val)) {
1124 kvm_inject_gp(vcpu, 0);
1125 return 1;
1126 }
1127 return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(kvm_set_dr);
1130
1131 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1132 {
1133 size_t size = ARRAY_SIZE(vcpu->arch.db);
1134
1135 switch (dr) {
1136 case 0 ... 3:
1137 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1138 break;
1139 case 4:
1140 /* fall through */
1141 case 6:
1142 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1143 *val = vcpu->arch.dr6;
1144 else
1145 *val = kvm_x86_ops.get_dr6(vcpu);
1146 break;
1147 case 5:
1148 /* fall through */
1149 default: /* 7 */
1150 *val = vcpu->arch.dr7;
1151 break;
1152 }
1153 return 0;
1154 }
1155 EXPORT_SYMBOL_GPL(kvm_get_dr);
1156
1157 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1158 {
1159 u32 ecx = kvm_rcx_read(vcpu);
1160 u64 data;
1161 int err;
1162
1163 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1164 if (err)
1165 return err;
1166 kvm_rax_write(vcpu, (u32)data);
1167 kvm_rdx_write(vcpu, data >> 32);
1168 return err;
1169 }
1170 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1171
1172 /*
1173 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1174 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1175 *
1176 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1177 * extract the supported MSRs from the related const lists.
1178 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1179 * capabilities of the host cpu. This capabilities test skips MSRs that are
1180 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1181 * may depend on host virtualization features rather than host cpu features.
1182 */
1183
1184 static const u32 msrs_to_save_all[] = {
1185 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1186 MSR_STAR,
1187 #ifdef CONFIG_X86_64
1188 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1189 #endif
1190 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1191 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1192 MSR_IA32_SPEC_CTRL,
1193 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1194 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1195 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1196 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1197 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1198 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1199 MSR_IA32_UMWAIT_CONTROL,
1200
1201 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1202 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1203 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1204 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1205 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1206 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1207 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1208 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1209 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1210 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1211 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1212 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1213 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1214 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1215 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1216 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1217 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1218 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1219 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1220 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1221 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1222 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1223 };
1224
1225 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1226 static unsigned num_msrs_to_save;
1227
1228 static const u32 emulated_msrs_all[] = {
1229 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1230 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1231 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1232 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1233 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1234 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1235 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1236 HV_X64_MSR_RESET,
1237 HV_X64_MSR_VP_INDEX,
1238 HV_X64_MSR_VP_RUNTIME,
1239 HV_X64_MSR_SCONTROL,
1240 HV_X64_MSR_STIMER0_CONFIG,
1241 HV_X64_MSR_VP_ASSIST_PAGE,
1242 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1243 HV_X64_MSR_TSC_EMULATION_STATUS,
1244
1245 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1246 MSR_KVM_PV_EOI_EN,
1247
1248 MSR_IA32_TSC_ADJUST,
1249 MSR_IA32_TSCDEADLINE,
1250 MSR_IA32_ARCH_CAPABILITIES,
1251 MSR_IA32_MISC_ENABLE,
1252 MSR_IA32_MCG_STATUS,
1253 MSR_IA32_MCG_CTL,
1254 MSR_IA32_MCG_EXT_CTL,
1255 MSR_IA32_SMBASE,
1256 MSR_SMI_COUNT,
1257 MSR_PLATFORM_INFO,
1258 MSR_MISC_FEATURES_ENABLES,
1259 MSR_AMD64_VIRT_SPEC_CTRL,
1260 MSR_IA32_POWER_CTL,
1261 MSR_IA32_UCODE_REV,
1262
1263 /*
1264 * The following list leaves out MSRs whose values are determined
1265 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1266 * We always support the "true" VMX control MSRs, even if the host
1267 * processor does not, so I am putting these registers here rather
1268 * than in msrs_to_save_all.
1269 */
1270 MSR_IA32_VMX_BASIC,
1271 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1275 MSR_IA32_VMX_MISC,
1276 MSR_IA32_VMX_CR0_FIXED0,
1277 MSR_IA32_VMX_CR4_FIXED0,
1278 MSR_IA32_VMX_VMCS_ENUM,
1279 MSR_IA32_VMX_PROCBASED_CTLS2,
1280 MSR_IA32_VMX_EPT_VPID_CAP,
1281 MSR_IA32_VMX_VMFUNC,
1282
1283 MSR_K7_HWCR,
1284 MSR_KVM_POLL_CONTROL,
1285 };
1286
1287 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1288 static unsigned num_emulated_msrs;
1289
1290 /*
1291 * List of msr numbers which are used to expose MSR-based features that
1292 * can be used by a hypervisor to validate requested CPU features.
1293 */
1294 static const u32 msr_based_features_all[] = {
1295 MSR_IA32_VMX_BASIC,
1296 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1297 MSR_IA32_VMX_PINBASED_CTLS,
1298 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1299 MSR_IA32_VMX_PROCBASED_CTLS,
1300 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1301 MSR_IA32_VMX_EXIT_CTLS,
1302 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1303 MSR_IA32_VMX_ENTRY_CTLS,
1304 MSR_IA32_VMX_MISC,
1305 MSR_IA32_VMX_CR0_FIXED0,
1306 MSR_IA32_VMX_CR0_FIXED1,
1307 MSR_IA32_VMX_CR4_FIXED0,
1308 MSR_IA32_VMX_CR4_FIXED1,
1309 MSR_IA32_VMX_VMCS_ENUM,
1310 MSR_IA32_VMX_PROCBASED_CTLS2,
1311 MSR_IA32_VMX_EPT_VPID_CAP,
1312 MSR_IA32_VMX_VMFUNC,
1313
1314 MSR_F10H_DECFG,
1315 MSR_IA32_UCODE_REV,
1316 MSR_IA32_ARCH_CAPABILITIES,
1317 };
1318
1319 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1320 static unsigned int num_msr_based_features;
1321
1322 static u64 kvm_get_arch_capabilities(void)
1323 {
1324 u64 data = 0;
1325
1326 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1327 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1328
1329 /*
1330 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1331 * the nested hypervisor runs with NX huge pages. If it is not,
1332 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1333 * L1 guests, so it need not worry about its own (L2) guests.
1334 */
1335 data |= ARCH_CAP_PSCHANGE_MC_NO;
1336
1337 /*
1338 * If we're doing cache flushes (either "always" or "cond")
1339 * we will do one whenever the guest does a vmlaunch/vmresume.
1340 * If an outer hypervisor is doing the cache flush for us
1341 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1342 * capability to the guest too, and if EPT is disabled we're not
1343 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1344 * require a nested hypervisor to do a flush of its own.
1345 */
1346 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1347 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1348
1349 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1350 data |= ARCH_CAP_RDCL_NO;
1351 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1352 data |= ARCH_CAP_SSB_NO;
1353 if (!boot_cpu_has_bug(X86_BUG_MDS))
1354 data |= ARCH_CAP_MDS_NO;
1355
1356 /*
1357 * On TAA affected systems:
1358 * - nothing to do if TSX is disabled on the host.
1359 * - we emulate TSX_CTRL if present on the host.
1360 * This lets the guest use VERW to clear CPU buffers.
1361 */
1362 if (!boot_cpu_has(X86_FEATURE_RTM))
1363 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1364 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1365 data |= ARCH_CAP_TAA_NO;
1366
1367 return data;
1368 }
1369
1370 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1371 {
1372 switch (msr->index) {
1373 case MSR_IA32_ARCH_CAPABILITIES:
1374 msr->data = kvm_get_arch_capabilities();
1375 break;
1376 case MSR_IA32_UCODE_REV:
1377 rdmsrl_safe(msr->index, &msr->data);
1378 break;
1379 default:
1380 if (kvm_x86_ops.get_msr_feature(msr))
1381 return 1;
1382 }
1383 return 0;
1384 }
1385
1386 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1387 {
1388 struct kvm_msr_entry msr;
1389 int r;
1390
1391 msr.index = index;
1392 r = kvm_get_msr_feature(&msr);
1393 if (r)
1394 return r;
1395
1396 *data = msr.data;
1397
1398 return 0;
1399 }
1400
1401 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1402 {
1403 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1404 return false;
1405
1406 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1407 return false;
1408
1409 if (efer & (EFER_LME | EFER_LMA) &&
1410 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1411 return false;
1412
1413 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1414 return false;
1415
1416 return true;
1417
1418 }
1419 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1420 {
1421 if (efer & efer_reserved_bits)
1422 return false;
1423
1424 return __kvm_valid_efer(vcpu, efer);
1425 }
1426 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1427
1428 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1429 {
1430 u64 old_efer = vcpu->arch.efer;
1431 u64 efer = msr_info->data;
1432
1433 if (efer & efer_reserved_bits)
1434 return 1;
1435
1436 if (!msr_info->host_initiated) {
1437 if (!__kvm_valid_efer(vcpu, efer))
1438 return 1;
1439
1440 if (is_paging(vcpu) &&
1441 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1442 return 1;
1443 }
1444
1445 efer &= ~EFER_LMA;
1446 efer |= vcpu->arch.efer & EFER_LMA;
1447
1448 kvm_x86_ops.set_efer(vcpu, efer);
1449
1450 /* Update reserved bits */
1451 if ((efer ^ old_efer) & EFER_NX)
1452 kvm_mmu_reset_context(vcpu);
1453
1454 return 0;
1455 }
1456
1457 void kvm_enable_efer_bits(u64 mask)
1458 {
1459 efer_reserved_bits &= ~mask;
1460 }
1461 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1462
1463 /*
1464 * Write @data into the MSR specified by @index. Select MSR specific fault
1465 * checks are bypassed if @host_initiated is %true.
1466 * Returns 0 on success, non-0 otherwise.
1467 * Assumes vcpu_load() was already called.
1468 */
1469 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1470 bool host_initiated)
1471 {
1472 struct msr_data msr;
1473
1474 switch (index) {
1475 case MSR_FS_BASE:
1476 case MSR_GS_BASE:
1477 case MSR_KERNEL_GS_BASE:
1478 case MSR_CSTAR:
1479 case MSR_LSTAR:
1480 if (is_noncanonical_address(data, vcpu))
1481 return 1;
1482 break;
1483 case MSR_IA32_SYSENTER_EIP:
1484 case MSR_IA32_SYSENTER_ESP:
1485 /*
1486 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1487 * non-canonical address is written on Intel but not on
1488 * AMD (which ignores the top 32-bits, because it does
1489 * not implement 64-bit SYSENTER).
1490 *
1491 * 64-bit code should hence be able to write a non-canonical
1492 * value on AMD. Making the address canonical ensures that
1493 * vmentry does not fail on Intel after writing a non-canonical
1494 * value, and that something deterministic happens if the guest
1495 * invokes 64-bit SYSENTER.
1496 */
1497 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1498 }
1499
1500 msr.data = data;
1501 msr.index = index;
1502 msr.host_initiated = host_initiated;
1503
1504 return kvm_x86_ops.set_msr(vcpu, &msr);
1505 }
1506
1507 /*
1508 * Read the MSR specified by @index into @data. Select MSR specific fault
1509 * checks are bypassed if @host_initiated is %true.
1510 * Returns 0 on success, non-0 otherwise.
1511 * Assumes vcpu_load() was already called.
1512 */
1513 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1514 bool host_initiated)
1515 {
1516 struct msr_data msr;
1517 int ret;
1518
1519 msr.index = index;
1520 msr.host_initiated = host_initiated;
1521
1522 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1523 if (!ret)
1524 *data = msr.data;
1525 return ret;
1526 }
1527
1528 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1529 {
1530 return __kvm_get_msr(vcpu, index, data, false);
1531 }
1532 EXPORT_SYMBOL_GPL(kvm_get_msr);
1533
1534 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1535 {
1536 return __kvm_set_msr(vcpu, index, data, false);
1537 }
1538 EXPORT_SYMBOL_GPL(kvm_set_msr);
1539
1540 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1541 {
1542 u32 ecx = kvm_rcx_read(vcpu);
1543 u64 data;
1544
1545 if (kvm_get_msr(vcpu, ecx, &data)) {
1546 trace_kvm_msr_read_ex(ecx);
1547 kvm_inject_gp(vcpu, 0);
1548 return 1;
1549 }
1550
1551 trace_kvm_msr_read(ecx, data);
1552
1553 kvm_rax_write(vcpu, data & -1u);
1554 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1555 return kvm_skip_emulated_instruction(vcpu);
1556 }
1557 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1558
1559 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1560 {
1561 u32 ecx = kvm_rcx_read(vcpu);
1562 u64 data = kvm_read_edx_eax(vcpu);
1563
1564 if (kvm_set_msr(vcpu, ecx, data)) {
1565 trace_kvm_msr_write_ex(ecx, data);
1566 kvm_inject_gp(vcpu, 0);
1567 return 1;
1568 }
1569
1570 trace_kvm_msr_write(ecx, data);
1571 return kvm_skip_emulated_instruction(vcpu);
1572 }
1573 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1574
1575 /*
1576 * The fast path for frequent and performance sensitive wrmsr emulation,
1577 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1578 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1579 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1580 * other cases which must be called after interrupts are enabled on the host.
1581 */
1582 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1583 {
1584 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1585 return 1;
1586
1587 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1588 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1589 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1590 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1591
1592 data &= ~(1 << 12);
1593 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1594 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1595 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1596 trace_kvm_apic_write(APIC_ICR, (u32)data);
1597 return 0;
1598 }
1599
1600 return 1;
1601 }
1602
1603 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1604 {
1605 u32 msr = kvm_rcx_read(vcpu);
1606 u64 data;
1607 int ret = 0;
1608
1609 switch (msr) {
1610 case APIC_BASE_MSR + (APIC_ICR >> 4):
1611 data = kvm_read_edx_eax(vcpu);
1612 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1613 break;
1614 default:
1615 return EXIT_FASTPATH_NONE;
1616 }
1617
1618 if (!ret) {
1619 trace_kvm_msr_write(msr, data);
1620 return EXIT_FASTPATH_SKIP_EMUL_INS;
1621 }
1622
1623 return EXIT_FASTPATH_NONE;
1624 }
1625 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1626
1627 /*
1628 * Adapt set_msr() to msr_io()'s calling convention
1629 */
1630 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1631 {
1632 return __kvm_get_msr(vcpu, index, data, true);
1633 }
1634
1635 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1636 {
1637 return __kvm_set_msr(vcpu, index, *data, true);
1638 }
1639
1640 #ifdef CONFIG_X86_64
1641 struct pvclock_clock {
1642 int vclock_mode;
1643 u64 cycle_last;
1644 u64 mask;
1645 u32 mult;
1646 u32 shift;
1647 u64 base_cycles;
1648 u64 offset;
1649 };
1650
1651 struct pvclock_gtod_data {
1652 seqcount_t seq;
1653
1654 struct pvclock_clock clock; /* extract of a clocksource struct */
1655 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1656
1657 ktime_t offs_boot;
1658 u64 wall_time_sec;
1659 };
1660
1661 static struct pvclock_gtod_data pvclock_gtod_data;
1662
1663 static void update_pvclock_gtod(struct timekeeper *tk)
1664 {
1665 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1666
1667 write_seqcount_begin(&vdata->seq);
1668
1669 /* copy pvclock gtod data */
1670 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1671 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1672 vdata->clock.mask = tk->tkr_mono.mask;
1673 vdata->clock.mult = tk->tkr_mono.mult;
1674 vdata->clock.shift = tk->tkr_mono.shift;
1675 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1676 vdata->clock.offset = tk->tkr_mono.base;
1677
1678 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1679 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1680 vdata->raw_clock.mask = tk->tkr_raw.mask;
1681 vdata->raw_clock.mult = tk->tkr_raw.mult;
1682 vdata->raw_clock.shift = tk->tkr_raw.shift;
1683 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1684 vdata->raw_clock.offset = tk->tkr_raw.base;
1685
1686 vdata->wall_time_sec = tk->xtime_sec;
1687
1688 vdata->offs_boot = tk->offs_boot;
1689
1690 write_seqcount_end(&vdata->seq);
1691 }
1692
1693 static s64 get_kvmclock_base_ns(void)
1694 {
1695 /* Count up from boot time, but with the frequency of the raw clock. */
1696 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1697 }
1698 #else
1699 static s64 get_kvmclock_base_ns(void)
1700 {
1701 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1702 return ktime_get_boottime_ns();
1703 }
1704 #endif
1705
1706 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1707 {
1708 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1709 kvm_vcpu_kick(vcpu);
1710 }
1711
1712 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1713 {
1714 int version;
1715 int r;
1716 struct pvclock_wall_clock wc;
1717 u64 wall_nsec;
1718
1719 if (!wall_clock)
1720 return;
1721
1722 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1723 if (r)
1724 return;
1725
1726 if (version & 1)
1727 ++version; /* first time write, random junk */
1728
1729 ++version;
1730
1731 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1732 return;
1733
1734 /*
1735 * The guest calculates current wall clock time by adding
1736 * system time (updated by kvm_guest_time_update below) to the
1737 * wall clock specified here. We do the reverse here.
1738 */
1739 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1740
1741 wc.nsec = do_div(wall_nsec, 1000000000);
1742 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1743 wc.version = version;
1744
1745 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1746
1747 version++;
1748 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1749 }
1750
1751 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1752 {
1753 do_shl32_div32(dividend, divisor);
1754 return dividend;
1755 }
1756
1757 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1758 s8 *pshift, u32 *pmultiplier)
1759 {
1760 uint64_t scaled64;
1761 int32_t shift = 0;
1762 uint64_t tps64;
1763 uint32_t tps32;
1764
1765 tps64 = base_hz;
1766 scaled64 = scaled_hz;
1767 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1768 tps64 >>= 1;
1769 shift--;
1770 }
1771
1772 tps32 = (uint32_t)tps64;
1773 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1774 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1775 scaled64 >>= 1;
1776 else
1777 tps32 <<= 1;
1778 shift++;
1779 }
1780
1781 *pshift = shift;
1782 *pmultiplier = div_frac(scaled64, tps32);
1783 }
1784
1785 #ifdef CONFIG_X86_64
1786 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1787 #endif
1788
1789 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1790 static unsigned long max_tsc_khz;
1791
1792 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1793 {
1794 u64 v = (u64)khz * (1000000 + ppm);
1795 do_div(v, 1000000);
1796 return v;
1797 }
1798
1799 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1800 {
1801 u64 ratio;
1802
1803 /* Guest TSC same frequency as host TSC? */
1804 if (!scale) {
1805 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1806 return 0;
1807 }
1808
1809 /* TSC scaling supported? */
1810 if (!kvm_has_tsc_control) {
1811 if (user_tsc_khz > tsc_khz) {
1812 vcpu->arch.tsc_catchup = 1;
1813 vcpu->arch.tsc_always_catchup = 1;
1814 return 0;
1815 } else {
1816 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1817 return -1;
1818 }
1819 }
1820
1821 /* TSC scaling required - calculate ratio */
1822 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1823 user_tsc_khz, tsc_khz);
1824
1825 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1826 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1827 user_tsc_khz);
1828 return -1;
1829 }
1830
1831 vcpu->arch.tsc_scaling_ratio = ratio;
1832 return 0;
1833 }
1834
1835 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1836 {
1837 u32 thresh_lo, thresh_hi;
1838 int use_scaling = 0;
1839
1840 /* tsc_khz can be zero if TSC calibration fails */
1841 if (user_tsc_khz == 0) {
1842 /* set tsc_scaling_ratio to a safe value */
1843 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1844 return -1;
1845 }
1846
1847 /* Compute a scale to convert nanoseconds in TSC cycles */
1848 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1849 &vcpu->arch.virtual_tsc_shift,
1850 &vcpu->arch.virtual_tsc_mult);
1851 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1852
1853 /*
1854 * Compute the variation in TSC rate which is acceptable
1855 * within the range of tolerance and decide if the
1856 * rate being applied is within that bounds of the hardware
1857 * rate. If so, no scaling or compensation need be done.
1858 */
1859 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1860 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1861 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1862 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1863 use_scaling = 1;
1864 }
1865 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1866 }
1867
1868 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1869 {
1870 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1871 vcpu->arch.virtual_tsc_mult,
1872 vcpu->arch.virtual_tsc_shift);
1873 tsc += vcpu->arch.this_tsc_write;
1874 return tsc;
1875 }
1876
1877 static inline int gtod_is_based_on_tsc(int mode)
1878 {
1879 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1880 }
1881
1882 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1883 {
1884 #ifdef CONFIG_X86_64
1885 bool vcpus_matched;
1886 struct kvm_arch *ka = &vcpu->kvm->arch;
1887 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1888
1889 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1890 atomic_read(&vcpu->kvm->online_vcpus));
1891
1892 /*
1893 * Once the masterclock is enabled, always perform request in
1894 * order to update it.
1895 *
1896 * In order to enable masterclock, the host clocksource must be TSC
1897 * and the vcpus need to have matched TSCs. When that happens,
1898 * perform request to enable masterclock.
1899 */
1900 if (ka->use_master_clock ||
1901 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1902 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1903
1904 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1905 atomic_read(&vcpu->kvm->online_vcpus),
1906 ka->use_master_clock, gtod->clock.vclock_mode);
1907 #endif
1908 }
1909
1910 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1911 {
1912 u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1913 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1914 }
1915
1916 /*
1917 * Multiply tsc by a fixed point number represented by ratio.
1918 *
1919 * The most significant 64-N bits (mult) of ratio represent the
1920 * integral part of the fixed point number; the remaining N bits
1921 * (frac) represent the fractional part, ie. ratio represents a fixed
1922 * point number (mult + frac * 2^(-N)).
1923 *
1924 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1925 */
1926 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1927 {
1928 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1929 }
1930
1931 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1932 {
1933 u64 _tsc = tsc;
1934 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1935
1936 if (ratio != kvm_default_tsc_scaling_ratio)
1937 _tsc = __scale_tsc(ratio, tsc);
1938
1939 return _tsc;
1940 }
1941 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1942
1943 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1944 {
1945 u64 tsc;
1946
1947 tsc = kvm_scale_tsc(vcpu, rdtsc());
1948
1949 return target_tsc - tsc;
1950 }
1951
1952 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1953 {
1954 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1955
1956 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1957 }
1958 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1959
1960 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1961 {
1962 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1963 }
1964
1965 static inline bool kvm_check_tsc_unstable(void)
1966 {
1967 #ifdef CONFIG_X86_64
1968 /*
1969 * TSC is marked unstable when we're running on Hyper-V,
1970 * 'TSC page' clocksource is good.
1971 */
1972 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
1973 return false;
1974 #endif
1975 return check_tsc_unstable();
1976 }
1977
1978 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1979 {
1980 struct kvm *kvm = vcpu->kvm;
1981 u64 offset, ns, elapsed;
1982 unsigned long flags;
1983 bool matched;
1984 bool already_matched;
1985 u64 data = msr->data;
1986 bool synchronizing = false;
1987
1988 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1989 offset = kvm_compute_tsc_offset(vcpu, data);
1990 ns = get_kvmclock_base_ns();
1991 elapsed = ns - kvm->arch.last_tsc_nsec;
1992
1993 if (vcpu->arch.virtual_tsc_khz) {
1994 if (data == 0 && msr->host_initiated) {
1995 /*
1996 * detection of vcpu initialization -- need to sync
1997 * with other vCPUs. This particularly helps to keep
1998 * kvm_clock stable after CPU hotplug
1999 */
2000 synchronizing = true;
2001 } else {
2002 u64 tsc_exp = kvm->arch.last_tsc_write +
2003 nsec_to_cycles(vcpu, elapsed);
2004 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2005 /*
2006 * Special case: TSC write with a small delta (1 second)
2007 * of virtual cycle time against real time is
2008 * interpreted as an attempt to synchronize the CPU.
2009 */
2010 synchronizing = data < tsc_exp + tsc_hz &&
2011 data + tsc_hz > tsc_exp;
2012 }
2013 }
2014
2015 /*
2016 * For a reliable TSC, we can match TSC offsets, and for an unstable
2017 * TSC, we add elapsed time in this computation. We could let the
2018 * compensation code attempt to catch up if we fall behind, but
2019 * it's better to try to match offsets from the beginning.
2020 */
2021 if (synchronizing &&
2022 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2023 if (!kvm_check_tsc_unstable()) {
2024 offset = kvm->arch.cur_tsc_offset;
2025 } else {
2026 u64 delta = nsec_to_cycles(vcpu, elapsed);
2027 data += delta;
2028 offset = kvm_compute_tsc_offset(vcpu, data);
2029 }
2030 matched = true;
2031 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2032 } else {
2033 /*
2034 * We split periods of matched TSC writes into generations.
2035 * For each generation, we track the original measured
2036 * nanosecond time, offset, and write, so if TSCs are in
2037 * sync, we can match exact offset, and if not, we can match
2038 * exact software computation in compute_guest_tsc()
2039 *
2040 * These values are tracked in kvm->arch.cur_xxx variables.
2041 */
2042 kvm->arch.cur_tsc_generation++;
2043 kvm->arch.cur_tsc_nsec = ns;
2044 kvm->arch.cur_tsc_write = data;
2045 kvm->arch.cur_tsc_offset = offset;
2046 matched = false;
2047 }
2048
2049 /*
2050 * We also track th most recent recorded KHZ, write and time to
2051 * allow the matching interval to be extended at each write.
2052 */
2053 kvm->arch.last_tsc_nsec = ns;
2054 kvm->arch.last_tsc_write = data;
2055 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2056
2057 vcpu->arch.last_guest_tsc = data;
2058
2059 /* Keep track of which generation this VCPU has synchronized to */
2060 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2061 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2062 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2063
2064 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2065 update_ia32_tsc_adjust_msr(vcpu, offset);
2066
2067 kvm_vcpu_write_tsc_offset(vcpu, offset);
2068 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2069
2070 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2071 if (!matched) {
2072 kvm->arch.nr_vcpus_matched_tsc = 0;
2073 } else if (!already_matched) {
2074 kvm->arch.nr_vcpus_matched_tsc++;
2075 }
2076
2077 kvm_track_tsc_matching(vcpu);
2078 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2079 }
2080
2081 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2082
2083 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2084 s64 adjustment)
2085 {
2086 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
2087 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2088 }
2089
2090 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2091 {
2092 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2093 WARN_ON(adjustment < 0);
2094 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2095 adjust_tsc_offset_guest(vcpu, adjustment);
2096 }
2097
2098 #ifdef CONFIG_X86_64
2099
2100 static u64 read_tsc(void)
2101 {
2102 u64 ret = (u64)rdtsc_ordered();
2103 u64 last = pvclock_gtod_data.clock.cycle_last;
2104
2105 if (likely(ret >= last))
2106 return ret;
2107
2108 /*
2109 * GCC likes to generate cmov here, but this branch is extremely
2110 * predictable (it's just a function of time and the likely is
2111 * very likely) and there's a data dependence, so force GCC
2112 * to generate a branch instead. I don't barrier() because
2113 * we don't actually need a barrier, and if this function
2114 * ever gets inlined it will generate worse code.
2115 */
2116 asm volatile ("");
2117 return last;
2118 }
2119
2120 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2121 int *mode)
2122 {
2123 long v;
2124 u64 tsc_pg_val;
2125
2126 switch (clock->vclock_mode) {
2127 case VDSO_CLOCKMODE_HVCLOCK:
2128 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2129 tsc_timestamp);
2130 if (tsc_pg_val != U64_MAX) {
2131 /* TSC page valid */
2132 *mode = VDSO_CLOCKMODE_HVCLOCK;
2133 v = (tsc_pg_val - clock->cycle_last) &
2134 clock->mask;
2135 } else {
2136 /* TSC page invalid */
2137 *mode = VDSO_CLOCKMODE_NONE;
2138 }
2139 break;
2140 case VDSO_CLOCKMODE_TSC:
2141 *mode = VDSO_CLOCKMODE_TSC;
2142 *tsc_timestamp = read_tsc();
2143 v = (*tsc_timestamp - clock->cycle_last) &
2144 clock->mask;
2145 break;
2146 default:
2147 *mode = VDSO_CLOCKMODE_NONE;
2148 }
2149
2150 if (*mode == VDSO_CLOCKMODE_NONE)
2151 *tsc_timestamp = v = 0;
2152
2153 return v * clock->mult;
2154 }
2155
2156 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2157 {
2158 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2159 unsigned long seq;
2160 int mode;
2161 u64 ns;
2162
2163 do {
2164 seq = read_seqcount_begin(&gtod->seq);
2165 ns = gtod->raw_clock.base_cycles;
2166 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2167 ns >>= gtod->raw_clock.shift;
2168 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2169 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2170 *t = ns;
2171
2172 return mode;
2173 }
2174
2175 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2176 {
2177 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2178 unsigned long seq;
2179 int mode;
2180 u64 ns;
2181
2182 do {
2183 seq = read_seqcount_begin(&gtod->seq);
2184 ts->tv_sec = gtod->wall_time_sec;
2185 ns = gtod->clock.base_cycles;
2186 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2187 ns >>= gtod->clock.shift;
2188 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2189
2190 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2191 ts->tv_nsec = ns;
2192
2193 return mode;
2194 }
2195
2196 /* returns true if host is using TSC based clocksource */
2197 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2198 {
2199 /* checked again under seqlock below */
2200 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2201 return false;
2202
2203 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2204 tsc_timestamp));
2205 }
2206
2207 /* returns true if host is using TSC based clocksource */
2208 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2209 u64 *tsc_timestamp)
2210 {
2211 /* checked again under seqlock below */
2212 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2213 return false;
2214
2215 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2216 }
2217 #endif
2218
2219 /*
2220 *
2221 * Assuming a stable TSC across physical CPUS, and a stable TSC
2222 * across virtual CPUs, the following condition is possible.
2223 * Each numbered line represents an event visible to both
2224 * CPUs at the next numbered event.
2225 *
2226 * "timespecX" represents host monotonic time. "tscX" represents
2227 * RDTSC value.
2228 *
2229 * VCPU0 on CPU0 | VCPU1 on CPU1
2230 *
2231 * 1. read timespec0,tsc0
2232 * 2. | timespec1 = timespec0 + N
2233 * | tsc1 = tsc0 + M
2234 * 3. transition to guest | transition to guest
2235 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2236 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2237 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2238 *
2239 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2240 *
2241 * - ret0 < ret1
2242 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2243 * ...
2244 * - 0 < N - M => M < N
2245 *
2246 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2247 * always the case (the difference between two distinct xtime instances
2248 * might be smaller then the difference between corresponding TSC reads,
2249 * when updating guest vcpus pvclock areas).
2250 *
2251 * To avoid that problem, do not allow visibility of distinct
2252 * system_timestamp/tsc_timestamp values simultaneously: use a master
2253 * copy of host monotonic time values. Update that master copy
2254 * in lockstep.
2255 *
2256 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2257 *
2258 */
2259
2260 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263 struct kvm_arch *ka = &kvm->arch;
2264 int vclock_mode;
2265 bool host_tsc_clocksource, vcpus_matched;
2266
2267 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2268 atomic_read(&kvm->online_vcpus));
2269
2270 /*
2271 * If the host uses TSC clock, then passthrough TSC as stable
2272 * to the guest.
2273 */
2274 host_tsc_clocksource = kvm_get_time_and_clockread(
2275 &ka->master_kernel_ns,
2276 &ka->master_cycle_now);
2277
2278 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2279 && !ka->backwards_tsc_observed
2280 && !ka->boot_vcpu_runs_old_kvmclock;
2281
2282 if (ka->use_master_clock)
2283 atomic_set(&kvm_guest_has_master_clock, 1);
2284
2285 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2286 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2287 vcpus_matched);
2288 #endif
2289 }
2290
2291 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2292 {
2293 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2294 }
2295
2296 static void kvm_gen_update_masterclock(struct kvm *kvm)
2297 {
2298 #ifdef CONFIG_X86_64
2299 int i;
2300 struct kvm_vcpu *vcpu;
2301 struct kvm_arch *ka = &kvm->arch;
2302
2303 spin_lock(&ka->pvclock_gtod_sync_lock);
2304 kvm_make_mclock_inprogress_request(kvm);
2305 /* no guest entries from this point */
2306 pvclock_update_vm_gtod_copy(kvm);
2307
2308 kvm_for_each_vcpu(i, vcpu, kvm)
2309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2310
2311 /* guest entries allowed */
2312 kvm_for_each_vcpu(i, vcpu, kvm)
2313 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2314
2315 spin_unlock(&ka->pvclock_gtod_sync_lock);
2316 #endif
2317 }
2318
2319 u64 get_kvmclock_ns(struct kvm *kvm)
2320 {
2321 struct kvm_arch *ka = &kvm->arch;
2322 struct pvclock_vcpu_time_info hv_clock;
2323 u64 ret;
2324
2325 spin_lock(&ka->pvclock_gtod_sync_lock);
2326 if (!ka->use_master_clock) {
2327 spin_unlock(&ka->pvclock_gtod_sync_lock);
2328 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2329 }
2330
2331 hv_clock.tsc_timestamp = ka->master_cycle_now;
2332 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2333 spin_unlock(&ka->pvclock_gtod_sync_lock);
2334
2335 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2336 get_cpu();
2337
2338 if (__this_cpu_read(cpu_tsc_khz)) {
2339 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2340 &hv_clock.tsc_shift,
2341 &hv_clock.tsc_to_system_mul);
2342 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2343 } else
2344 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2345
2346 put_cpu();
2347
2348 return ret;
2349 }
2350
2351 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2352 {
2353 struct kvm_vcpu_arch *vcpu = &v->arch;
2354 struct pvclock_vcpu_time_info guest_hv_clock;
2355
2356 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2357 &guest_hv_clock, sizeof(guest_hv_clock))))
2358 return;
2359
2360 /* This VCPU is paused, but it's legal for a guest to read another
2361 * VCPU's kvmclock, so we really have to follow the specification where
2362 * it says that version is odd if data is being modified, and even after
2363 * it is consistent.
2364 *
2365 * Version field updates must be kept separate. This is because
2366 * kvm_write_guest_cached might use a "rep movs" instruction, and
2367 * writes within a string instruction are weakly ordered. So there
2368 * are three writes overall.
2369 *
2370 * As a small optimization, only write the version field in the first
2371 * and third write. The vcpu->pv_time cache is still valid, because the
2372 * version field is the first in the struct.
2373 */
2374 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2375
2376 if (guest_hv_clock.version & 1)
2377 ++guest_hv_clock.version; /* first time write, random junk */
2378
2379 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2380 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2381 &vcpu->hv_clock,
2382 sizeof(vcpu->hv_clock.version));
2383
2384 smp_wmb();
2385
2386 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2387 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2388
2389 if (vcpu->pvclock_set_guest_stopped_request) {
2390 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2391 vcpu->pvclock_set_guest_stopped_request = false;
2392 }
2393
2394 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2395
2396 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2397 &vcpu->hv_clock,
2398 sizeof(vcpu->hv_clock));
2399
2400 smp_wmb();
2401
2402 vcpu->hv_clock.version++;
2403 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2404 &vcpu->hv_clock,
2405 sizeof(vcpu->hv_clock.version));
2406 }
2407
2408 static int kvm_guest_time_update(struct kvm_vcpu *v)
2409 {
2410 unsigned long flags, tgt_tsc_khz;
2411 struct kvm_vcpu_arch *vcpu = &v->arch;
2412 struct kvm_arch *ka = &v->kvm->arch;
2413 s64 kernel_ns;
2414 u64 tsc_timestamp, host_tsc;
2415 u8 pvclock_flags;
2416 bool use_master_clock;
2417
2418 kernel_ns = 0;
2419 host_tsc = 0;
2420
2421 /*
2422 * If the host uses TSC clock, then passthrough TSC as stable
2423 * to the guest.
2424 */
2425 spin_lock(&ka->pvclock_gtod_sync_lock);
2426 use_master_clock = ka->use_master_clock;
2427 if (use_master_clock) {
2428 host_tsc = ka->master_cycle_now;
2429 kernel_ns = ka->master_kernel_ns;
2430 }
2431 spin_unlock(&ka->pvclock_gtod_sync_lock);
2432
2433 /* Keep irq disabled to prevent changes to the clock */
2434 local_irq_save(flags);
2435 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2436 if (unlikely(tgt_tsc_khz == 0)) {
2437 local_irq_restore(flags);
2438 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2439 return 1;
2440 }
2441 if (!use_master_clock) {
2442 host_tsc = rdtsc();
2443 kernel_ns = get_kvmclock_base_ns();
2444 }
2445
2446 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2447
2448 /*
2449 * We may have to catch up the TSC to match elapsed wall clock
2450 * time for two reasons, even if kvmclock is used.
2451 * 1) CPU could have been running below the maximum TSC rate
2452 * 2) Broken TSC compensation resets the base at each VCPU
2453 * entry to avoid unknown leaps of TSC even when running
2454 * again on the same CPU. This may cause apparent elapsed
2455 * time to disappear, and the guest to stand still or run
2456 * very slowly.
2457 */
2458 if (vcpu->tsc_catchup) {
2459 u64 tsc = compute_guest_tsc(v, kernel_ns);
2460 if (tsc > tsc_timestamp) {
2461 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2462 tsc_timestamp = tsc;
2463 }
2464 }
2465
2466 local_irq_restore(flags);
2467
2468 /* With all the info we got, fill in the values */
2469
2470 if (kvm_has_tsc_control)
2471 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2472
2473 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2474 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2475 &vcpu->hv_clock.tsc_shift,
2476 &vcpu->hv_clock.tsc_to_system_mul);
2477 vcpu->hw_tsc_khz = tgt_tsc_khz;
2478 }
2479
2480 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2481 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2482 vcpu->last_guest_tsc = tsc_timestamp;
2483
2484 /* If the host uses TSC clocksource, then it is stable */
2485 pvclock_flags = 0;
2486 if (use_master_clock)
2487 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2488
2489 vcpu->hv_clock.flags = pvclock_flags;
2490
2491 if (vcpu->pv_time_enabled)
2492 kvm_setup_pvclock_page(v);
2493 if (v == kvm_get_vcpu(v->kvm, 0))
2494 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2495 return 0;
2496 }
2497
2498 /*
2499 * kvmclock updates which are isolated to a given vcpu, such as
2500 * vcpu->cpu migration, should not allow system_timestamp from
2501 * the rest of the vcpus to remain static. Otherwise ntp frequency
2502 * correction applies to one vcpu's system_timestamp but not
2503 * the others.
2504 *
2505 * So in those cases, request a kvmclock update for all vcpus.
2506 * We need to rate-limit these requests though, as they can
2507 * considerably slow guests that have a large number of vcpus.
2508 * The time for a remote vcpu to update its kvmclock is bound
2509 * by the delay we use to rate-limit the updates.
2510 */
2511
2512 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2513
2514 static void kvmclock_update_fn(struct work_struct *work)
2515 {
2516 int i;
2517 struct delayed_work *dwork = to_delayed_work(work);
2518 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2519 kvmclock_update_work);
2520 struct kvm *kvm = container_of(ka, struct kvm, arch);
2521 struct kvm_vcpu *vcpu;
2522
2523 kvm_for_each_vcpu(i, vcpu, kvm) {
2524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2525 kvm_vcpu_kick(vcpu);
2526 }
2527 }
2528
2529 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2530 {
2531 struct kvm *kvm = v->kvm;
2532
2533 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2534 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2535 KVMCLOCK_UPDATE_DELAY);
2536 }
2537
2538 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2539
2540 static void kvmclock_sync_fn(struct work_struct *work)
2541 {
2542 struct delayed_work *dwork = to_delayed_work(work);
2543 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2544 kvmclock_sync_work);
2545 struct kvm *kvm = container_of(ka, struct kvm, arch);
2546
2547 if (!kvmclock_periodic_sync)
2548 return;
2549
2550 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2551 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2552 KVMCLOCK_SYNC_PERIOD);
2553 }
2554
2555 /*
2556 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2557 */
2558 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2559 {
2560 /* McStatusWrEn enabled? */
2561 if (guest_cpuid_is_amd_or_hygon(vcpu))
2562 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2563
2564 return false;
2565 }
2566
2567 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2568 {
2569 u64 mcg_cap = vcpu->arch.mcg_cap;
2570 unsigned bank_num = mcg_cap & 0xff;
2571 u32 msr = msr_info->index;
2572 u64 data = msr_info->data;
2573
2574 switch (msr) {
2575 case MSR_IA32_MCG_STATUS:
2576 vcpu->arch.mcg_status = data;
2577 break;
2578 case MSR_IA32_MCG_CTL:
2579 if (!(mcg_cap & MCG_CTL_P) &&
2580 (data || !msr_info->host_initiated))
2581 return 1;
2582 if (data != 0 && data != ~(u64)0)
2583 return 1;
2584 vcpu->arch.mcg_ctl = data;
2585 break;
2586 default:
2587 if (msr >= MSR_IA32_MC0_CTL &&
2588 msr < MSR_IA32_MCx_CTL(bank_num)) {
2589 u32 offset = array_index_nospec(
2590 msr - MSR_IA32_MC0_CTL,
2591 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2592
2593 /* only 0 or all 1s can be written to IA32_MCi_CTL
2594 * some Linux kernels though clear bit 10 in bank 4 to
2595 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2596 * this to avoid an uncatched #GP in the guest
2597 */
2598 if ((offset & 0x3) == 0 &&
2599 data != 0 && (data | (1 << 10)) != ~(u64)0)
2600 return -1;
2601
2602 /* MCi_STATUS */
2603 if (!msr_info->host_initiated &&
2604 (offset & 0x3) == 1 && data != 0) {
2605 if (!can_set_mci_status(vcpu))
2606 return -1;
2607 }
2608
2609 vcpu->arch.mce_banks[offset] = data;
2610 break;
2611 }
2612 return 1;
2613 }
2614 return 0;
2615 }
2616
2617 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2618 {
2619 struct kvm *kvm = vcpu->kvm;
2620 int lm = is_long_mode(vcpu);
2621 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2622 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2623 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2624 : kvm->arch.xen_hvm_config.blob_size_32;
2625 u32 page_num = data & ~PAGE_MASK;
2626 u64 page_addr = data & PAGE_MASK;
2627 u8 *page;
2628 int r;
2629
2630 r = -E2BIG;
2631 if (page_num >= blob_size)
2632 goto out;
2633 r = -ENOMEM;
2634 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2635 if (IS_ERR(page)) {
2636 r = PTR_ERR(page);
2637 goto out;
2638 }
2639 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2640 goto out_free;
2641 r = 0;
2642 out_free:
2643 kfree(page);
2644 out:
2645 return r;
2646 }
2647
2648 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2649 {
2650 gpa_t gpa = data & ~0x3f;
2651
2652 /* Bits 3:5 are reserved, Should be zero */
2653 if (data & 0x38)
2654 return 1;
2655
2656 vcpu->arch.apf.msr_val = data;
2657
2658 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2659 kvm_clear_async_pf_completion_queue(vcpu);
2660 kvm_async_pf_hash_reset(vcpu);
2661 return 0;
2662 }
2663
2664 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2665 sizeof(u32)))
2666 return 1;
2667
2668 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2669 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2670 kvm_async_pf_wakeup_all(vcpu);
2671 return 0;
2672 }
2673
2674 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2675 {
2676 vcpu->arch.pv_time_enabled = false;
2677 vcpu->arch.time = 0;
2678 }
2679
2680 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2681 {
2682 ++vcpu->stat.tlb_flush;
2683 kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa);
2684 }
2685
2686 static void record_steal_time(struct kvm_vcpu *vcpu)
2687 {
2688 struct kvm_host_map map;
2689 struct kvm_steal_time *st;
2690
2691 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2692 return;
2693
2694 /* -EAGAIN is returned in atomic context so we can just return. */
2695 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2696 &map, &vcpu->arch.st.cache, false))
2697 return;
2698
2699 st = map.hva +
2700 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2701
2702 /*
2703 * Doing a TLB flush here, on the guest's behalf, can avoid
2704 * expensive IPIs.
2705 */
2706 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2707 st->preempted & KVM_VCPU_FLUSH_TLB);
2708 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2709 kvm_vcpu_flush_tlb(vcpu, false);
2710
2711 vcpu->arch.st.preempted = 0;
2712
2713 if (st->version & 1)
2714 st->version += 1; /* first time write, random junk */
2715
2716 st->version += 1;
2717
2718 smp_wmb();
2719
2720 st->steal += current->sched_info.run_delay -
2721 vcpu->arch.st.last_steal;
2722 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2723
2724 smp_wmb();
2725
2726 st->version += 1;
2727
2728 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2729 }
2730
2731 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2732 {
2733 bool pr = false;
2734 u32 msr = msr_info->index;
2735 u64 data = msr_info->data;
2736
2737 switch (msr) {
2738 case MSR_AMD64_NB_CFG:
2739 case MSR_IA32_UCODE_WRITE:
2740 case MSR_VM_HSAVE_PA:
2741 case MSR_AMD64_PATCH_LOADER:
2742 case MSR_AMD64_BU_CFG2:
2743 case MSR_AMD64_DC_CFG:
2744 case MSR_F15H_EX_CFG:
2745 break;
2746
2747 case MSR_IA32_UCODE_REV:
2748 if (msr_info->host_initiated)
2749 vcpu->arch.microcode_version = data;
2750 break;
2751 case MSR_IA32_ARCH_CAPABILITIES:
2752 if (!msr_info->host_initiated)
2753 return 1;
2754 vcpu->arch.arch_capabilities = data;
2755 break;
2756 case MSR_EFER:
2757 return set_efer(vcpu, msr_info);
2758 case MSR_K7_HWCR:
2759 data &= ~(u64)0x40; /* ignore flush filter disable */
2760 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2761 data &= ~(u64)0x8; /* ignore TLB cache disable */
2762
2763 /* Handle McStatusWrEn */
2764 if (data == BIT_ULL(18)) {
2765 vcpu->arch.msr_hwcr = data;
2766 } else if (data != 0) {
2767 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2768 data);
2769 return 1;
2770 }
2771 break;
2772 case MSR_FAM10H_MMIO_CONF_BASE:
2773 if (data != 0) {
2774 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2775 "0x%llx\n", data);
2776 return 1;
2777 }
2778 break;
2779 case MSR_IA32_DEBUGCTLMSR:
2780 if (!data) {
2781 /* We support the non-activated case already */
2782 break;
2783 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2784 /* Values other than LBR and BTF are vendor-specific,
2785 thus reserved and should throw a #GP */
2786 return 1;
2787 }
2788 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2789 __func__, data);
2790 break;
2791 case 0x200 ... 0x2ff:
2792 return kvm_mtrr_set_msr(vcpu, msr, data);
2793 case MSR_IA32_APICBASE:
2794 return kvm_set_apic_base(vcpu, msr_info);
2795 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2796 return kvm_x2apic_msr_write(vcpu, msr, data);
2797 case MSR_IA32_TSCDEADLINE:
2798 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2799 break;
2800 case MSR_IA32_TSC_ADJUST:
2801 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2802 if (!msr_info->host_initiated) {
2803 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2804 adjust_tsc_offset_guest(vcpu, adj);
2805 }
2806 vcpu->arch.ia32_tsc_adjust_msr = data;
2807 }
2808 break;
2809 case MSR_IA32_MISC_ENABLE:
2810 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2811 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2812 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2813 return 1;
2814 vcpu->arch.ia32_misc_enable_msr = data;
2815 kvm_update_cpuid(vcpu);
2816 } else {
2817 vcpu->arch.ia32_misc_enable_msr = data;
2818 }
2819 break;
2820 case MSR_IA32_SMBASE:
2821 if (!msr_info->host_initiated)
2822 return 1;
2823 vcpu->arch.smbase = data;
2824 break;
2825 case MSR_IA32_POWER_CTL:
2826 vcpu->arch.msr_ia32_power_ctl = data;
2827 break;
2828 case MSR_IA32_TSC:
2829 kvm_write_tsc(vcpu, msr_info);
2830 break;
2831 case MSR_IA32_XSS:
2832 if (!msr_info->host_initiated &&
2833 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2834 return 1;
2835 /*
2836 * KVM supports exposing PT to the guest, but does not support
2837 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2838 * XSAVES/XRSTORS to save/restore PT MSRs.
2839 */
2840 if (data & ~supported_xss)
2841 return 1;
2842 vcpu->arch.ia32_xss = data;
2843 break;
2844 case MSR_SMI_COUNT:
2845 if (!msr_info->host_initiated)
2846 return 1;
2847 vcpu->arch.smi_count = data;
2848 break;
2849 case MSR_KVM_WALL_CLOCK_NEW:
2850 case MSR_KVM_WALL_CLOCK:
2851 vcpu->kvm->arch.wall_clock = data;
2852 kvm_write_wall_clock(vcpu->kvm, data);
2853 break;
2854 case MSR_KVM_SYSTEM_TIME_NEW:
2855 case MSR_KVM_SYSTEM_TIME: {
2856 struct kvm_arch *ka = &vcpu->kvm->arch;
2857
2858 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2859 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2860
2861 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2862 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2863
2864 ka->boot_vcpu_runs_old_kvmclock = tmp;
2865 }
2866
2867 vcpu->arch.time = data;
2868 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2869
2870 /* we verify if the enable bit is set... */
2871 vcpu->arch.pv_time_enabled = false;
2872 if (!(data & 1))
2873 break;
2874
2875 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2876 &vcpu->arch.pv_time, data & ~1ULL,
2877 sizeof(struct pvclock_vcpu_time_info)))
2878 vcpu->arch.pv_time_enabled = true;
2879
2880 break;
2881 }
2882 case MSR_KVM_ASYNC_PF_EN:
2883 if (kvm_pv_enable_async_pf(vcpu, data))
2884 return 1;
2885 break;
2886 case MSR_KVM_STEAL_TIME:
2887
2888 if (unlikely(!sched_info_on()))
2889 return 1;
2890
2891 if (data & KVM_STEAL_RESERVED_MASK)
2892 return 1;
2893
2894 vcpu->arch.st.msr_val = data;
2895
2896 if (!(data & KVM_MSR_ENABLED))
2897 break;
2898
2899 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2900
2901 break;
2902 case MSR_KVM_PV_EOI_EN:
2903 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2904 return 1;
2905 break;
2906
2907 case MSR_KVM_POLL_CONTROL:
2908 /* only enable bit supported */
2909 if (data & (-1ULL << 1))
2910 return 1;
2911
2912 vcpu->arch.msr_kvm_poll_control = data;
2913 break;
2914
2915 case MSR_IA32_MCG_CTL:
2916 case MSR_IA32_MCG_STATUS:
2917 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2918 return set_msr_mce(vcpu, msr_info);
2919
2920 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2921 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2922 pr = true; /* fall through */
2923 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2924 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2925 if (kvm_pmu_is_valid_msr(vcpu, msr))
2926 return kvm_pmu_set_msr(vcpu, msr_info);
2927
2928 if (pr || data != 0)
2929 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2930 "0x%x data 0x%llx\n", msr, data);
2931 break;
2932 case MSR_K7_CLK_CTL:
2933 /*
2934 * Ignore all writes to this no longer documented MSR.
2935 * Writes are only relevant for old K7 processors,
2936 * all pre-dating SVM, but a recommended workaround from
2937 * AMD for these chips. It is possible to specify the
2938 * affected processor models on the command line, hence
2939 * the need to ignore the workaround.
2940 */
2941 break;
2942 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2943 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2944 case HV_X64_MSR_CRASH_CTL:
2945 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2946 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2947 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2948 case HV_X64_MSR_TSC_EMULATION_STATUS:
2949 return kvm_hv_set_msr_common(vcpu, msr, data,
2950 msr_info->host_initiated);
2951 case MSR_IA32_BBL_CR_CTL3:
2952 /* Drop writes to this legacy MSR -- see rdmsr
2953 * counterpart for further detail.
2954 */
2955 if (report_ignored_msrs)
2956 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2957 msr, data);
2958 break;
2959 case MSR_AMD64_OSVW_ID_LENGTH:
2960 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2961 return 1;
2962 vcpu->arch.osvw.length = data;
2963 break;
2964 case MSR_AMD64_OSVW_STATUS:
2965 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2966 return 1;
2967 vcpu->arch.osvw.status = data;
2968 break;
2969 case MSR_PLATFORM_INFO:
2970 if (!msr_info->host_initiated ||
2971 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2972 cpuid_fault_enabled(vcpu)))
2973 return 1;
2974 vcpu->arch.msr_platform_info = data;
2975 break;
2976 case MSR_MISC_FEATURES_ENABLES:
2977 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2978 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2979 !supports_cpuid_fault(vcpu)))
2980 return 1;
2981 vcpu->arch.msr_misc_features_enables = data;
2982 break;
2983 default:
2984 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2985 return xen_hvm_config(vcpu, data);
2986 if (kvm_pmu_is_valid_msr(vcpu, msr))
2987 return kvm_pmu_set_msr(vcpu, msr_info);
2988 if (!ignore_msrs) {
2989 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2990 msr, data);
2991 return 1;
2992 } else {
2993 if (report_ignored_msrs)
2994 vcpu_unimpl(vcpu,
2995 "ignored wrmsr: 0x%x data 0x%llx\n",
2996 msr, data);
2997 break;
2998 }
2999 }
3000 return 0;
3001 }
3002 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3003
3004 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3005 {
3006 u64 data;
3007 u64 mcg_cap = vcpu->arch.mcg_cap;
3008 unsigned bank_num = mcg_cap & 0xff;
3009
3010 switch (msr) {
3011 case MSR_IA32_P5_MC_ADDR:
3012 case MSR_IA32_P5_MC_TYPE:
3013 data = 0;
3014 break;
3015 case MSR_IA32_MCG_CAP:
3016 data = vcpu->arch.mcg_cap;
3017 break;
3018 case MSR_IA32_MCG_CTL:
3019 if (!(mcg_cap & MCG_CTL_P) && !host)
3020 return 1;
3021 data = vcpu->arch.mcg_ctl;
3022 break;
3023 case MSR_IA32_MCG_STATUS:
3024 data = vcpu->arch.mcg_status;
3025 break;
3026 default:
3027 if (msr >= MSR_IA32_MC0_CTL &&
3028 msr < MSR_IA32_MCx_CTL(bank_num)) {
3029 u32 offset = array_index_nospec(
3030 msr - MSR_IA32_MC0_CTL,
3031 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3032
3033 data = vcpu->arch.mce_banks[offset];
3034 break;
3035 }
3036 return 1;
3037 }
3038 *pdata = data;
3039 return 0;
3040 }
3041
3042 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3043 {
3044 switch (msr_info->index) {
3045 case MSR_IA32_PLATFORM_ID:
3046 case MSR_IA32_EBL_CR_POWERON:
3047 case MSR_IA32_DEBUGCTLMSR:
3048 case MSR_IA32_LASTBRANCHFROMIP:
3049 case MSR_IA32_LASTBRANCHTOIP:
3050 case MSR_IA32_LASTINTFROMIP:
3051 case MSR_IA32_LASTINTTOIP:
3052 case MSR_K8_SYSCFG:
3053 case MSR_K8_TSEG_ADDR:
3054 case MSR_K8_TSEG_MASK:
3055 case MSR_VM_HSAVE_PA:
3056 case MSR_K8_INT_PENDING_MSG:
3057 case MSR_AMD64_NB_CFG:
3058 case MSR_FAM10H_MMIO_CONF_BASE:
3059 case MSR_AMD64_BU_CFG2:
3060 case MSR_IA32_PERF_CTL:
3061 case MSR_AMD64_DC_CFG:
3062 case MSR_F15H_EX_CFG:
3063 msr_info->data = 0;
3064 break;
3065 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3066 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3067 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3068 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3069 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3070 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3071 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3072 msr_info->data = 0;
3073 break;
3074 case MSR_IA32_UCODE_REV:
3075 msr_info->data = vcpu->arch.microcode_version;
3076 break;
3077 case MSR_IA32_ARCH_CAPABILITIES:
3078 if (!msr_info->host_initiated &&
3079 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3080 return 1;
3081 msr_info->data = vcpu->arch.arch_capabilities;
3082 break;
3083 case MSR_IA32_POWER_CTL:
3084 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3085 break;
3086 case MSR_IA32_TSC:
3087 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3088 break;
3089 case MSR_MTRRcap:
3090 case 0x200 ... 0x2ff:
3091 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3092 case 0xcd: /* fsb frequency */
3093 msr_info->data = 3;
3094 break;
3095 /*
3096 * MSR_EBC_FREQUENCY_ID
3097 * Conservative value valid for even the basic CPU models.
3098 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3099 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3100 * and 266MHz for model 3, or 4. Set Core Clock
3101 * Frequency to System Bus Frequency Ratio to 1 (bits
3102 * 31:24) even though these are only valid for CPU
3103 * models > 2, however guests may end up dividing or
3104 * multiplying by zero otherwise.
3105 */
3106 case MSR_EBC_FREQUENCY_ID:
3107 msr_info->data = 1 << 24;
3108 break;
3109 case MSR_IA32_APICBASE:
3110 msr_info->data = kvm_get_apic_base(vcpu);
3111 break;
3112 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3113 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3114 case MSR_IA32_TSCDEADLINE:
3115 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3116 break;
3117 case MSR_IA32_TSC_ADJUST:
3118 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3119 break;
3120 case MSR_IA32_MISC_ENABLE:
3121 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3122 break;
3123 case MSR_IA32_SMBASE:
3124 if (!msr_info->host_initiated)
3125 return 1;
3126 msr_info->data = vcpu->arch.smbase;
3127 break;
3128 case MSR_SMI_COUNT:
3129 msr_info->data = vcpu->arch.smi_count;
3130 break;
3131 case MSR_IA32_PERF_STATUS:
3132 /* TSC increment by tick */
3133 msr_info->data = 1000ULL;
3134 /* CPU multiplier */
3135 msr_info->data |= (((uint64_t)4ULL) << 40);
3136 break;
3137 case MSR_EFER:
3138 msr_info->data = vcpu->arch.efer;
3139 break;
3140 case MSR_KVM_WALL_CLOCK:
3141 case MSR_KVM_WALL_CLOCK_NEW:
3142 msr_info->data = vcpu->kvm->arch.wall_clock;
3143 break;
3144 case MSR_KVM_SYSTEM_TIME:
3145 case MSR_KVM_SYSTEM_TIME_NEW:
3146 msr_info->data = vcpu->arch.time;
3147 break;
3148 case MSR_KVM_ASYNC_PF_EN:
3149 msr_info->data = vcpu->arch.apf.msr_val;
3150 break;
3151 case MSR_KVM_STEAL_TIME:
3152 msr_info->data = vcpu->arch.st.msr_val;
3153 break;
3154 case MSR_KVM_PV_EOI_EN:
3155 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3156 break;
3157 case MSR_KVM_POLL_CONTROL:
3158 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3159 break;
3160 case MSR_IA32_P5_MC_ADDR:
3161 case MSR_IA32_P5_MC_TYPE:
3162 case MSR_IA32_MCG_CAP:
3163 case MSR_IA32_MCG_CTL:
3164 case MSR_IA32_MCG_STATUS:
3165 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3166 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3167 msr_info->host_initiated);
3168 case MSR_IA32_XSS:
3169 if (!msr_info->host_initiated &&
3170 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3171 return 1;
3172 msr_info->data = vcpu->arch.ia32_xss;
3173 break;
3174 case MSR_K7_CLK_CTL:
3175 /*
3176 * Provide expected ramp-up count for K7. All other
3177 * are set to zero, indicating minimum divisors for
3178 * every field.
3179 *
3180 * This prevents guest kernels on AMD host with CPU
3181 * type 6, model 8 and higher from exploding due to
3182 * the rdmsr failing.
3183 */
3184 msr_info->data = 0x20000000;
3185 break;
3186 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3187 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3188 case HV_X64_MSR_CRASH_CTL:
3189 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3190 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3191 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3192 case HV_X64_MSR_TSC_EMULATION_STATUS:
3193 return kvm_hv_get_msr_common(vcpu,
3194 msr_info->index, &msr_info->data,
3195 msr_info->host_initiated);
3196 case MSR_IA32_BBL_CR_CTL3:
3197 /* This legacy MSR exists but isn't fully documented in current
3198 * silicon. It is however accessed by winxp in very narrow
3199 * scenarios where it sets bit #19, itself documented as
3200 * a "reserved" bit. Best effort attempt to source coherent
3201 * read data here should the balance of the register be
3202 * interpreted by the guest:
3203 *
3204 * L2 cache control register 3: 64GB range, 256KB size,
3205 * enabled, latency 0x1, configured
3206 */
3207 msr_info->data = 0xbe702111;
3208 break;
3209 case MSR_AMD64_OSVW_ID_LENGTH:
3210 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3211 return 1;
3212 msr_info->data = vcpu->arch.osvw.length;
3213 break;
3214 case MSR_AMD64_OSVW_STATUS:
3215 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3216 return 1;
3217 msr_info->data = vcpu->arch.osvw.status;
3218 break;
3219 case MSR_PLATFORM_INFO:
3220 if (!msr_info->host_initiated &&
3221 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3222 return 1;
3223 msr_info->data = vcpu->arch.msr_platform_info;
3224 break;
3225 case MSR_MISC_FEATURES_ENABLES:
3226 msr_info->data = vcpu->arch.msr_misc_features_enables;
3227 break;
3228 case MSR_K7_HWCR:
3229 msr_info->data = vcpu->arch.msr_hwcr;
3230 break;
3231 default:
3232 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3233 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3234 if (!ignore_msrs) {
3235 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3236 msr_info->index);
3237 return 1;
3238 } else {
3239 if (report_ignored_msrs)
3240 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3241 msr_info->index);
3242 msr_info->data = 0;
3243 }
3244 break;
3245 }
3246 return 0;
3247 }
3248 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3249
3250 /*
3251 * Read or write a bunch of msrs. All parameters are kernel addresses.
3252 *
3253 * @return number of msrs set successfully.
3254 */
3255 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3256 struct kvm_msr_entry *entries,
3257 int (*do_msr)(struct kvm_vcpu *vcpu,
3258 unsigned index, u64 *data))
3259 {
3260 int i;
3261
3262 for (i = 0; i < msrs->nmsrs; ++i)
3263 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3264 break;
3265
3266 return i;
3267 }
3268
3269 /*
3270 * Read or write a bunch of msrs. Parameters are user addresses.
3271 *
3272 * @return number of msrs set successfully.
3273 */
3274 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3275 int (*do_msr)(struct kvm_vcpu *vcpu,
3276 unsigned index, u64 *data),
3277 int writeback)
3278 {
3279 struct kvm_msrs msrs;
3280 struct kvm_msr_entry *entries;
3281 int r, n;
3282 unsigned size;
3283
3284 r = -EFAULT;
3285 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3286 goto out;
3287
3288 r = -E2BIG;
3289 if (msrs.nmsrs >= MAX_IO_MSRS)
3290 goto out;
3291
3292 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3293 entries = memdup_user(user_msrs->entries, size);
3294 if (IS_ERR(entries)) {
3295 r = PTR_ERR(entries);
3296 goto out;
3297 }
3298
3299 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3300 if (r < 0)
3301 goto out_free;
3302
3303 r = -EFAULT;
3304 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3305 goto out_free;
3306
3307 r = n;
3308
3309 out_free:
3310 kfree(entries);
3311 out:
3312 return r;
3313 }
3314
3315 static inline bool kvm_can_mwait_in_guest(void)
3316 {
3317 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3318 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3319 boot_cpu_has(X86_FEATURE_ARAT);
3320 }
3321
3322 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3323 {
3324 int r = 0;
3325
3326 switch (ext) {
3327 case KVM_CAP_IRQCHIP:
3328 case KVM_CAP_HLT:
3329 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3330 case KVM_CAP_SET_TSS_ADDR:
3331 case KVM_CAP_EXT_CPUID:
3332 case KVM_CAP_EXT_EMUL_CPUID:
3333 case KVM_CAP_CLOCKSOURCE:
3334 case KVM_CAP_PIT:
3335 case KVM_CAP_NOP_IO_DELAY:
3336 case KVM_CAP_MP_STATE:
3337 case KVM_CAP_SYNC_MMU:
3338 case KVM_CAP_USER_NMI:
3339 case KVM_CAP_REINJECT_CONTROL:
3340 case KVM_CAP_IRQ_INJECT_STATUS:
3341 case KVM_CAP_IOEVENTFD:
3342 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3343 case KVM_CAP_PIT2:
3344 case KVM_CAP_PIT_STATE2:
3345 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3346 case KVM_CAP_XEN_HVM:
3347 case KVM_CAP_VCPU_EVENTS:
3348 case KVM_CAP_HYPERV:
3349 case KVM_CAP_HYPERV_VAPIC:
3350 case KVM_CAP_HYPERV_SPIN:
3351 case KVM_CAP_HYPERV_SYNIC:
3352 case KVM_CAP_HYPERV_SYNIC2:
3353 case KVM_CAP_HYPERV_VP_INDEX:
3354 case KVM_CAP_HYPERV_EVENTFD:
3355 case KVM_CAP_HYPERV_TLBFLUSH:
3356 case KVM_CAP_HYPERV_SEND_IPI:
3357 case KVM_CAP_HYPERV_CPUID:
3358 case KVM_CAP_PCI_SEGMENT:
3359 case KVM_CAP_DEBUGREGS:
3360 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3361 case KVM_CAP_XSAVE:
3362 case KVM_CAP_ASYNC_PF:
3363 case KVM_CAP_GET_TSC_KHZ:
3364 case KVM_CAP_KVMCLOCK_CTRL:
3365 case KVM_CAP_READONLY_MEM:
3366 case KVM_CAP_HYPERV_TIME:
3367 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3368 case KVM_CAP_TSC_DEADLINE_TIMER:
3369 case KVM_CAP_DISABLE_QUIRKS:
3370 case KVM_CAP_SET_BOOT_CPU_ID:
3371 case KVM_CAP_SPLIT_IRQCHIP:
3372 case KVM_CAP_IMMEDIATE_EXIT:
3373 case KVM_CAP_PMU_EVENT_FILTER:
3374 case KVM_CAP_GET_MSR_FEATURES:
3375 case KVM_CAP_MSR_PLATFORM_INFO:
3376 case KVM_CAP_EXCEPTION_PAYLOAD:
3377 r = 1;
3378 break;
3379 case KVM_CAP_SYNC_REGS:
3380 r = KVM_SYNC_X86_VALID_FIELDS;
3381 break;
3382 case KVM_CAP_ADJUST_CLOCK:
3383 r = KVM_CLOCK_TSC_STABLE;
3384 break;
3385 case KVM_CAP_X86_DISABLE_EXITS:
3386 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3387 KVM_X86_DISABLE_EXITS_CSTATE;
3388 if(kvm_can_mwait_in_guest())
3389 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3390 break;
3391 case KVM_CAP_X86_SMM:
3392 /* SMBASE is usually relocated above 1M on modern chipsets,
3393 * and SMM handlers might indeed rely on 4G segment limits,
3394 * so do not report SMM to be available if real mode is
3395 * emulated via vm86 mode. Still, do not go to great lengths
3396 * to avoid userspace's usage of the feature, because it is a
3397 * fringe case that is not enabled except via specific settings
3398 * of the module parameters.
3399 */
3400 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3401 break;
3402 case KVM_CAP_VAPIC:
3403 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3404 break;
3405 case KVM_CAP_NR_VCPUS:
3406 r = KVM_SOFT_MAX_VCPUS;
3407 break;
3408 case KVM_CAP_MAX_VCPUS:
3409 r = KVM_MAX_VCPUS;
3410 break;
3411 case KVM_CAP_MAX_VCPU_ID:
3412 r = KVM_MAX_VCPU_ID;
3413 break;
3414 case KVM_CAP_PV_MMU: /* obsolete */
3415 r = 0;
3416 break;
3417 case KVM_CAP_MCE:
3418 r = KVM_MAX_MCE_BANKS;
3419 break;
3420 case KVM_CAP_XCRS:
3421 r = boot_cpu_has(X86_FEATURE_XSAVE);
3422 break;
3423 case KVM_CAP_TSC_CONTROL:
3424 r = kvm_has_tsc_control;
3425 break;
3426 case KVM_CAP_X2APIC_API:
3427 r = KVM_X2APIC_API_VALID_FLAGS;
3428 break;
3429 case KVM_CAP_NESTED_STATE:
3430 r = kvm_x86_ops.get_nested_state ?
3431 kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0;
3432 break;
3433 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3434 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3435 break;
3436 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3437 r = kvm_x86_ops.nested_enable_evmcs != NULL;
3438 break;
3439 default:
3440 break;
3441 }
3442 return r;
3443
3444 }
3445
3446 long kvm_arch_dev_ioctl(struct file *filp,
3447 unsigned int ioctl, unsigned long arg)
3448 {
3449 void __user *argp = (void __user *)arg;
3450 long r;
3451
3452 switch (ioctl) {
3453 case KVM_GET_MSR_INDEX_LIST: {
3454 struct kvm_msr_list __user *user_msr_list = argp;
3455 struct kvm_msr_list msr_list;
3456 unsigned n;
3457
3458 r = -EFAULT;
3459 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3460 goto out;
3461 n = msr_list.nmsrs;
3462 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3463 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3464 goto out;
3465 r = -E2BIG;
3466 if (n < msr_list.nmsrs)
3467 goto out;
3468 r = -EFAULT;
3469 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3470 num_msrs_to_save * sizeof(u32)))
3471 goto out;
3472 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3473 &emulated_msrs,
3474 num_emulated_msrs * sizeof(u32)))
3475 goto out;
3476 r = 0;
3477 break;
3478 }
3479 case KVM_GET_SUPPORTED_CPUID:
3480 case KVM_GET_EMULATED_CPUID: {
3481 struct kvm_cpuid2 __user *cpuid_arg = argp;
3482 struct kvm_cpuid2 cpuid;
3483
3484 r = -EFAULT;
3485 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3486 goto out;
3487
3488 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3489 ioctl);
3490 if (r)
3491 goto out;
3492
3493 r = -EFAULT;
3494 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3495 goto out;
3496 r = 0;
3497 break;
3498 }
3499 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3500 r = -EFAULT;
3501 if (copy_to_user(argp, &kvm_mce_cap_supported,
3502 sizeof(kvm_mce_cap_supported)))
3503 goto out;
3504 r = 0;
3505 break;
3506 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3507 struct kvm_msr_list __user *user_msr_list = argp;
3508 struct kvm_msr_list msr_list;
3509 unsigned int n;
3510
3511 r = -EFAULT;
3512 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3513 goto out;
3514 n = msr_list.nmsrs;
3515 msr_list.nmsrs = num_msr_based_features;
3516 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3517 goto out;
3518 r = -E2BIG;
3519 if (n < msr_list.nmsrs)
3520 goto out;
3521 r = -EFAULT;
3522 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3523 num_msr_based_features * sizeof(u32)))
3524 goto out;
3525 r = 0;
3526 break;
3527 }
3528 case KVM_GET_MSRS:
3529 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3530 break;
3531 default:
3532 r = -EINVAL;
3533 break;
3534 }
3535 out:
3536 return r;
3537 }
3538
3539 static void wbinvd_ipi(void *garbage)
3540 {
3541 wbinvd();
3542 }
3543
3544 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3545 {
3546 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3547 }
3548
3549 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3550 {
3551 /* Address WBINVD may be executed by guest */
3552 if (need_emulate_wbinvd(vcpu)) {
3553 if (kvm_x86_ops.has_wbinvd_exit())
3554 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3555 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3556 smp_call_function_single(vcpu->cpu,
3557 wbinvd_ipi, NULL, 1);
3558 }
3559
3560 kvm_x86_ops.vcpu_load(vcpu, cpu);
3561
3562 /* Apply any externally detected TSC adjustments (due to suspend) */
3563 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3564 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3565 vcpu->arch.tsc_offset_adjustment = 0;
3566 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3567 }
3568
3569 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3570 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3571 rdtsc() - vcpu->arch.last_host_tsc;
3572 if (tsc_delta < 0)
3573 mark_tsc_unstable("KVM discovered backwards TSC");
3574
3575 if (kvm_check_tsc_unstable()) {
3576 u64 offset = kvm_compute_tsc_offset(vcpu,
3577 vcpu->arch.last_guest_tsc);
3578 kvm_vcpu_write_tsc_offset(vcpu, offset);
3579 vcpu->arch.tsc_catchup = 1;
3580 }
3581
3582 if (kvm_lapic_hv_timer_in_use(vcpu))
3583 kvm_lapic_restart_hv_timer(vcpu);
3584
3585 /*
3586 * On a host with synchronized TSC, there is no need to update
3587 * kvmclock on vcpu->cpu migration
3588 */
3589 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3590 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3591 if (vcpu->cpu != cpu)
3592 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3593 vcpu->cpu = cpu;
3594 }
3595
3596 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3597 }
3598
3599 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3600 {
3601 struct kvm_host_map map;
3602 struct kvm_steal_time *st;
3603
3604 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3605 return;
3606
3607 if (vcpu->arch.st.preempted)
3608 return;
3609
3610 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3611 &vcpu->arch.st.cache, true))
3612 return;
3613
3614 st = map.hva +
3615 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3616
3617 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3618
3619 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3620 }
3621
3622 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3623 {
3624 int idx;
3625
3626 if (vcpu->preempted)
3627 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3628
3629 /*
3630 * Disable page faults because we're in atomic context here.
3631 * kvm_write_guest_offset_cached() would call might_fault()
3632 * that relies on pagefault_disable() to tell if there's a
3633 * bug. NOTE: the write to guest memory may not go through if
3634 * during postcopy live migration or if there's heavy guest
3635 * paging.
3636 */
3637 pagefault_disable();
3638 /*
3639 * kvm_memslots() will be called by
3640 * kvm_write_guest_offset_cached() so take the srcu lock.
3641 */
3642 idx = srcu_read_lock(&vcpu->kvm->srcu);
3643 kvm_steal_time_set_preempted(vcpu);
3644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3645 pagefault_enable();
3646 kvm_x86_ops.vcpu_put(vcpu);
3647 vcpu->arch.last_host_tsc = rdtsc();
3648 /*
3649 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3650 * on every vmexit, but if not, we might have a stale dr6 from the
3651 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3652 */
3653 set_debugreg(0, 6);
3654 }
3655
3656 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3657 struct kvm_lapic_state *s)
3658 {
3659 if (vcpu->arch.apicv_active)
3660 kvm_x86_ops.sync_pir_to_irr(vcpu);
3661
3662 return kvm_apic_get_state(vcpu, s);
3663 }
3664
3665 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3666 struct kvm_lapic_state *s)
3667 {
3668 int r;
3669
3670 r = kvm_apic_set_state(vcpu, s);
3671 if (r)
3672 return r;
3673 update_cr8_intercept(vcpu);
3674
3675 return 0;
3676 }
3677
3678 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3679 {
3680 return (!lapic_in_kernel(vcpu) ||
3681 kvm_apic_accept_pic_intr(vcpu));
3682 }
3683
3684 /*
3685 * if userspace requested an interrupt window, check that the
3686 * interrupt window is open.
3687 *
3688 * No need to exit to userspace if we already have an interrupt queued.
3689 */
3690 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3691 {
3692 return kvm_arch_interrupt_allowed(vcpu) &&
3693 !kvm_cpu_has_interrupt(vcpu) &&
3694 !kvm_event_needs_reinjection(vcpu) &&
3695 kvm_cpu_accept_dm_intr(vcpu);
3696 }
3697
3698 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3699 struct kvm_interrupt *irq)
3700 {
3701 if (irq->irq >= KVM_NR_INTERRUPTS)
3702 return -EINVAL;
3703
3704 if (!irqchip_in_kernel(vcpu->kvm)) {
3705 kvm_queue_interrupt(vcpu, irq->irq, false);
3706 kvm_make_request(KVM_REQ_EVENT, vcpu);
3707 return 0;
3708 }
3709
3710 /*
3711 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3712 * fail for in-kernel 8259.
3713 */
3714 if (pic_in_kernel(vcpu->kvm))
3715 return -ENXIO;
3716
3717 if (vcpu->arch.pending_external_vector != -1)
3718 return -EEXIST;
3719
3720 vcpu->arch.pending_external_vector = irq->irq;
3721 kvm_make_request(KVM_REQ_EVENT, vcpu);
3722 return 0;
3723 }
3724
3725 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3726 {
3727 kvm_inject_nmi(vcpu);
3728
3729 return 0;
3730 }
3731
3732 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3733 {
3734 kvm_make_request(KVM_REQ_SMI, vcpu);
3735
3736 return 0;
3737 }
3738
3739 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3740 struct kvm_tpr_access_ctl *tac)
3741 {
3742 if (tac->flags)
3743 return -EINVAL;
3744 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3745 return 0;
3746 }
3747
3748 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3749 u64 mcg_cap)
3750 {
3751 int r;
3752 unsigned bank_num = mcg_cap & 0xff, bank;
3753
3754 r = -EINVAL;
3755 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3756 goto out;
3757 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3758 goto out;
3759 r = 0;
3760 vcpu->arch.mcg_cap = mcg_cap;
3761 /* Init IA32_MCG_CTL to all 1s */
3762 if (mcg_cap & MCG_CTL_P)
3763 vcpu->arch.mcg_ctl = ~(u64)0;
3764 /* Init IA32_MCi_CTL to all 1s */
3765 for (bank = 0; bank < bank_num; bank++)
3766 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3767
3768 kvm_x86_ops.setup_mce(vcpu);
3769 out:
3770 return r;
3771 }
3772
3773 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3774 struct kvm_x86_mce *mce)
3775 {
3776 u64 mcg_cap = vcpu->arch.mcg_cap;
3777 unsigned bank_num = mcg_cap & 0xff;
3778 u64 *banks = vcpu->arch.mce_banks;
3779
3780 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3781 return -EINVAL;
3782 /*
3783 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3784 * reporting is disabled
3785 */
3786 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3787 vcpu->arch.mcg_ctl != ~(u64)0)
3788 return 0;
3789 banks += 4 * mce->bank;
3790 /*
3791 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3792 * reporting is disabled for the bank
3793 */
3794 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3795 return 0;
3796 if (mce->status & MCI_STATUS_UC) {
3797 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3798 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3799 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3800 return 0;
3801 }
3802 if (banks[1] & MCI_STATUS_VAL)
3803 mce->status |= MCI_STATUS_OVER;
3804 banks[2] = mce->addr;
3805 banks[3] = mce->misc;
3806 vcpu->arch.mcg_status = mce->mcg_status;
3807 banks[1] = mce->status;
3808 kvm_queue_exception(vcpu, MC_VECTOR);
3809 } else if (!(banks[1] & MCI_STATUS_VAL)
3810 || !(banks[1] & MCI_STATUS_UC)) {
3811 if (banks[1] & MCI_STATUS_VAL)
3812 mce->status |= MCI_STATUS_OVER;
3813 banks[2] = mce->addr;
3814 banks[3] = mce->misc;
3815 banks[1] = mce->status;
3816 } else
3817 banks[1] |= MCI_STATUS_OVER;
3818 return 0;
3819 }
3820
3821 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3822 struct kvm_vcpu_events *events)
3823 {
3824 process_nmi(vcpu);
3825
3826 /*
3827 * In guest mode, payload delivery should be deferred,
3828 * so that the L1 hypervisor can intercept #PF before
3829 * CR2 is modified (or intercept #DB before DR6 is
3830 * modified under nVMX). Unless the per-VM capability,
3831 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3832 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3833 * opportunistically defer the exception payload, deliver it if the
3834 * capability hasn't been requested before processing a
3835 * KVM_GET_VCPU_EVENTS.
3836 */
3837 if (!vcpu->kvm->arch.exception_payload_enabled &&
3838 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3839 kvm_deliver_exception_payload(vcpu);
3840
3841 /*
3842 * The API doesn't provide the instruction length for software
3843 * exceptions, so don't report them. As long as the guest RIP
3844 * isn't advanced, we should expect to encounter the exception
3845 * again.
3846 */
3847 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3848 events->exception.injected = 0;
3849 events->exception.pending = 0;
3850 } else {
3851 events->exception.injected = vcpu->arch.exception.injected;
3852 events->exception.pending = vcpu->arch.exception.pending;
3853 /*
3854 * For ABI compatibility, deliberately conflate
3855 * pending and injected exceptions when
3856 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3857 */
3858 if (!vcpu->kvm->arch.exception_payload_enabled)
3859 events->exception.injected |=
3860 vcpu->arch.exception.pending;
3861 }
3862 events->exception.nr = vcpu->arch.exception.nr;
3863 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3864 events->exception.error_code = vcpu->arch.exception.error_code;
3865 events->exception_has_payload = vcpu->arch.exception.has_payload;
3866 events->exception_payload = vcpu->arch.exception.payload;
3867
3868 events->interrupt.injected =
3869 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3870 events->interrupt.nr = vcpu->arch.interrupt.nr;
3871 events->interrupt.soft = 0;
3872 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3873
3874 events->nmi.injected = vcpu->arch.nmi_injected;
3875 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3876 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3877 events->nmi.pad = 0;
3878
3879 events->sipi_vector = 0; /* never valid when reporting to user space */
3880
3881 events->smi.smm = is_smm(vcpu);
3882 events->smi.pending = vcpu->arch.smi_pending;
3883 events->smi.smm_inside_nmi =
3884 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3885 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3886
3887 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3888 | KVM_VCPUEVENT_VALID_SHADOW
3889 | KVM_VCPUEVENT_VALID_SMM);
3890 if (vcpu->kvm->arch.exception_payload_enabled)
3891 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3892
3893 memset(&events->reserved, 0, sizeof(events->reserved));
3894 }
3895
3896 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3897
3898 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3899 struct kvm_vcpu_events *events)
3900 {
3901 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3902 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3903 | KVM_VCPUEVENT_VALID_SHADOW
3904 | KVM_VCPUEVENT_VALID_SMM
3905 | KVM_VCPUEVENT_VALID_PAYLOAD))
3906 return -EINVAL;
3907
3908 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3909 if (!vcpu->kvm->arch.exception_payload_enabled)
3910 return -EINVAL;
3911 if (events->exception.pending)
3912 events->exception.injected = 0;
3913 else
3914 events->exception_has_payload = 0;
3915 } else {
3916 events->exception.pending = 0;
3917 events->exception_has_payload = 0;
3918 }
3919
3920 if ((events->exception.injected || events->exception.pending) &&
3921 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3922 return -EINVAL;
3923
3924 /* INITs are latched while in SMM */
3925 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3926 (events->smi.smm || events->smi.pending) &&
3927 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3928 return -EINVAL;
3929
3930 process_nmi(vcpu);
3931 vcpu->arch.exception.injected = events->exception.injected;
3932 vcpu->arch.exception.pending = events->exception.pending;
3933 vcpu->arch.exception.nr = events->exception.nr;
3934 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3935 vcpu->arch.exception.error_code = events->exception.error_code;
3936 vcpu->arch.exception.has_payload = events->exception_has_payload;
3937 vcpu->arch.exception.payload = events->exception_payload;
3938
3939 vcpu->arch.interrupt.injected = events->interrupt.injected;
3940 vcpu->arch.interrupt.nr = events->interrupt.nr;
3941 vcpu->arch.interrupt.soft = events->interrupt.soft;
3942 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3943 kvm_x86_ops.set_interrupt_shadow(vcpu,
3944 events->interrupt.shadow);
3945
3946 vcpu->arch.nmi_injected = events->nmi.injected;
3947 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3948 vcpu->arch.nmi_pending = events->nmi.pending;
3949 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
3950
3951 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3952 lapic_in_kernel(vcpu))
3953 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3954
3955 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3956 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3957 if (events->smi.smm)
3958 vcpu->arch.hflags |= HF_SMM_MASK;
3959 else
3960 vcpu->arch.hflags &= ~HF_SMM_MASK;
3961 kvm_smm_changed(vcpu);
3962 }
3963
3964 vcpu->arch.smi_pending = events->smi.pending;
3965
3966 if (events->smi.smm) {
3967 if (events->smi.smm_inside_nmi)
3968 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3969 else
3970 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3971 }
3972
3973 if (lapic_in_kernel(vcpu)) {
3974 if (events->smi.latched_init)
3975 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3976 else
3977 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3978 }
3979 }
3980
3981 kvm_make_request(KVM_REQ_EVENT, vcpu);
3982
3983 return 0;
3984 }
3985
3986 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3987 struct kvm_debugregs *dbgregs)
3988 {
3989 unsigned long val;
3990
3991 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3992 kvm_get_dr(vcpu, 6, &val);
3993 dbgregs->dr6 = val;
3994 dbgregs->dr7 = vcpu->arch.dr7;
3995 dbgregs->flags = 0;
3996 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3997 }
3998
3999 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4000 struct kvm_debugregs *dbgregs)
4001 {
4002 if (dbgregs->flags)
4003 return -EINVAL;
4004
4005 if (dbgregs->dr6 & ~0xffffffffull)
4006 return -EINVAL;
4007 if (dbgregs->dr7 & ~0xffffffffull)
4008 return -EINVAL;
4009
4010 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4011 kvm_update_dr0123(vcpu);
4012 vcpu->arch.dr6 = dbgregs->dr6;
4013 kvm_update_dr6(vcpu);
4014 vcpu->arch.dr7 = dbgregs->dr7;
4015 kvm_update_dr7(vcpu);
4016
4017 return 0;
4018 }
4019
4020 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4021
4022 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4023 {
4024 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4025 u64 xstate_bv = xsave->header.xfeatures;
4026 u64 valid;
4027
4028 /*
4029 * Copy legacy XSAVE area, to avoid complications with CPUID
4030 * leaves 0 and 1 in the loop below.
4031 */
4032 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4033
4034 /* Set XSTATE_BV */
4035 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4036 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4037
4038 /*
4039 * Copy each region from the possibly compacted offset to the
4040 * non-compacted offset.
4041 */
4042 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4043 while (valid) {
4044 u64 xfeature_mask = valid & -valid;
4045 int xfeature_nr = fls64(xfeature_mask) - 1;
4046 void *src = get_xsave_addr(xsave, xfeature_nr);
4047
4048 if (src) {
4049 u32 size, offset, ecx, edx;
4050 cpuid_count(XSTATE_CPUID, xfeature_nr,
4051 &size, &offset, &ecx, &edx);
4052 if (xfeature_nr == XFEATURE_PKRU)
4053 memcpy(dest + offset, &vcpu->arch.pkru,
4054 sizeof(vcpu->arch.pkru));
4055 else
4056 memcpy(dest + offset, src, size);
4057
4058 }
4059
4060 valid -= xfeature_mask;
4061 }
4062 }
4063
4064 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4065 {
4066 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4067 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4068 u64 valid;
4069
4070 /*
4071 * Copy legacy XSAVE area, to avoid complications with CPUID
4072 * leaves 0 and 1 in the loop below.
4073 */
4074 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4075
4076 /* Set XSTATE_BV and possibly XCOMP_BV. */
4077 xsave->header.xfeatures = xstate_bv;
4078 if (boot_cpu_has(X86_FEATURE_XSAVES))
4079 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4080
4081 /*
4082 * Copy each region from the non-compacted offset to the
4083 * possibly compacted offset.
4084 */
4085 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4086 while (valid) {
4087 u64 xfeature_mask = valid & -valid;
4088 int xfeature_nr = fls64(xfeature_mask) - 1;
4089 void *dest = get_xsave_addr(xsave, xfeature_nr);
4090
4091 if (dest) {
4092 u32 size, offset, ecx, edx;
4093 cpuid_count(XSTATE_CPUID, xfeature_nr,
4094 &size, &offset, &ecx, &edx);
4095 if (xfeature_nr == XFEATURE_PKRU)
4096 memcpy(&vcpu->arch.pkru, src + offset,
4097 sizeof(vcpu->arch.pkru));
4098 else
4099 memcpy(dest, src + offset, size);
4100 }
4101
4102 valid -= xfeature_mask;
4103 }
4104 }
4105
4106 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4107 struct kvm_xsave *guest_xsave)
4108 {
4109 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4110 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4111 fill_xsave((u8 *) guest_xsave->region, vcpu);
4112 } else {
4113 memcpy(guest_xsave->region,
4114 &vcpu->arch.guest_fpu->state.fxsave,
4115 sizeof(struct fxregs_state));
4116 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4117 XFEATURE_MASK_FPSSE;
4118 }
4119 }
4120
4121 #define XSAVE_MXCSR_OFFSET 24
4122
4123 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4124 struct kvm_xsave *guest_xsave)
4125 {
4126 u64 xstate_bv =
4127 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4128 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4129
4130 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4131 /*
4132 * Here we allow setting states that are not present in
4133 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4134 * with old userspace.
4135 */
4136 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4137 return -EINVAL;
4138 load_xsave(vcpu, (u8 *)guest_xsave->region);
4139 } else {
4140 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4141 mxcsr & ~mxcsr_feature_mask)
4142 return -EINVAL;
4143 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4144 guest_xsave->region, sizeof(struct fxregs_state));
4145 }
4146 return 0;
4147 }
4148
4149 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4150 struct kvm_xcrs *guest_xcrs)
4151 {
4152 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4153 guest_xcrs->nr_xcrs = 0;
4154 return;
4155 }
4156
4157 guest_xcrs->nr_xcrs = 1;
4158 guest_xcrs->flags = 0;
4159 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4160 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4161 }
4162
4163 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4164 struct kvm_xcrs *guest_xcrs)
4165 {
4166 int i, r = 0;
4167
4168 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4169 return -EINVAL;
4170
4171 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4172 return -EINVAL;
4173
4174 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4175 /* Only support XCR0 currently */
4176 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4177 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4178 guest_xcrs->xcrs[i].value);
4179 break;
4180 }
4181 if (r)
4182 r = -EINVAL;
4183 return r;
4184 }
4185
4186 /*
4187 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4188 * stopped by the hypervisor. This function will be called from the host only.
4189 * EINVAL is returned when the host attempts to set the flag for a guest that
4190 * does not support pv clocks.
4191 */
4192 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4193 {
4194 if (!vcpu->arch.pv_time_enabled)
4195 return -EINVAL;
4196 vcpu->arch.pvclock_set_guest_stopped_request = true;
4197 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4198 return 0;
4199 }
4200
4201 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4202 struct kvm_enable_cap *cap)
4203 {
4204 int r;
4205 uint16_t vmcs_version;
4206 void __user *user_ptr;
4207
4208 if (cap->flags)
4209 return -EINVAL;
4210
4211 switch (cap->cap) {
4212 case KVM_CAP_HYPERV_SYNIC2:
4213 if (cap->args[0])
4214 return -EINVAL;
4215 /* fall through */
4216
4217 case KVM_CAP_HYPERV_SYNIC:
4218 if (!irqchip_in_kernel(vcpu->kvm))
4219 return -EINVAL;
4220 return kvm_hv_activate_synic(vcpu, cap->cap ==
4221 KVM_CAP_HYPERV_SYNIC2);
4222 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4223 if (!kvm_x86_ops.nested_enable_evmcs)
4224 return -ENOTTY;
4225 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version);
4226 if (!r) {
4227 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4228 if (copy_to_user(user_ptr, &vmcs_version,
4229 sizeof(vmcs_version)))
4230 r = -EFAULT;
4231 }
4232 return r;
4233 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4234 if (!kvm_x86_ops.enable_direct_tlbflush)
4235 return -ENOTTY;
4236
4237 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4238
4239 default:
4240 return -EINVAL;
4241 }
4242 }
4243
4244 long kvm_arch_vcpu_ioctl(struct file *filp,
4245 unsigned int ioctl, unsigned long arg)
4246 {
4247 struct kvm_vcpu *vcpu = filp->private_data;
4248 void __user *argp = (void __user *)arg;
4249 int r;
4250 union {
4251 struct kvm_lapic_state *lapic;
4252 struct kvm_xsave *xsave;
4253 struct kvm_xcrs *xcrs;
4254 void *buffer;
4255 } u;
4256
4257 vcpu_load(vcpu);
4258
4259 u.buffer = NULL;
4260 switch (ioctl) {
4261 case KVM_GET_LAPIC: {
4262 r = -EINVAL;
4263 if (!lapic_in_kernel(vcpu))
4264 goto out;
4265 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4266 GFP_KERNEL_ACCOUNT);
4267
4268 r = -ENOMEM;
4269 if (!u.lapic)
4270 goto out;
4271 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4272 if (r)
4273 goto out;
4274 r = -EFAULT;
4275 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4276 goto out;
4277 r = 0;
4278 break;
4279 }
4280 case KVM_SET_LAPIC: {
4281 r = -EINVAL;
4282 if (!lapic_in_kernel(vcpu))
4283 goto out;
4284 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4285 if (IS_ERR(u.lapic)) {
4286 r = PTR_ERR(u.lapic);
4287 goto out_nofree;
4288 }
4289
4290 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4291 break;
4292 }
4293 case KVM_INTERRUPT: {
4294 struct kvm_interrupt irq;
4295
4296 r = -EFAULT;
4297 if (copy_from_user(&irq, argp, sizeof(irq)))
4298 goto out;
4299 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4300 break;
4301 }
4302 case KVM_NMI: {
4303 r = kvm_vcpu_ioctl_nmi(vcpu);
4304 break;
4305 }
4306 case KVM_SMI: {
4307 r = kvm_vcpu_ioctl_smi(vcpu);
4308 break;
4309 }
4310 case KVM_SET_CPUID: {
4311 struct kvm_cpuid __user *cpuid_arg = argp;
4312 struct kvm_cpuid cpuid;
4313
4314 r = -EFAULT;
4315 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4316 goto out;
4317 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4318 break;
4319 }
4320 case KVM_SET_CPUID2: {
4321 struct kvm_cpuid2 __user *cpuid_arg = argp;
4322 struct kvm_cpuid2 cpuid;
4323
4324 r = -EFAULT;
4325 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4326 goto out;
4327 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4328 cpuid_arg->entries);
4329 break;
4330 }
4331 case KVM_GET_CPUID2: {
4332 struct kvm_cpuid2 __user *cpuid_arg = argp;
4333 struct kvm_cpuid2 cpuid;
4334
4335 r = -EFAULT;
4336 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4337 goto out;
4338 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4339 cpuid_arg->entries);
4340 if (r)
4341 goto out;
4342 r = -EFAULT;
4343 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4344 goto out;
4345 r = 0;
4346 break;
4347 }
4348 case KVM_GET_MSRS: {
4349 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4350 r = msr_io(vcpu, argp, do_get_msr, 1);
4351 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4352 break;
4353 }
4354 case KVM_SET_MSRS: {
4355 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4356 r = msr_io(vcpu, argp, do_set_msr, 0);
4357 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4358 break;
4359 }
4360 case KVM_TPR_ACCESS_REPORTING: {
4361 struct kvm_tpr_access_ctl tac;
4362
4363 r = -EFAULT;
4364 if (copy_from_user(&tac, argp, sizeof(tac)))
4365 goto out;
4366 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4367 if (r)
4368 goto out;
4369 r = -EFAULT;
4370 if (copy_to_user(argp, &tac, sizeof(tac)))
4371 goto out;
4372 r = 0;
4373 break;
4374 };
4375 case KVM_SET_VAPIC_ADDR: {
4376 struct kvm_vapic_addr va;
4377 int idx;
4378
4379 r = -EINVAL;
4380 if (!lapic_in_kernel(vcpu))
4381 goto out;
4382 r = -EFAULT;
4383 if (copy_from_user(&va, argp, sizeof(va)))
4384 goto out;
4385 idx = srcu_read_lock(&vcpu->kvm->srcu);
4386 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4387 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4388 break;
4389 }
4390 case KVM_X86_SETUP_MCE: {
4391 u64 mcg_cap;
4392
4393 r = -EFAULT;
4394 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4395 goto out;
4396 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4397 break;
4398 }
4399 case KVM_X86_SET_MCE: {
4400 struct kvm_x86_mce mce;
4401
4402 r = -EFAULT;
4403 if (copy_from_user(&mce, argp, sizeof(mce)))
4404 goto out;
4405 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4406 break;
4407 }
4408 case KVM_GET_VCPU_EVENTS: {
4409 struct kvm_vcpu_events events;
4410
4411 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4412
4413 r = -EFAULT;
4414 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4415 break;
4416 r = 0;
4417 break;
4418 }
4419 case KVM_SET_VCPU_EVENTS: {
4420 struct kvm_vcpu_events events;
4421
4422 r = -EFAULT;
4423 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4424 break;
4425
4426 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4427 break;
4428 }
4429 case KVM_GET_DEBUGREGS: {
4430 struct kvm_debugregs dbgregs;
4431
4432 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4433
4434 r = -EFAULT;
4435 if (copy_to_user(argp, &dbgregs,
4436 sizeof(struct kvm_debugregs)))
4437 break;
4438 r = 0;
4439 break;
4440 }
4441 case KVM_SET_DEBUGREGS: {
4442 struct kvm_debugregs dbgregs;
4443
4444 r = -EFAULT;
4445 if (copy_from_user(&dbgregs, argp,
4446 sizeof(struct kvm_debugregs)))
4447 break;
4448
4449 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4450 break;
4451 }
4452 case KVM_GET_XSAVE: {
4453 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4454 r = -ENOMEM;
4455 if (!u.xsave)
4456 break;
4457
4458 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4459
4460 r = -EFAULT;
4461 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4462 break;
4463 r = 0;
4464 break;
4465 }
4466 case KVM_SET_XSAVE: {
4467 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4468 if (IS_ERR(u.xsave)) {
4469 r = PTR_ERR(u.xsave);
4470 goto out_nofree;
4471 }
4472
4473 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4474 break;
4475 }
4476 case KVM_GET_XCRS: {
4477 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4478 r = -ENOMEM;
4479 if (!u.xcrs)
4480 break;
4481
4482 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4483
4484 r = -EFAULT;
4485 if (copy_to_user(argp, u.xcrs,
4486 sizeof(struct kvm_xcrs)))
4487 break;
4488 r = 0;
4489 break;
4490 }
4491 case KVM_SET_XCRS: {
4492 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4493 if (IS_ERR(u.xcrs)) {
4494 r = PTR_ERR(u.xcrs);
4495 goto out_nofree;
4496 }
4497
4498 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4499 break;
4500 }
4501 case KVM_SET_TSC_KHZ: {
4502 u32 user_tsc_khz;
4503
4504 r = -EINVAL;
4505 user_tsc_khz = (u32)arg;
4506
4507 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4508 goto out;
4509
4510 if (user_tsc_khz == 0)
4511 user_tsc_khz = tsc_khz;
4512
4513 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4514 r = 0;
4515
4516 goto out;
4517 }
4518 case KVM_GET_TSC_KHZ: {
4519 r = vcpu->arch.virtual_tsc_khz;
4520 goto out;
4521 }
4522 case KVM_KVMCLOCK_CTRL: {
4523 r = kvm_set_guest_paused(vcpu);
4524 goto out;
4525 }
4526 case KVM_ENABLE_CAP: {
4527 struct kvm_enable_cap cap;
4528
4529 r = -EFAULT;
4530 if (copy_from_user(&cap, argp, sizeof(cap)))
4531 goto out;
4532 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4533 break;
4534 }
4535 case KVM_GET_NESTED_STATE: {
4536 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4537 u32 user_data_size;
4538
4539 r = -EINVAL;
4540 if (!kvm_x86_ops.get_nested_state)
4541 break;
4542
4543 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4544 r = -EFAULT;
4545 if (get_user(user_data_size, &user_kvm_nested_state->size))
4546 break;
4547
4548 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state,
4549 user_data_size);
4550 if (r < 0)
4551 break;
4552
4553 if (r > user_data_size) {
4554 if (put_user(r, &user_kvm_nested_state->size))
4555 r = -EFAULT;
4556 else
4557 r = -E2BIG;
4558 break;
4559 }
4560
4561 r = 0;
4562 break;
4563 }
4564 case KVM_SET_NESTED_STATE: {
4565 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4566 struct kvm_nested_state kvm_state;
4567 int idx;
4568
4569 r = -EINVAL;
4570 if (!kvm_x86_ops.set_nested_state)
4571 break;
4572
4573 r = -EFAULT;
4574 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4575 break;
4576
4577 r = -EINVAL;
4578 if (kvm_state.size < sizeof(kvm_state))
4579 break;
4580
4581 if (kvm_state.flags &
4582 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4583 | KVM_STATE_NESTED_EVMCS))
4584 break;
4585
4586 /* nested_run_pending implies guest_mode. */
4587 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4588 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4589 break;
4590
4591 idx = srcu_read_lock(&vcpu->kvm->srcu);
4592 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4593 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4594 break;
4595 }
4596 case KVM_GET_SUPPORTED_HV_CPUID: {
4597 struct kvm_cpuid2 __user *cpuid_arg = argp;
4598 struct kvm_cpuid2 cpuid;
4599
4600 r = -EFAULT;
4601 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4602 goto out;
4603
4604 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4605 cpuid_arg->entries);
4606 if (r)
4607 goto out;
4608
4609 r = -EFAULT;
4610 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4611 goto out;
4612 r = 0;
4613 break;
4614 }
4615 default:
4616 r = -EINVAL;
4617 }
4618 out:
4619 kfree(u.buffer);
4620 out_nofree:
4621 vcpu_put(vcpu);
4622 return r;
4623 }
4624
4625 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4626 {
4627 return VM_FAULT_SIGBUS;
4628 }
4629
4630 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4631 {
4632 int ret;
4633
4634 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4635 return -EINVAL;
4636 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4637 return ret;
4638 }
4639
4640 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4641 u64 ident_addr)
4642 {
4643 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4644 }
4645
4646 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4647 unsigned long kvm_nr_mmu_pages)
4648 {
4649 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4650 return -EINVAL;
4651
4652 mutex_lock(&kvm->slots_lock);
4653
4654 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4655 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4656
4657 mutex_unlock(&kvm->slots_lock);
4658 return 0;
4659 }
4660
4661 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4662 {
4663 return kvm->arch.n_max_mmu_pages;
4664 }
4665
4666 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4667 {
4668 struct kvm_pic *pic = kvm->arch.vpic;
4669 int r;
4670
4671 r = 0;
4672 switch (chip->chip_id) {
4673 case KVM_IRQCHIP_PIC_MASTER:
4674 memcpy(&chip->chip.pic, &pic->pics[0],
4675 sizeof(struct kvm_pic_state));
4676 break;
4677 case KVM_IRQCHIP_PIC_SLAVE:
4678 memcpy(&chip->chip.pic, &pic->pics[1],
4679 sizeof(struct kvm_pic_state));
4680 break;
4681 case KVM_IRQCHIP_IOAPIC:
4682 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4683 break;
4684 default:
4685 r = -EINVAL;
4686 break;
4687 }
4688 return r;
4689 }
4690
4691 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4692 {
4693 struct kvm_pic *pic = kvm->arch.vpic;
4694 int r;
4695
4696 r = 0;
4697 switch (chip->chip_id) {
4698 case KVM_IRQCHIP_PIC_MASTER:
4699 spin_lock(&pic->lock);
4700 memcpy(&pic->pics[0], &chip->chip.pic,
4701 sizeof(struct kvm_pic_state));
4702 spin_unlock(&pic->lock);
4703 break;
4704 case KVM_IRQCHIP_PIC_SLAVE:
4705 spin_lock(&pic->lock);
4706 memcpy(&pic->pics[1], &chip->chip.pic,
4707 sizeof(struct kvm_pic_state));
4708 spin_unlock(&pic->lock);
4709 break;
4710 case KVM_IRQCHIP_IOAPIC:
4711 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4712 break;
4713 default:
4714 r = -EINVAL;
4715 break;
4716 }
4717 kvm_pic_update_irq(pic);
4718 return r;
4719 }
4720
4721 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4722 {
4723 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4724
4725 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4726
4727 mutex_lock(&kps->lock);
4728 memcpy(ps, &kps->channels, sizeof(*ps));
4729 mutex_unlock(&kps->lock);
4730 return 0;
4731 }
4732
4733 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4734 {
4735 int i;
4736 struct kvm_pit *pit = kvm->arch.vpit;
4737
4738 mutex_lock(&pit->pit_state.lock);
4739 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4740 for (i = 0; i < 3; i++)
4741 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4742 mutex_unlock(&pit->pit_state.lock);
4743 return 0;
4744 }
4745
4746 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4747 {
4748 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4749 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4750 sizeof(ps->channels));
4751 ps->flags = kvm->arch.vpit->pit_state.flags;
4752 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4753 memset(&ps->reserved, 0, sizeof(ps->reserved));
4754 return 0;
4755 }
4756
4757 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4758 {
4759 int start = 0;
4760 int i;
4761 u32 prev_legacy, cur_legacy;
4762 struct kvm_pit *pit = kvm->arch.vpit;
4763
4764 mutex_lock(&pit->pit_state.lock);
4765 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4766 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4767 if (!prev_legacy && cur_legacy)
4768 start = 1;
4769 memcpy(&pit->pit_state.channels, &ps->channels,
4770 sizeof(pit->pit_state.channels));
4771 pit->pit_state.flags = ps->flags;
4772 for (i = 0; i < 3; i++)
4773 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4774 start && i == 0);
4775 mutex_unlock(&pit->pit_state.lock);
4776 return 0;
4777 }
4778
4779 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4780 struct kvm_reinject_control *control)
4781 {
4782 struct kvm_pit *pit = kvm->arch.vpit;
4783
4784 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4785 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4786 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4787 */
4788 mutex_lock(&pit->pit_state.lock);
4789 kvm_pit_set_reinject(pit, control->pit_reinject);
4790 mutex_unlock(&pit->pit_state.lock);
4791
4792 return 0;
4793 }
4794
4795 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4796 {
4797 /*
4798 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4799 */
4800 if (kvm_x86_ops.flush_log_dirty)
4801 kvm_x86_ops.flush_log_dirty(kvm);
4802 }
4803
4804 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4805 bool line_status)
4806 {
4807 if (!irqchip_in_kernel(kvm))
4808 return -ENXIO;
4809
4810 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4811 irq_event->irq, irq_event->level,
4812 line_status);
4813 return 0;
4814 }
4815
4816 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4817 struct kvm_enable_cap *cap)
4818 {
4819 int r;
4820
4821 if (cap->flags)
4822 return -EINVAL;
4823
4824 switch (cap->cap) {
4825 case KVM_CAP_DISABLE_QUIRKS:
4826 kvm->arch.disabled_quirks = cap->args[0];
4827 r = 0;
4828 break;
4829 case KVM_CAP_SPLIT_IRQCHIP: {
4830 mutex_lock(&kvm->lock);
4831 r = -EINVAL;
4832 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4833 goto split_irqchip_unlock;
4834 r = -EEXIST;
4835 if (irqchip_in_kernel(kvm))
4836 goto split_irqchip_unlock;
4837 if (kvm->created_vcpus)
4838 goto split_irqchip_unlock;
4839 r = kvm_setup_empty_irq_routing(kvm);
4840 if (r)
4841 goto split_irqchip_unlock;
4842 /* Pairs with irqchip_in_kernel. */
4843 smp_wmb();
4844 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4845 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4846 r = 0;
4847 split_irqchip_unlock:
4848 mutex_unlock(&kvm->lock);
4849 break;
4850 }
4851 case KVM_CAP_X2APIC_API:
4852 r = -EINVAL;
4853 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4854 break;
4855
4856 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4857 kvm->arch.x2apic_format = true;
4858 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4859 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4860
4861 r = 0;
4862 break;
4863 case KVM_CAP_X86_DISABLE_EXITS:
4864 r = -EINVAL;
4865 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4866 break;
4867
4868 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4869 kvm_can_mwait_in_guest())
4870 kvm->arch.mwait_in_guest = true;
4871 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4872 kvm->arch.hlt_in_guest = true;
4873 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4874 kvm->arch.pause_in_guest = true;
4875 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4876 kvm->arch.cstate_in_guest = true;
4877 r = 0;
4878 break;
4879 case KVM_CAP_MSR_PLATFORM_INFO:
4880 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4881 r = 0;
4882 break;
4883 case KVM_CAP_EXCEPTION_PAYLOAD:
4884 kvm->arch.exception_payload_enabled = cap->args[0];
4885 r = 0;
4886 break;
4887 default:
4888 r = -EINVAL;
4889 break;
4890 }
4891 return r;
4892 }
4893
4894 long kvm_arch_vm_ioctl(struct file *filp,
4895 unsigned int ioctl, unsigned long arg)
4896 {
4897 struct kvm *kvm = filp->private_data;
4898 void __user *argp = (void __user *)arg;
4899 int r = -ENOTTY;
4900 /*
4901 * This union makes it completely explicit to gcc-3.x
4902 * that these two variables' stack usage should be
4903 * combined, not added together.
4904 */
4905 union {
4906 struct kvm_pit_state ps;
4907 struct kvm_pit_state2 ps2;
4908 struct kvm_pit_config pit_config;
4909 } u;
4910
4911 switch (ioctl) {
4912 case KVM_SET_TSS_ADDR:
4913 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4914 break;
4915 case KVM_SET_IDENTITY_MAP_ADDR: {
4916 u64 ident_addr;
4917
4918 mutex_lock(&kvm->lock);
4919 r = -EINVAL;
4920 if (kvm->created_vcpus)
4921 goto set_identity_unlock;
4922 r = -EFAULT;
4923 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4924 goto set_identity_unlock;
4925 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4926 set_identity_unlock:
4927 mutex_unlock(&kvm->lock);
4928 break;
4929 }
4930 case KVM_SET_NR_MMU_PAGES:
4931 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4932 break;
4933 case KVM_GET_NR_MMU_PAGES:
4934 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4935 break;
4936 case KVM_CREATE_IRQCHIP: {
4937 mutex_lock(&kvm->lock);
4938
4939 r = -EEXIST;
4940 if (irqchip_in_kernel(kvm))
4941 goto create_irqchip_unlock;
4942
4943 r = -EINVAL;
4944 if (kvm->created_vcpus)
4945 goto create_irqchip_unlock;
4946
4947 r = kvm_pic_init(kvm);
4948 if (r)
4949 goto create_irqchip_unlock;
4950
4951 r = kvm_ioapic_init(kvm);
4952 if (r) {
4953 kvm_pic_destroy(kvm);
4954 goto create_irqchip_unlock;
4955 }
4956
4957 r = kvm_setup_default_irq_routing(kvm);
4958 if (r) {
4959 kvm_ioapic_destroy(kvm);
4960 kvm_pic_destroy(kvm);
4961 goto create_irqchip_unlock;
4962 }
4963 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4964 smp_wmb();
4965 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4966 create_irqchip_unlock:
4967 mutex_unlock(&kvm->lock);
4968 break;
4969 }
4970 case KVM_CREATE_PIT:
4971 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4972 goto create_pit;
4973 case KVM_CREATE_PIT2:
4974 r = -EFAULT;
4975 if (copy_from_user(&u.pit_config, argp,
4976 sizeof(struct kvm_pit_config)))
4977 goto out;
4978 create_pit:
4979 mutex_lock(&kvm->lock);
4980 r = -EEXIST;
4981 if (kvm->arch.vpit)
4982 goto create_pit_unlock;
4983 r = -ENOMEM;
4984 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4985 if (kvm->arch.vpit)
4986 r = 0;
4987 create_pit_unlock:
4988 mutex_unlock(&kvm->lock);
4989 break;
4990 case KVM_GET_IRQCHIP: {
4991 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4992 struct kvm_irqchip *chip;
4993
4994 chip = memdup_user(argp, sizeof(*chip));
4995 if (IS_ERR(chip)) {
4996 r = PTR_ERR(chip);
4997 goto out;
4998 }
4999
5000 r = -ENXIO;
5001 if (!irqchip_kernel(kvm))
5002 goto get_irqchip_out;
5003 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5004 if (r)
5005 goto get_irqchip_out;
5006 r = -EFAULT;
5007 if (copy_to_user(argp, chip, sizeof(*chip)))
5008 goto get_irqchip_out;
5009 r = 0;
5010 get_irqchip_out:
5011 kfree(chip);
5012 break;
5013 }
5014 case KVM_SET_IRQCHIP: {
5015 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5016 struct kvm_irqchip *chip;
5017
5018 chip = memdup_user(argp, sizeof(*chip));
5019 if (IS_ERR(chip)) {
5020 r = PTR_ERR(chip);
5021 goto out;
5022 }
5023
5024 r = -ENXIO;
5025 if (!irqchip_kernel(kvm))
5026 goto set_irqchip_out;
5027 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5028 set_irqchip_out:
5029 kfree(chip);
5030 break;
5031 }
5032 case KVM_GET_PIT: {
5033 r = -EFAULT;
5034 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5035 goto out;
5036 r = -ENXIO;
5037 if (!kvm->arch.vpit)
5038 goto out;
5039 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5040 if (r)
5041 goto out;
5042 r = -EFAULT;
5043 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5044 goto out;
5045 r = 0;
5046 break;
5047 }
5048 case KVM_SET_PIT: {
5049 r = -EFAULT;
5050 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5051 goto out;
5052 r = -ENXIO;
5053 if (!kvm->arch.vpit)
5054 goto out;
5055 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5056 break;
5057 }
5058 case KVM_GET_PIT2: {
5059 r = -ENXIO;
5060 if (!kvm->arch.vpit)
5061 goto out;
5062 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5063 if (r)
5064 goto out;
5065 r = -EFAULT;
5066 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5067 goto out;
5068 r = 0;
5069 break;
5070 }
5071 case KVM_SET_PIT2: {
5072 r = -EFAULT;
5073 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5074 goto out;
5075 r = -ENXIO;
5076 if (!kvm->arch.vpit)
5077 goto out;
5078 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5079 break;
5080 }
5081 case KVM_REINJECT_CONTROL: {
5082 struct kvm_reinject_control control;
5083 r = -EFAULT;
5084 if (copy_from_user(&control, argp, sizeof(control)))
5085 goto out;
5086 r = -ENXIO;
5087 if (!kvm->arch.vpit)
5088 goto out;
5089 r = kvm_vm_ioctl_reinject(kvm, &control);
5090 break;
5091 }
5092 case KVM_SET_BOOT_CPU_ID:
5093 r = 0;
5094 mutex_lock(&kvm->lock);
5095 if (kvm->created_vcpus)
5096 r = -EBUSY;
5097 else
5098 kvm->arch.bsp_vcpu_id = arg;
5099 mutex_unlock(&kvm->lock);
5100 break;
5101 case KVM_XEN_HVM_CONFIG: {
5102 struct kvm_xen_hvm_config xhc;
5103 r = -EFAULT;
5104 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5105 goto out;
5106 r = -EINVAL;
5107 if (xhc.flags)
5108 goto out;
5109 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5110 r = 0;
5111 break;
5112 }
5113 case KVM_SET_CLOCK: {
5114 struct kvm_clock_data user_ns;
5115 u64 now_ns;
5116
5117 r = -EFAULT;
5118 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5119 goto out;
5120
5121 r = -EINVAL;
5122 if (user_ns.flags)
5123 goto out;
5124
5125 r = 0;
5126 /*
5127 * TODO: userspace has to take care of races with VCPU_RUN, so
5128 * kvm_gen_update_masterclock() can be cut down to locked
5129 * pvclock_update_vm_gtod_copy().
5130 */
5131 kvm_gen_update_masterclock(kvm);
5132 now_ns = get_kvmclock_ns(kvm);
5133 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5134 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5135 break;
5136 }
5137 case KVM_GET_CLOCK: {
5138 struct kvm_clock_data user_ns;
5139 u64 now_ns;
5140
5141 now_ns = get_kvmclock_ns(kvm);
5142 user_ns.clock = now_ns;
5143 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5144 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5145
5146 r = -EFAULT;
5147 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5148 goto out;
5149 r = 0;
5150 break;
5151 }
5152 case KVM_MEMORY_ENCRYPT_OP: {
5153 r = -ENOTTY;
5154 if (kvm_x86_ops.mem_enc_op)
5155 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5156 break;
5157 }
5158 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5159 struct kvm_enc_region region;
5160
5161 r = -EFAULT;
5162 if (copy_from_user(&region, argp, sizeof(region)))
5163 goto out;
5164
5165 r = -ENOTTY;
5166 if (kvm_x86_ops.mem_enc_reg_region)
5167 r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5168 break;
5169 }
5170 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5171 struct kvm_enc_region region;
5172
5173 r = -EFAULT;
5174 if (copy_from_user(&region, argp, sizeof(region)))
5175 goto out;
5176
5177 r = -ENOTTY;
5178 if (kvm_x86_ops.mem_enc_unreg_region)
5179 r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5180 break;
5181 }
5182 case KVM_HYPERV_EVENTFD: {
5183 struct kvm_hyperv_eventfd hvevfd;
5184
5185 r = -EFAULT;
5186 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5187 goto out;
5188 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5189 break;
5190 }
5191 case KVM_SET_PMU_EVENT_FILTER:
5192 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5193 break;
5194 default:
5195 r = -ENOTTY;
5196 }
5197 out:
5198 return r;
5199 }
5200
5201 static void kvm_init_msr_list(void)
5202 {
5203 struct x86_pmu_capability x86_pmu;
5204 u32 dummy[2];
5205 unsigned i;
5206
5207 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5208 "Please update the fixed PMCs in msrs_to_saved_all[]");
5209
5210 perf_get_x86_pmu_capability(&x86_pmu);
5211
5212 num_msrs_to_save = 0;
5213 num_emulated_msrs = 0;
5214 num_msr_based_features = 0;
5215
5216 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5217 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5218 continue;
5219
5220 /*
5221 * Even MSRs that are valid in the host may not be exposed
5222 * to the guests in some cases.
5223 */
5224 switch (msrs_to_save_all[i]) {
5225 case MSR_IA32_BNDCFGS:
5226 if (!kvm_mpx_supported())
5227 continue;
5228 break;
5229 case MSR_TSC_AUX:
5230 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5231 continue;
5232 break;
5233 case MSR_IA32_RTIT_CTL:
5234 case MSR_IA32_RTIT_STATUS:
5235 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5236 continue;
5237 break;
5238 case MSR_IA32_RTIT_CR3_MATCH:
5239 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5240 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5241 continue;
5242 break;
5243 case MSR_IA32_RTIT_OUTPUT_BASE:
5244 case MSR_IA32_RTIT_OUTPUT_MASK:
5245 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5246 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5247 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5248 continue;
5249 break;
5250 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5251 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5252 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5253 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5254 continue;
5255 break;
5256 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5257 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5258 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5259 continue;
5260 break;
5261 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5262 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5263 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5264 continue;
5265 }
5266 default:
5267 break;
5268 }
5269
5270 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5271 }
5272
5273 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5274 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5275 continue;
5276
5277 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5278 }
5279
5280 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5281 struct kvm_msr_entry msr;
5282
5283 msr.index = msr_based_features_all[i];
5284 if (kvm_get_msr_feature(&msr))
5285 continue;
5286
5287 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5288 }
5289 }
5290
5291 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5292 const void *v)
5293 {
5294 int handled = 0;
5295 int n;
5296
5297 do {
5298 n = min(len, 8);
5299 if (!(lapic_in_kernel(vcpu) &&
5300 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5301 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5302 break;
5303 handled += n;
5304 addr += n;
5305 len -= n;
5306 v += n;
5307 } while (len);
5308
5309 return handled;
5310 }
5311
5312 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5313 {
5314 int handled = 0;
5315 int n;
5316
5317 do {
5318 n = min(len, 8);
5319 if (!(lapic_in_kernel(vcpu) &&
5320 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5321 addr, n, v))
5322 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5323 break;
5324 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5325 handled += n;
5326 addr += n;
5327 len -= n;
5328 v += n;
5329 } while (len);
5330
5331 return handled;
5332 }
5333
5334 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5335 struct kvm_segment *var, int seg)
5336 {
5337 kvm_x86_ops.set_segment(vcpu, var, seg);
5338 }
5339
5340 void kvm_get_segment(struct kvm_vcpu *vcpu,
5341 struct kvm_segment *var, int seg)
5342 {
5343 kvm_x86_ops.get_segment(vcpu, var, seg);
5344 }
5345
5346 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5347 struct x86_exception *exception)
5348 {
5349 gpa_t t_gpa;
5350
5351 BUG_ON(!mmu_is_nested(vcpu));
5352
5353 /* NPT walks are always user-walks */
5354 access |= PFERR_USER_MASK;
5355 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5356
5357 return t_gpa;
5358 }
5359
5360 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5361 struct x86_exception *exception)
5362 {
5363 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5364 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5365 }
5366
5367 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5368 struct x86_exception *exception)
5369 {
5370 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5371 access |= PFERR_FETCH_MASK;
5372 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5373 }
5374
5375 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5376 struct x86_exception *exception)
5377 {
5378 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5379 access |= PFERR_WRITE_MASK;
5380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5381 }
5382
5383 /* uses this to access any guest's mapped memory without checking CPL */
5384 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5385 struct x86_exception *exception)
5386 {
5387 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5388 }
5389
5390 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5391 struct kvm_vcpu *vcpu, u32 access,
5392 struct x86_exception *exception)
5393 {
5394 void *data = val;
5395 int r = X86EMUL_CONTINUE;
5396
5397 while (bytes) {
5398 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5399 exception);
5400 unsigned offset = addr & (PAGE_SIZE-1);
5401 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5402 int ret;
5403
5404 if (gpa == UNMAPPED_GVA)
5405 return X86EMUL_PROPAGATE_FAULT;
5406 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5407 offset, toread);
5408 if (ret < 0) {
5409 r = X86EMUL_IO_NEEDED;
5410 goto out;
5411 }
5412
5413 bytes -= toread;
5414 data += toread;
5415 addr += toread;
5416 }
5417 out:
5418 return r;
5419 }
5420
5421 /* used for instruction fetching */
5422 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5423 gva_t addr, void *val, unsigned int bytes,
5424 struct x86_exception *exception)
5425 {
5426 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5427 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5428 unsigned offset;
5429 int ret;
5430
5431 /* Inline kvm_read_guest_virt_helper for speed. */
5432 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5433 exception);
5434 if (unlikely(gpa == UNMAPPED_GVA))
5435 return X86EMUL_PROPAGATE_FAULT;
5436
5437 offset = addr & (PAGE_SIZE-1);
5438 if (WARN_ON(offset + bytes > PAGE_SIZE))
5439 bytes = (unsigned)PAGE_SIZE - offset;
5440 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5441 offset, bytes);
5442 if (unlikely(ret < 0))
5443 return X86EMUL_IO_NEEDED;
5444
5445 return X86EMUL_CONTINUE;
5446 }
5447
5448 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5449 gva_t addr, void *val, unsigned int bytes,
5450 struct x86_exception *exception)
5451 {
5452 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5453
5454 /*
5455 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5456 * is returned, but our callers are not ready for that and they blindly
5457 * call kvm_inject_page_fault. Ensure that they at least do not leak
5458 * uninitialized kernel stack memory into cr2 and error code.
5459 */
5460 memset(exception, 0, sizeof(*exception));
5461 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5462 exception);
5463 }
5464 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5465
5466 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5467 gva_t addr, void *val, unsigned int bytes,
5468 struct x86_exception *exception, bool system)
5469 {
5470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5471 u32 access = 0;
5472
5473 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5474 access |= PFERR_USER_MASK;
5475
5476 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5477 }
5478
5479 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5480 unsigned long addr, void *val, unsigned int bytes)
5481 {
5482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5483 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5484
5485 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5486 }
5487
5488 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5489 struct kvm_vcpu *vcpu, u32 access,
5490 struct x86_exception *exception)
5491 {
5492 void *data = val;
5493 int r = X86EMUL_CONTINUE;
5494
5495 while (bytes) {
5496 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5497 access,
5498 exception);
5499 unsigned offset = addr & (PAGE_SIZE-1);
5500 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5501 int ret;
5502
5503 if (gpa == UNMAPPED_GVA)
5504 return X86EMUL_PROPAGATE_FAULT;
5505 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5506 if (ret < 0) {
5507 r = X86EMUL_IO_NEEDED;
5508 goto out;
5509 }
5510
5511 bytes -= towrite;
5512 data += towrite;
5513 addr += towrite;
5514 }
5515 out:
5516 return r;
5517 }
5518
5519 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5520 unsigned int bytes, struct x86_exception *exception,
5521 bool system)
5522 {
5523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5524 u32 access = PFERR_WRITE_MASK;
5525
5526 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5527 access |= PFERR_USER_MASK;
5528
5529 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5530 access, exception);
5531 }
5532
5533 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5534 unsigned int bytes, struct x86_exception *exception)
5535 {
5536 /* kvm_write_guest_virt_system can pull in tons of pages. */
5537 vcpu->arch.l1tf_flush_l1d = true;
5538
5539 /*
5540 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5541 * is returned, but our callers are not ready for that and they blindly
5542 * call kvm_inject_page_fault. Ensure that they at least do not leak
5543 * uninitialized kernel stack memory into cr2 and error code.
5544 */
5545 memset(exception, 0, sizeof(*exception));
5546 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5547 PFERR_WRITE_MASK, exception);
5548 }
5549 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5550
5551 int handle_ud(struct kvm_vcpu *vcpu)
5552 {
5553 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5554 int emul_type = EMULTYPE_TRAP_UD;
5555 char sig[5]; /* ud2; .ascii "kvm" */
5556 struct x86_exception e;
5557
5558 if (force_emulation_prefix &&
5559 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5560 sig, sizeof(sig), &e) == 0 &&
5561 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5562 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5563 emul_type = EMULTYPE_TRAP_UD_FORCED;
5564 }
5565
5566 return kvm_emulate_instruction(vcpu, emul_type);
5567 }
5568 EXPORT_SYMBOL_GPL(handle_ud);
5569
5570 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5571 gpa_t gpa, bool write)
5572 {
5573 /* For APIC access vmexit */
5574 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5575 return 1;
5576
5577 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5578 trace_vcpu_match_mmio(gva, gpa, write, true);
5579 return 1;
5580 }
5581
5582 return 0;
5583 }
5584
5585 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5586 gpa_t *gpa, struct x86_exception *exception,
5587 bool write)
5588 {
5589 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5590 | (write ? PFERR_WRITE_MASK : 0);
5591
5592 /*
5593 * currently PKRU is only applied to ept enabled guest so
5594 * there is no pkey in EPT page table for L1 guest or EPT
5595 * shadow page table for L2 guest.
5596 */
5597 if (vcpu_match_mmio_gva(vcpu, gva)
5598 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5599 vcpu->arch.mmio_access, 0, access)) {
5600 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5601 (gva & (PAGE_SIZE - 1));
5602 trace_vcpu_match_mmio(gva, *gpa, write, false);
5603 return 1;
5604 }
5605
5606 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5607
5608 if (*gpa == UNMAPPED_GVA)
5609 return -1;
5610
5611 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5612 }
5613
5614 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5615 const void *val, int bytes)
5616 {
5617 int ret;
5618
5619 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5620 if (ret < 0)
5621 return 0;
5622 kvm_page_track_write(vcpu, gpa, val, bytes);
5623 return 1;
5624 }
5625
5626 struct read_write_emulator_ops {
5627 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5628 int bytes);
5629 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5630 void *val, int bytes);
5631 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5632 int bytes, void *val);
5633 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5634 void *val, int bytes);
5635 bool write;
5636 };
5637
5638 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5639 {
5640 if (vcpu->mmio_read_completed) {
5641 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5642 vcpu->mmio_fragments[0].gpa, val);
5643 vcpu->mmio_read_completed = 0;
5644 return 1;
5645 }
5646
5647 return 0;
5648 }
5649
5650 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5651 void *val, int bytes)
5652 {
5653 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5654 }
5655
5656 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5657 void *val, int bytes)
5658 {
5659 return emulator_write_phys(vcpu, gpa, val, bytes);
5660 }
5661
5662 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5663 {
5664 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5665 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5666 }
5667
5668 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5669 void *val, int bytes)
5670 {
5671 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5672 return X86EMUL_IO_NEEDED;
5673 }
5674
5675 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5676 void *val, int bytes)
5677 {
5678 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5679
5680 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5681 return X86EMUL_CONTINUE;
5682 }
5683
5684 static const struct read_write_emulator_ops read_emultor = {
5685 .read_write_prepare = read_prepare,
5686 .read_write_emulate = read_emulate,
5687 .read_write_mmio = vcpu_mmio_read,
5688 .read_write_exit_mmio = read_exit_mmio,
5689 };
5690
5691 static const struct read_write_emulator_ops write_emultor = {
5692 .read_write_emulate = write_emulate,
5693 .read_write_mmio = write_mmio,
5694 .read_write_exit_mmio = write_exit_mmio,
5695 .write = true,
5696 };
5697
5698 static int emulator_read_write_onepage(unsigned long addr, void *val,
5699 unsigned int bytes,
5700 struct x86_exception *exception,
5701 struct kvm_vcpu *vcpu,
5702 const struct read_write_emulator_ops *ops)
5703 {
5704 gpa_t gpa;
5705 int handled, ret;
5706 bool write = ops->write;
5707 struct kvm_mmio_fragment *frag;
5708 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5709
5710 /*
5711 * If the exit was due to a NPF we may already have a GPA.
5712 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5713 * Note, this cannot be used on string operations since string
5714 * operation using rep will only have the initial GPA from the NPF
5715 * occurred.
5716 */
5717 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5718 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5719 gpa = ctxt->gpa_val;
5720 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5721 } else {
5722 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5723 if (ret < 0)
5724 return X86EMUL_PROPAGATE_FAULT;
5725 }
5726
5727 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5728 return X86EMUL_CONTINUE;
5729
5730 /*
5731 * Is this MMIO handled locally?
5732 */
5733 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5734 if (handled == bytes)
5735 return X86EMUL_CONTINUE;
5736
5737 gpa += handled;
5738 bytes -= handled;
5739 val += handled;
5740
5741 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5742 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5743 frag->gpa = gpa;
5744 frag->data = val;
5745 frag->len = bytes;
5746 return X86EMUL_CONTINUE;
5747 }
5748
5749 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5750 unsigned long addr,
5751 void *val, unsigned int bytes,
5752 struct x86_exception *exception,
5753 const struct read_write_emulator_ops *ops)
5754 {
5755 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5756 gpa_t gpa;
5757 int rc;
5758
5759 if (ops->read_write_prepare &&
5760 ops->read_write_prepare(vcpu, val, bytes))
5761 return X86EMUL_CONTINUE;
5762
5763 vcpu->mmio_nr_fragments = 0;
5764
5765 /* Crossing a page boundary? */
5766 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5767 int now;
5768
5769 now = -addr & ~PAGE_MASK;
5770 rc = emulator_read_write_onepage(addr, val, now, exception,
5771 vcpu, ops);
5772
5773 if (rc != X86EMUL_CONTINUE)
5774 return rc;
5775 addr += now;
5776 if (ctxt->mode != X86EMUL_MODE_PROT64)
5777 addr = (u32)addr;
5778 val += now;
5779 bytes -= now;
5780 }
5781
5782 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5783 vcpu, ops);
5784 if (rc != X86EMUL_CONTINUE)
5785 return rc;
5786
5787 if (!vcpu->mmio_nr_fragments)
5788 return rc;
5789
5790 gpa = vcpu->mmio_fragments[0].gpa;
5791
5792 vcpu->mmio_needed = 1;
5793 vcpu->mmio_cur_fragment = 0;
5794
5795 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5796 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5797 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5798 vcpu->run->mmio.phys_addr = gpa;
5799
5800 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5801 }
5802
5803 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5804 unsigned long addr,
5805 void *val,
5806 unsigned int bytes,
5807 struct x86_exception *exception)
5808 {
5809 return emulator_read_write(ctxt, addr, val, bytes,
5810 exception, &read_emultor);
5811 }
5812
5813 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5814 unsigned long addr,
5815 const void *val,
5816 unsigned int bytes,
5817 struct x86_exception *exception)
5818 {
5819 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5820 exception, &write_emultor);
5821 }
5822
5823 #define CMPXCHG_TYPE(t, ptr, old, new) \
5824 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5825
5826 #ifdef CONFIG_X86_64
5827 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5828 #else
5829 # define CMPXCHG64(ptr, old, new) \
5830 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5831 #endif
5832
5833 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5834 unsigned long addr,
5835 const void *old,
5836 const void *new,
5837 unsigned int bytes,
5838 struct x86_exception *exception)
5839 {
5840 struct kvm_host_map map;
5841 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5842 u64 page_line_mask;
5843 gpa_t gpa;
5844 char *kaddr;
5845 bool exchanged;
5846
5847 /* guests cmpxchg8b have to be emulated atomically */
5848 if (bytes > 8 || (bytes & (bytes - 1)))
5849 goto emul_write;
5850
5851 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5852
5853 if (gpa == UNMAPPED_GVA ||
5854 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5855 goto emul_write;
5856
5857 /*
5858 * Emulate the atomic as a straight write to avoid #AC if SLD is
5859 * enabled in the host and the access splits a cache line.
5860 */
5861 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5862 page_line_mask = ~(cache_line_size() - 1);
5863 else
5864 page_line_mask = PAGE_MASK;
5865
5866 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5867 goto emul_write;
5868
5869 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5870 goto emul_write;
5871
5872 kaddr = map.hva + offset_in_page(gpa);
5873
5874 switch (bytes) {
5875 case 1:
5876 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5877 break;
5878 case 2:
5879 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5880 break;
5881 case 4:
5882 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5883 break;
5884 case 8:
5885 exchanged = CMPXCHG64(kaddr, old, new);
5886 break;
5887 default:
5888 BUG();
5889 }
5890
5891 kvm_vcpu_unmap(vcpu, &map, true);
5892
5893 if (!exchanged)
5894 return X86EMUL_CMPXCHG_FAILED;
5895
5896 kvm_page_track_write(vcpu, gpa, new, bytes);
5897
5898 return X86EMUL_CONTINUE;
5899
5900 emul_write:
5901 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5902
5903 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5904 }
5905
5906 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5907 {
5908 int r = 0, i;
5909
5910 for (i = 0; i < vcpu->arch.pio.count; i++) {
5911 if (vcpu->arch.pio.in)
5912 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5913 vcpu->arch.pio.size, pd);
5914 else
5915 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5916 vcpu->arch.pio.port, vcpu->arch.pio.size,
5917 pd);
5918 if (r)
5919 break;
5920 pd += vcpu->arch.pio.size;
5921 }
5922 return r;
5923 }
5924
5925 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5926 unsigned short port, void *val,
5927 unsigned int count, bool in)
5928 {
5929 vcpu->arch.pio.port = port;
5930 vcpu->arch.pio.in = in;
5931 vcpu->arch.pio.count = count;
5932 vcpu->arch.pio.size = size;
5933
5934 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5935 vcpu->arch.pio.count = 0;
5936 return 1;
5937 }
5938
5939 vcpu->run->exit_reason = KVM_EXIT_IO;
5940 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5941 vcpu->run->io.size = size;
5942 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5943 vcpu->run->io.count = count;
5944 vcpu->run->io.port = port;
5945
5946 return 0;
5947 }
5948
5949 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5950 unsigned short port, void *val, unsigned int count)
5951 {
5952 int ret;
5953
5954 if (vcpu->arch.pio.count)
5955 goto data_avail;
5956
5957 memset(vcpu->arch.pio_data, 0, size * count);
5958
5959 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5960 if (ret) {
5961 data_avail:
5962 memcpy(val, vcpu->arch.pio_data, size * count);
5963 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5964 vcpu->arch.pio.count = 0;
5965 return 1;
5966 }
5967
5968 return 0;
5969 }
5970
5971 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5972 int size, unsigned short port, void *val,
5973 unsigned int count)
5974 {
5975 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
5976
5977 }
5978
5979 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
5980 unsigned short port, const void *val,
5981 unsigned int count)
5982 {
5983 memcpy(vcpu->arch.pio_data, val, size * count);
5984 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5985 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5986 }
5987
5988 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5989 int size, unsigned short port,
5990 const void *val, unsigned int count)
5991 {
5992 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
5993 }
5994
5995 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5996 {
5997 return kvm_x86_ops.get_segment_base(vcpu, seg);
5998 }
5999
6000 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6001 {
6002 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6003 }
6004
6005 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6006 {
6007 if (!need_emulate_wbinvd(vcpu))
6008 return X86EMUL_CONTINUE;
6009
6010 if (kvm_x86_ops.has_wbinvd_exit()) {
6011 int cpu = get_cpu();
6012
6013 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6014 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6015 wbinvd_ipi, NULL, 1);
6016 put_cpu();
6017 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6018 } else
6019 wbinvd();
6020 return X86EMUL_CONTINUE;
6021 }
6022
6023 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6024 {
6025 kvm_emulate_wbinvd_noskip(vcpu);
6026 return kvm_skip_emulated_instruction(vcpu);
6027 }
6028 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6029
6030
6031
6032 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6033 {
6034 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6035 }
6036
6037 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6038 unsigned long *dest)
6039 {
6040 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6041 }
6042
6043 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6044 unsigned long value)
6045 {
6046
6047 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6048 }
6049
6050 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6051 {
6052 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6053 }
6054
6055 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6056 {
6057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6058 unsigned long value;
6059
6060 switch (cr) {
6061 case 0:
6062 value = kvm_read_cr0(vcpu);
6063 break;
6064 case 2:
6065 value = vcpu->arch.cr2;
6066 break;
6067 case 3:
6068 value = kvm_read_cr3(vcpu);
6069 break;
6070 case 4:
6071 value = kvm_read_cr4(vcpu);
6072 break;
6073 case 8:
6074 value = kvm_get_cr8(vcpu);
6075 break;
6076 default:
6077 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6078 return 0;
6079 }
6080
6081 return value;
6082 }
6083
6084 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6085 {
6086 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6087 int res = 0;
6088
6089 switch (cr) {
6090 case 0:
6091 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6092 break;
6093 case 2:
6094 vcpu->arch.cr2 = val;
6095 break;
6096 case 3:
6097 res = kvm_set_cr3(vcpu, val);
6098 break;
6099 case 4:
6100 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6101 break;
6102 case 8:
6103 res = kvm_set_cr8(vcpu, val);
6104 break;
6105 default:
6106 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6107 res = -1;
6108 }
6109
6110 return res;
6111 }
6112
6113 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6114 {
6115 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6116 }
6117
6118 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6119 {
6120 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6121 }
6122
6123 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6124 {
6125 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6126 }
6127
6128 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6129 {
6130 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6131 }
6132
6133 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6134 {
6135 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6136 }
6137
6138 static unsigned long emulator_get_cached_segment_base(
6139 struct x86_emulate_ctxt *ctxt, int seg)
6140 {
6141 return get_segment_base(emul_to_vcpu(ctxt), seg);
6142 }
6143
6144 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6145 struct desc_struct *desc, u32 *base3,
6146 int seg)
6147 {
6148 struct kvm_segment var;
6149
6150 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6151 *selector = var.selector;
6152
6153 if (var.unusable) {
6154 memset(desc, 0, sizeof(*desc));
6155 if (base3)
6156 *base3 = 0;
6157 return false;
6158 }
6159
6160 if (var.g)
6161 var.limit >>= 12;
6162 set_desc_limit(desc, var.limit);
6163 set_desc_base(desc, (unsigned long)var.base);
6164 #ifdef CONFIG_X86_64
6165 if (base3)
6166 *base3 = var.base >> 32;
6167 #endif
6168 desc->type = var.type;
6169 desc->s = var.s;
6170 desc->dpl = var.dpl;
6171 desc->p = var.present;
6172 desc->avl = var.avl;
6173 desc->l = var.l;
6174 desc->d = var.db;
6175 desc->g = var.g;
6176
6177 return true;
6178 }
6179
6180 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6181 struct desc_struct *desc, u32 base3,
6182 int seg)
6183 {
6184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6185 struct kvm_segment var;
6186
6187 var.selector = selector;
6188 var.base = get_desc_base(desc);
6189 #ifdef CONFIG_X86_64
6190 var.base |= ((u64)base3) << 32;
6191 #endif
6192 var.limit = get_desc_limit(desc);
6193 if (desc->g)
6194 var.limit = (var.limit << 12) | 0xfff;
6195 var.type = desc->type;
6196 var.dpl = desc->dpl;
6197 var.db = desc->d;
6198 var.s = desc->s;
6199 var.l = desc->l;
6200 var.g = desc->g;
6201 var.avl = desc->avl;
6202 var.present = desc->p;
6203 var.unusable = !var.present;
6204 var.padding = 0;
6205
6206 kvm_set_segment(vcpu, &var, seg);
6207 return;
6208 }
6209
6210 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6211 u32 msr_index, u64 *pdata)
6212 {
6213 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6214 }
6215
6216 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6217 u32 msr_index, u64 data)
6218 {
6219 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6220 }
6221
6222 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6223 {
6224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6225
6226 return vcpu->arch.smbase;
6227 }
6228
6229 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6230 {
6231 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6232
6233 vcpu->arch.smbase = smbase;
6234 }
6235
6236 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6237 u32 pmc)
6238 {
6239 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6240 }
6241
6242 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6243 u32 pmc, u64 *pdata)
6244 {
6245 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6246 }
6247
6248 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6249 {
6250 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6251 }
6252
6253 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6254 struct x86_instruction_info *info,
6255 enum x86_intercept_stage stage)
6256 {
6257 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6258 &ctxt->exception);
6259 }
6260
6261 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6262 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6263 bool exact_only)
6264 {
6265 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6266 }
6267
6268 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6269 {
6270 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6271 }
6272
6273 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6274 {
6275 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6276 }
6277
6278 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6279 {
6280 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6281 }
6282
6283 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6284 {
6285 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6286 }
6287
6288 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6289 {
6290 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6291 }
6292
6293 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6294 {
6295 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6296 }
6297
6298 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6299 {
6300 return emul_to_vcpu(ctxt)->arch.hflags;
6301 }
6302
6303 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6304 {
6305 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6306 }
6307
6308 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6309 const char *smstate)
6310 {
6311 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6312 }
6313
6314 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6315 {
6316 kvm_smm_changed(emul_to_vcpu(ctxt));
6317 }
6318
6319 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6320 {
6321 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6322 }
6323
6324 static const struct x86_emulate_ops emulate_ops = {
6325 .read_gpr = emulator_read_gpr,
6326 .write_gpr = emulator_write_gpr,
6327 .read_std = emulator_read_std,
6328 .write_std = emulator_write_std,
6329 .read_phys = kvm_read_guest_phys_system,
6330 .fetch = kvm_fetch_guest_virt,
6331 .read_emulated = emulator_read_emulated,
6332 .write_emulated = emulator_write_emulated,
6333 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6334 .invlpg = emulator_invlpg,
6335 .pio_in_emulated = emulator_pio_in_emulated,
6336 .pio_out_emulated = emulator_pio_out_emulated,
6337 .get_segment = emulator_get_segment,
6338 .set_segment = emulator_set_segment,
6339 .get_cached_segment_base = emulator_get_cached_segment_base,
6340 .get_gdt = emulator_get_gdt,
6341 .get_idt = emulator_get_idt,
6342 .set_gdt = emulator_set_gdt,
6343 .set_idt = emulator_set_idt,
6344 .get_cr = emulator_get_cr,
6345 .set_cr = emulator_set_cr,
6346 .cpl = emulator_get_cpl,
6347 .get_dr = emulator_get_dr,
6348 .set_dr = emulator_set_dr,
6349 .get_smbase = emulator_get_smbase,
6350 .set_smbase = emulator_set_smbase,
6351 .set_msr = emulator_set_msr,
6352 .get_msr = emulator_get_msr,
6353 .check_pmc = emulator_check_pmc,
6354 .read_pmc = emulator_read_pmc,
6355 .halt = emulator_halt,
6356 .wbinvd = emulator_wbinvd,
6357 .fix_hypercall = emulator_fix_hypercall,
6358 .intercept = emulator_intercept,
6359 .get_cpuid = emulator_get_cpuid,
6360 .guest_has_long_mode = emulator_guest_has_long_mode,
6361 .guest_has_movbe = emulator_guest_has_movbe,
6362 .guest_has_fxsr = emulator_guest_has_fxsr,
6363 .set_nmi_mask = emulator_set_nmi_mask,
6364 .get_hflags = emulator_get_hflags,
6365 .set_hflags = emulator_set_hflags,
6366 .pre_leave_smm = emulator_pre_leave_smm,
6367 .post_leave_smm = emulator_post_leave_smm,
6368 .set_xcr = emulator_set_xcr,
6369 };
6370
6371 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6372 {
6373 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6374 /*
6375 * an sti; sti; sequence only disable interrupts for the first
6376 * instruction. So, if the last instruction, be it emulated or
6377 * not, left the system with the INT_STI flag enabled, it
6378 * means that the last instruction is an sti. We should not
6379 * leave the flag on in this case. The same goes for mov ss
6380 */
6381 if (int_shadow & mask)
6382 mask = 0;
6383 if (unlikely(int_shadow || mask)) {
6384 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6385 if (!mask)
6386 kvm_make_request(KVM_REQ_EVENT, vcpu);
6387 }
6388 }
6389
6390 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6391 {
6392 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6393 if (ctxt->exception.vector == PF_VECTOR)
6394 return kvm_propagate_fault(vcpu, &ctxt->exception);
6395
6396 if (ctxt->exception.error_code_valid)
6397 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6398 ctxt->exception.error_code);
6399 else
6400 kvm_queue_exception(vcpu, ctxt->exception.vector);
6401 return false;
6402 }
6403
6404 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6405 {
6406 struct x86_emulate_ctxt *ctxt;
6407
6408 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6409 if (!ctxt) {
6410 pr_err("kvm: failed to allocate vcpu's emulator\n");
6411 return NULL;
6412 }
6413
6414 ctxt->vcpu = vcpu;
6415 ctxt->ops = &emulate_ops;
6416 vcpu->arch.emulate_ctxt = ctxt;
6417
6418 return ctxt;
6419 }
6420
6421 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6422 {
6423 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6424 int cs_db, cs_l;
6425
6426 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6427
6428 ctxt->gpa_available = false;
6429 ctxt->eflags = kvm_get_rflags(vcpu);
6430 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6431
6432 ctxt->eip = kvm_rip_read(vcpu);
6433 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6434 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6435 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6436 cs_db ? X86EMUL_MODE_PROT32 :
6437 X86EMUL_MODE_PROT16;
6438 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6439 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6440 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6441
6442 init_decode_cache(ctxt);
6443 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6444 }
6445
6446 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6447 {
6448 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6449 int ret;
6450
6451 init_emulate_ctxt(vcpu);
6452
6453 ctxt->op_bytes = 2;
6454 ctxt->ad_bytes = 2;
6455 ctxt->_eip = ctxt->eip + inc_eip;
6456 ret = emulate_int_real(ctxt, irq);
6457
6458 if (ret != X86EMUL_CONTINUE) {
6459 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6460 } else {
6461 ctxt->eip = ctxt->_eip;
6462 kvm_rip_write(vcpu, ctxt->eip);
6463 kvm_set_rflags(vcpu, ctxt->eflags);
6464 }
6465 }
6466 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6467
6468 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6469 {
6470 ++vcpu->stat.insn_emulation_fail;
6471 trace_kvm_emulate_insn_failed(vcpu);
6472
6473 if (emulation_type & EMULTYPE_VMWARE_GP) {
6474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6475 return 1;
6476 }
6477
6478 if (emulation_type & EMULTYPE_SKIP) {
6479 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6480 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6481 vcpu->run->internal.ndata = 0;
6482 return 0;
6483 }
6484
6485 kvm_queue_exception(vcpu, UD_VECTOR);
6486
6487 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6488 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6489 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6490 vcpu->run->internal.ndata = 0;
6491 return 0;
6492 }
6493
6494 return 1;
6495 }
6496
6497 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6498 bool write_fault_to_shadow_pgtable,
6499 int emulation_type)
6500 {
6501 gpa_t gpa = cr2_or_gpa;
6502 kvm_pfn_t pfn;
6503
6504 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6505 return false;
6506
6507 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6508 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6509 return false;
6510
6511 if (!vcpu->arch.mmu->direct_map) {
6512 /*
6513 * Write permission should be allowed since only
6514 * write access need to be emulated.
6515 */
6516 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6517
6518 /*
6519 * If the mapping is invalid in guest, let cpu retry
6520 * it to generate fault.
6521 */
6522 if (gpa == UNMAPPED_GVA)
6523 return true;
6524 }
6525
6526 /*
6527 * Do not retry the unhandleable instruction if it faults on the
6528 * readonly host memory, otherwise it will goto a infinite loop:
6529 * retry instruction -> write #PF -> emulation fail -> retry
6530 * instruction -> ...
6531 */
6532 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6533
6534 /*
6535 * If the instruction failed on the error pfn, it can not be fixed,
6536 * report the error to userspace.
6537 */
6538 if (is_error_noslot_pfn(pfn))
6539 return false;
6540
6541 kvm_release_pfn_clean(pfn);
6542
6543 /* The instructions are well-emulated on direct mmu. */
6544 if (vcpu->arch.mmu->direct_map) {
6545 unsigned int indirect_shadow_pages;
6546
6547 spin_lock(&vcpu->kvm->mmu_lock);
6548 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6549 spin_unlock(&vcpu->kvm->mmu_lock);
6550
6551 if (indirect_shadow_pages)
6552 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6553
6554 return true;
6555 }
6556
6557 /*
6558 * if emulation was due to access to shadowed page table
6559 * and it failed try to unshadow page and re-enter the
6560 * guest to let CPU execute the instruction.
6561 */
6562 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6563
6564 /*
6565 * If the access faults on its page table, it can not
6566 * be fixed by unprotecting shadow page and it should
6567 * be reported to userspace.
6568 */
6569 return !write_fault_to_shadow_pgtable;
6570 }
6571
6572 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6573 gpa_t cr2_or_gpa, int emulation_type)
6574 {
6575 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6576 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6577
6578 last_retry_eip = vcpu->arch.last_retry_eip;
6579 last_retry_addr = vcpu->arch.last_retry_addr;
6580
6581 /*
6582 * If the emulation is caused by #PF and it is non-page_table
6583 * writing instruction, it means the VM-EXIT is caused by shadow
6584 * page protected, we can zap the shadow page and retry this
6585 * instruction directly.
6586 *
6587 * Note: if the guest uses a non-page-table modifying instruction
6588 * on the PDE that points to the instruction, then we will unmap
6589 * the instruction and go to an infinite loop. So, we cache the
6590 * last retried eip and the last fault address, if we meet the eip
6591 * and the address again, we can break out of the potential infinite
6592 * loop.
6593 */
6594 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6595
6596 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6597 return false;
6598
6599 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6600 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6601 return false;
6602
6603 if (x86_page_table_writing_insn(ctxt))
6604 return false;
6605
6606 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6607 return false;
6608
6609 vcpu->arch.last_retry_eip = ctxt->eip;
6610 vcpu->arch.last_retry_addr = cr2_or_gpa;
6611
6612 if (!vcpu->arch.mmu->direct_map)
6613 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6614
6615 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6616
6617 return true;
6618 }
6619
6620 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6621 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6622
6623 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6624 {
6625 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6626 /* This is a good place to trace that we are exiting SMM. */
6627 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6628
6629 /* Process a latched INIT or SMI, if any. */
6630 kvm_make_request(KVM_REQ_EVENT, vcpu);
6631 }
6632
6633 kvm_mmu_reset_context(vcpu);
6634 }
6635
6636 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6637 unsigned long *db)
6638 {
6639 u32 dr6 = 0;
6640 int i;
6641 u32 enable, rwlen;
6642
6643 enable = dr7;
6644 rwlen = dr7 >> 16;
6645 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6646 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6647 dr6 |= (1 << i);
6648 return dr6;
6649 }
6650
6651 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6652 {
6653 struct kvm_run *kvm_run = vcpu->run;
6654
6655 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6656 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6657 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6658 kvm_run->debug.arch.exception = DB_VECTOR;
6659 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6660 return 0;
6661 }
6662 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6663 return 1;
6664 }
6665
6666 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6667 {
6668 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6669 int r;
6670
6671 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6672 if (unlikely(!r))
6673 return 0;
6674
6675 /*
6676 * rflags is the old, "raw" value of the flags. The new value has
6677 * not been saved yet.
6678 *
6679 * This is correct even for TF set by the guest, because "the
6680 * processor will not generate this exception after the instruction
6681 * that sets the TF flag".
6682 */
6683 if (unlikely(rflags & X86_EFLAGS_TF))
6684 r = kvm_vcpu_do_singlestep(vcpu);
6685 return r;
6686 }
6687 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6688
6689 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6690 {
6691 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6692 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6693 struct kvm_run *kvm_run = vcpu->run;
6694 unsigned long eip = kvm_get_linear_rip(vcpu);
6695 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6696 vcpu->arch.guest_debug_dr7,
6697 vcpu->arch.eff_db);
6698
6699 if (dr6 != 0) {
6700 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6701 kvm_run->debug.arch.pc = eip;
6702 kvm_run->debug.arch.exception = DB_VECTOR;
6703 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6704 *r = 0;
6705 return true;
6706 }
6707 }
6708
6709 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6710 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6711 unsigned long eip = kvm_get_linear_rip(vcpu);
6712 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6713 vcpu->arch.dr7,
6714 vcpu->arch.db);
6715
6716 if (dr6 != 0) {
6717 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6718 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6719 kvm_queue_exception(vcpu, DB_VECTOR);
6720 *r = 1;
6721 return true;
6722 }
6723 }
6724
6725 return false;
6726 }
6727
6728 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6729 {
6730 switch (ctxt->opcode_len) {
6731 case 1:
6732 switch (ctxt->b) {
6733 case 0xe4: /* IN */
6734 case 0xe5:
6735 case 0xec:
6736 case 0xed:
6737 case 0xe6: /* OUT */
6738 case 0xe7:
6739 case 0xee:
6740 case 0xef:
6741 case 0x6c: /* INS */
6742 case 0x6d:
6743 case 0x6e: /* OUTS */
6744 case 0x6f:
6745 return true;
6746 }
6747 break;
6748 case 2:
6749 switch (ctxt->b) {
6750 case 0x33: /* RDPMC */
6751 return true;
6752 }
6753 break;
6754 }
6755
6756 return false;
6757 }
6758
6759 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6760 int emulation_type, void *insn, int insn_len)
6761 {
6762 int r;
6763 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6764 bool writeback = true;
6765 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6766
6767 vcpu->arch.l1tf_flush_l1d = true;
6768
6769 /*
6770 * Clear write_fault_to_shadow_pgtable here to ensure it is
6771 * never reused.
6772 */
6773 vcpu->arch.write_fault_to_shadow_pgtable = false;
6774 kvm_clear_exception_queue(vcpu);
6775
6776 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6777 init_emulate_ctxt(vcpu);
6778
6779 /*
6780 * We will reenter on the same instruction since
6781 * we do not set complete_userspace_io. This does not
6782 * handle watchpoints yet, those would be handled in
6783 * the emulate_ops.
6784 */
6785 if (!(emulation_type & EMULTYPE_SKIP) &&
6786 kvm_vcpu_check_breakpoint(vcpu, &r))
6787 return r;
6788
6789 ctxt->interruptibility = 0;
6790 ctxt->have_exception = false;
6791 ctxt->exception.vector = -1;
6792 ctxt->perm_ok = false;
6793
6794 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6795
6796 r = x86_decode_insn(ctxt, insn, insn_len);
6797
6798 trace_kvm_emulate_insn_start(vcpu);
6799 ++vcpu->stat.insn_emulation;
6800 if (r != EMULATION_OK) {
6801 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6802 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6803 kvm_queue_exception(vcpu, UD_VECTOR);
6804 return 1;
6805 }
6806 if (reexecute_instruction(vcpu, cr2_or_gpa,
6807 write_fault_to_spt,
6808 emulation_type))
6809 return 1;
6810 if (ctxt->have_exception) {
6811 /*
6812 * #UD should result in just EMULATION_FAILED, and trap-like
6813 * exception should not be encountered during decode.
6814 */
6815 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6816 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6817 inject_emulated_exception(vcpu);
6818 return 1;
6819 }
6820 return handle_emulation_failure(vcpu, emulation_type);
6821 }
6822 }
6823
6824 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6825 !is_vmware_backdoor_opcode(ctxt)) {
6826 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6827 return 1;
6828 }
6829
6830 /*
6831 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6832 * for kvm_skip_emulated_instruction(). The caller is responsible for
6833 * updating interruptibility state and injecting single-step #DBs.
6834 */
6835 if (emulation_type & EMULTYPE_SKIP) {
6836 kvm_rip_write(vcpu, ctxt->_eip);
6837 if (ctxt->eflags & X86_EFLAGS_RF)
6838 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6839 return 1;
6840 }
6841
6842 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6843 return 1;
6844
6845 /* this is needed for vmware backdoor interface to work since it
6846 changes registers values during IO operation */
6847 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6848 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6849 emulator_invalidate_register_cache(ctxt);
6850 }
6851
6852 restart:
6853 if (emulation_type & EMULTYPE_PF) {
6854 /* Save the faulting GPA (cr2) in the address field */
6855 ctxt->exception.address = cr2_or_gpa;
6856
6857 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6858 if (vcpu->arch.mmu->direct_map) {
6859 ctxt->gpa_available = true;
6860 ctxt->gpa_val = cr2_or_gpa;
6861 }
6862 } else {
6863 /* Sanitize the address out of an abundance of paranoia. */
6864 ctxt->exception.address = 0;
6865 }
6866
6867 r = x86_emulate_insn(ctxt);
6868
6869 if (r == EMULATION_INTERCEPTED)
6870 return 1;
6871
6872 if (r == EMULATION_FAILED) {
6873 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6874 emulation_type))
6875 return 1;
6876
6877 return handle_emulation_failure(vcpu, emulation_type);
6878 }
6879
6880 if (ctxt->have_exception) {
6881 r = 1;
6882 if (inject_emulated_exception(vcpu))
6883 return r;
6884 } else if (vcpu->arch.pio.count) {
6885 if (!vcpu->arch.pio.in) {
6886 /* FIXME: return into emulator if single-stepping. */
6887 vcpu->arch.pio.count = 0;
6888 } else {
6889 writeback = false;
6890 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6891 }
6892 r = 0;
6893 } else if (vcpu->mmio_needed) {
6894 ++vcpu->stat.mmio_exits;
6895
6896 if (!vcpu->mmio_is_write)
6897 writeback = false;
6898 r = 0;
6899 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6900 } else if (r == EMULATION_RESTART)
6901 goto restart;
6902 else
6903 r = 1;
6904
6905 if (writeback) {
6906 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6907 toggle_interruptibility(vcpu, ctxt->interruptibility);
6908 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6909 if (!ctxt->have_exception ||
6910 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6911 kvm_rip_write(vcpu, ctxt->eip);
6912 if (r && ctxt->tf)
6913 r = kvm_vcpu_do_singlestep(vcpu);
6914 if (kvm_x86_ops.update_emulated_instruction)
6915 kvm_x86_ops.update_emulated_instruction(vcpu);
6916 __kvm_set_rflags(vcpu, ctxt->eflags);
6917 }
6918
6919 /*
6920 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6921 * do nothing, and it will be requested again as soon as
6922 * the shadow expires. But we still need to check here,
6923 * because POPF has no interrupt shadow.
6924 */
6925 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6926 kvm_make_request(KVM_REQ_EVENT, vcpu);
6927 } else
6928 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6929
6930 return r;
6931 }
6932
6933 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6934 {
6935 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6936 }
6937 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6938
6939 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6940 void *insn, int insn_len)
6941 {
6942 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6943 }
6944 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6945
6946 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6947 {
6948 vcpu->arch.pio.count = 0;
6949 return 1;
6950 }
6951
6952 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6953 {
6954 vcpu->arch.pio.count = 0;
6955
6956 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6957 return 1;
6958
6959 return kvm_skip_emulated_instruction(vcpu);
6960 }
6961
6962 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6963 unsigned short port)
6964 {
6965 unsigned long val = kvm_rax_read(vcpu);
6966 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6967
6968 if (ret)
6969 return ret;
6970
6971 /*
6972 * Workaround userspace that relies on old KVM behavior of %rip being
6973 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6974 */
6975 if (port == 0x7e &&
6976 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6977 vcpu->arch.complete_userspace_io =
6978 complete_fast_pio_out_port_0x7e;
6979 kvm_skip_emulated_instruction(vcpu);
6980 } else {
6981 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6982 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6983 }
6984 return 0;
6985 }
6986
6987 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6988 {
6989 unsigned long val;
6990
6991 /* We should only ever be called with arch.pio.count equal to 1 */
6992 BUG_ON(vcpu->arch.pio.count != 1);
6993
6994 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6995 vcpu->arch.pio.count = 0;
6996 return 1;
6997 }
6998
6999 /* For size less than 4 we merge, else we zero extend */
7000 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7001
7002 /*
7003 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7004 * the copy and tracing
7005 */
7006 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7007 kvm_rax_write(vcpu, val);
7008
7009 return kvm_skip_emulated_instruction(vcpu);
7010 }
7011
7012 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7013 unsigned short port)
7014 {
7015 unsigned long val;
7016 int ret;
7017
7018 /* For size less than 4 we merge, else we zero extend */
7019 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7020
7021 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7022 if (ret) {
7023 kvm_rax_write(vcpu, val);
7024 return ret;
7025 }
7026
7027 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7028 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7029
7030 return 0;
7031 }
7032
7033 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7034 {
7035 int ret;
7036
7037 if (in)
7038 ret = kvm_fast_pio_in(vcpu, size, port);
7039 else
7040 ret = kvm_fast_pio_out(vcpu, size, port);
7041 return ret && kvm_skip_emulated_instruction(vcpu);
7042 }
7043 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7044
7045 static int kvmclock_cpu_down_prep(unsigned int cpu)
7046 {
7047 __this_cpu_write(cpu_tsc_khz, 0);
7048 return 0;
7049 }
7050
7051 static void tsc_khz_changed(void *data)
7052 {
7053 struct cpufreq_freqs *freq = data;
7054 unsigned long khz = 0;
7055
7056 if (data)
7057 khz = freq->new;
7058 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7059 khz = cpufreq_quick_get(raw_smp_processor_id());
7060 if (!khz)
7061 khz = tsc_khz;
7062 __this_cpu_write(cpu_tsc_khz, khz);
7063 }
7064
7065 #ifdef CONFIG_X86_64
7066 static void kvm_hyperv_tsc_notifier(void)
7067 {
7068 struct kvm *kvm;
7069 struct kvm_vcpu *vcpu;
7070 int cpu;
7071
7072 mutex_lock(&kvm_lock);
7073 list_for_each_entry(kvm, &vm_list, vm_list)
7074 kvm_make_mclock_inprogress_request(kvm);
7075
7076 hyperv_stop_tsc_emulation();
7077
7078 /* TSC frequency always matches when on Hyper-V */
7079 for_each_present_cpu(cpu)
7080 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7081 kvm_max_guest_tsc_khz = tsc_khz;
7082
7083 list_for_each_entry(kvm, &vm_list, vm_list) {
7084 struct kvm_arch *ka = &kvm->arch;
7085
7086 spin_lock(&ka->pvclock_gtod_sync_lock);
7087
7088 pvclock_update_vm_gtod_copy(kvm);
7089
7090 kvm_for_each_vcpu(cpu, vcpu, kvm)
7091 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7092
7093 kvm_for_each_vcpu(cpu, vcpu, kvm)
7094 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7095
7096 spin_unlock(&ka->pvclock_gtod_sync_lock);
7097 }
7098 mutex_unlock(&kvm_lock);
7099 }
7100 #endif
7101
7102 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7103 {
7104 struct kvm *kvm;
7105 struct kvm_vcpu *vcpu;
7106 int i, send_ipi = 0;
7107
7108 /*
7109 * We allow guests to temporarily run on slowing clocks,
7110 * provided we notify them after, or to run on accelerating
7111 * clocks, provided we notify them before. Thus time never
7112 * goes backwards.
7113 *
7114 * However, we have a problem. We can't atomically update
7115 * the frequency of a given CPU from this function; it is
7116 * merely a notifier, which can be called from any CPU.
7117 * Changing the TSC frequency at arbitrary points in time
7118 * requires a recomputation of local variables related to
7119 * the TSC for each VCPU. We must flag these local variables
7120 * to be updated and be sure the update takes place with the
7121 * new frequency before any guests proceed.
7122 *
7123 * Unfortunately, the combination of hotplug CPU and frequency
7124 * change creates an intractable locking scenario; the order
7125 * of when these callouts happen is undefined with respect to
7126 * CPU hotplug, and they can race with each other. As such,
7127 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7128 * undefined; you can actually have a CPU frequency change take
7129 * place in between the computation of X and the setting of the
7130 * variable. To protect against this problem, all updates of
7131 * the per_cpu tsc_khz variable are done in an interrupt
7132 * protected IPI, and all callers wishing to update the value
7133 * must wait for a synchronous IPI to complete (which is trivial
7134 * if the caller is on the CPU already). This establishes the
7135 * necessary total order on variable updates.
7136 *
7137 * Note that because a guest time update may take place
7138 * anytime after the setting of the VCPU's request bit, the
7139 * correct TSC value must be set before the request. However,
7140 * to ensure the update actually makes it to any guest which
7141 * starts running in hardware virtualization between the set
7142 * and the acquisition of the spinlock, we must also ping the
7143 * CPU after setting the request bit.
7144 *
7145 */
7146
7147 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7148
7149 mutex_lock(&kvm_lock);
7150 list_for_each_entry(kvm, &vm_list, vm_list) {
7151 kvm_for_each_vcpu(i, vcpu, kvm) {
7152 if (vcpu->cpu != cpu)
7153 continue;
7154 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7155 if (vcpu->cpu != raw_smp_processor_id())
7156 send_ipi = 1;
7157 }
7158 }
7159 mutex_unlock(&kvm_lock);
7160
7161 if (freq->old < freq->new && send_ipi) {
7162 /*
7163 * We upscale the frequency. Must make the guest
7164 * doesn't see old kvmclock values while running with
7165 * the new frequency, otherwise we risk the guest sees
7166 * time go backwards.
7167 *
7168 * In case we update the frequency for another cpu
7169 * (which might be in guest context) send an interrupt
7170 * to kick the cpu out of guest context. Next time
7171 * guest context is entered kvmclock will be updated,
7172 * so the guest will not see stale values.
7173 */
7174 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7175 }
7176 }
7177
7178 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7179 void *data)
7180 {
7181 struct cpufreq_freqs *freq = data;
7182 int cpu;
7183
7184 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7185 return 0;
7186 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7187 return 0;
7188
7189 for_each_cpu(cpu, freq->policy->cpus)
7190 __kvmclock_cpufreq_notifier(freq, cpu);
7191
7192 return 0;
7193 }
7194
7195 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7196 .notifier_call = kvmclock_cpufreq_notifier
7197 };
7198
7199 static int kvmclock_cpu_online(unsigned int cpu)
7200 {
7201 tsc_khz_changed(NULL);
7202 return 0;
7203 }
7204
7205 static void kvm_timer_init(void)
7206 {
7207 max_tsc_khz = tsc_khz;
7208
7209 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7210 #ifdef CONFIG_CPU_FREQ
7211 struct cpufreq_policy *policy;
7212 int cpu;
7213
7214 cpu = get_cpu();
7215 policy = cpufreq_cpu_get(cpu);
7216 if (policy) {
7217 if (policy->cpuinfo.max_freq)
7218 max_tsc_khz = policy->cpuinfo.max_freq;
7219 cpufreq_cpu_put(policy);
7220 }
7221 put_cpu();
7222 #endif
7223 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7224 CPUFREQ_TRANSITION_NOTIFIER);
7225 }
7226
7227 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7228 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7229 }
7230
7231 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7232 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7233
7234 int kvm_is_in_guest(void)
7235 {
7236 return __this_cpu_read(current_vcpu) != NULL;
7237 }
7238
7239 static int kvm_is_user_mode(void)
7240 {
7241 int user_mode = 3;
7242
7243 if (__this_cpu_read(current_vcpu))
7244 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7245
7246 return user_mode != 0;
7247 }
7248
7249 static unsigned long kvm_get_guest_ip(void)
7250 {
7251 unsigned long ip = 0;
7252
7253 if (__this_cpu_read(current_vcpu))
7254 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7255
7256 return ip;
7257 }
7258
7259 static void kvm_handle_intel_pt_intr(void)
7260 {
7261 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7262
7263 kvm_make_request(KVM_REQ_PMI, vcpu);
7264 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7265 (unsigned long *)&vcpu->arch.pmu.global_status);
7266 }
7267
7268 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7269 .is_in_guest = kvm_is_in_guest,
7270 .is_user_mode = kvm_is_user_mode,
7271 .get_guest_ip = kvm_get_guest_ip,
7272 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7273 };
7274
7275 #ifdef CONFIG_X86_64
7276 static void pvclock_gtod_update_fn(struct work_struct *work)
7277 {
7278 struct kvm *kvm;
7279
7280 struct kvm_vcpu *vcpu;
7281 int i;
7282
7283 mutex_lock(&kvm_lock);
7284 list_for_each_entry(kvm, &vm_list, vm_list)
7285 kvm_for_each_vcpu(i, vcpu, kvm)
7286 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7287 atomic_set(&kvm_guest_has_master_clock, 0);
7288 mutex_unlock(&kvm_lock);
7289 }
7290
7291 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7292
7293 /*
7294 * Notification about pvclock gtod data update.
7295 */
7296 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7297 void *priv)
7298 {
7299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7300 struct timekeeper *tk = priv;
7301
7302 update_pvclock_gtod(tk);
7303
7304 /* disable master clock if host does not trust, or does not
7305 * use, TSC based clocksource.
7306 */
7307 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7308 atomic_read(&kvm_guest_has_master_clock) != 0)
7309 queue_work(system_long_wq, &pvclock_gtod_work);
7310
7311 return 0;
7312 }
7313
7314 static struct notifier_block pvclock_gtod_notifier = {
7315 .notifier_call = pvclock_gtod_notify,
7316 };
7317 #endif
7318
7319 int kvm_arch_init(void *opaque)
7320 {
7321 struct kvm_x86_init_ops *ops = opaque;
7322 int r;
7323
7324 if (kvm_x86_ops.hardware_enable) {
7325 printk(KERN_ERR "kvm: already loaded the other module\n");
7326 r = -EEXIST;
7327 goto out;
7328 }
7329
7330 if (!ops->cpu_has_kvm_support()) {
7331 pr_err_ratelimited("kvm: no hardware support\n");
7332 r = -EOPNOTSUPP;
7333 goto out;
7334 }
7335 if (ops->disabled_by_bios()) {
7336 pr_err_ratelimited("kvm: disabled by bios\n");
7337 r = -EOPNOTSUPP;
7338 goto out;
7339 }
7340
7341 /*
7342 * KVM explicitly assumes that the guest has an FPU and
7343 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7344 * vCPU's FPU state as a fxregs_state struct.
7345 */
7346 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7347 printk(KERN_ERR "kvm: inadequate fpu\n");
7348 r = -EOPNOTSUPP;
7349 goto out;
7350 }
7351
7352 r = -ENOMEM;
7353 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7354 __alignof__(struct fpu), SLAB_ACCOUNT,
7355 NULL);
7356 if (!x86_fpu_cache) {
7357 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7358 goto out;
7359 }
7360
7361 x86_emulator_cache = kvm_alloc_emulator_cache();
7362 if (!x86_emulator_cache) {
7363 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7364 goto out_free_x86_fpu_cache;
7365 }
7366
7367 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7368 if (!shared_msrs) {
7369 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7370 goto out_free_x86_emulator_cache;
7371 }
7372
7373 r = kvm_mmu_module_init();
7374 if (r)
7375 goto out_free_percpu;
7376
7377 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7378 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7379 PT_PRESENT_MASK, 0, sme_me_mask);
7380 kvm_timer_init();
7381
7382 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7383
7384 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7385 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7386 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7387 }
7388
7389 kvm_lapic_init();
7390 if (pi_inject_timer == -1)
7391 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7392 #ifdef CONFIG_X86_64
7393 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7394
7395 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7396 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7397 #endif
7398
7399 return 0;
7400
7401 out_free_percpu:
7402 free_percpu(shared_msrs);
7403 out_free_x86_emulator_cache:
7404 kmem_cache_destroy(x86_emulator_cache);
7405 out_free_x86_fpu_cache:
7406 kmem_cache_destroy(x86_fpu_cache);
7407 out:
7408 return r;
7409 }
7410
7411 void kvm_arch_exit(void)
7412 {
7413 #ifdef CONFIG_X86_64
7414 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7415 clear_hv_tscchange_cb();
7416 #endif
7417 kvm_lapic_exit();
7418 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7419
7420 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7421 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7422 CPUFREQ_TRANSITION_NOTIFIER);
7423 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7424 #ifdef CONFIG_X86_64
7425 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7426 #endif
7427 kvm_x86_ops.hardware_enable = NULL;
7428 kvm_mmu_module_exit();
7429 free_percpu(shared_msrs);
7430 kmem_cache_destroy(x86_fpu_cache);
7431 }
7432
7433 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7434 {
7435 ++vcpu->stat.halt_exits;
7436 if (lapic_in_kernel(vcpu)) {
7437 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7438 return 1;
7439 } else {
7440 vcpu->run->exit_reason = KVM_EXIT_HLT;
7441 return 0;
7442 }
7443 }
7444 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7445
7446 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7447 {
7448 int ret = kvm_skip_emulated_instruction(vcpu);
7449 /*
7450 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7451 * KVM_EXIT_DEBUG here.
7452 */
7453 return kvm_vcpu_halt(vcpu) && ret;
7454 }
7455 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7456
7457 #ifdef CONFIG_X86_64
7458 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7459 unsigned long clock_type)
7460 {
7461 struct kvm_clock_pairing clock_pairing;
7462 struct timespec64 ts;
7463 u64 cycle;
7464 int ret;
7465
7466 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7467 return -KVM_EOPNOTSUPP;
7468
7469 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7470 return -KVM_EOPNOTSUPP;
7471
7472 clock_pairing.sec = ts.tv_sec;
7473 clock_pairing.nsec = ts.tv_nsec;
7474 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7475 clock_pairing.flags = 0;
7476 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7477
7478 ret = 0;
7479 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7480 sizeof(struct kvm_clock_pairing)))
7481 ret = -KVM_EFAULT;
7482
7483 return ret;
7484 }
7485 #endif
7486
7487 /*
7488 * kvm_pv_kick_cpu_op: Kick a vcpu.
7489 *
7490 * @apicid - apicid of vcpu to be kicked.
7491 */
7492 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7493 {
7494 struct kvm_lapic_irq lapic_irq;
7495
7496 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7497 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7498 lapic_irq.level = 0;
7499 lapic_irq.dest_id = apicid;
7500 lapic_irq.msi_redir_hint = false;
7501
7502 lapic_irq.delivery_mode = APIC_DM_REMRD;
7503 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7504 }
7505
7506 bool kvm_apicv_activated(struct kvm *kvm)
7507 {
7508 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7509 }
7510 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7511
7512 void kvm_apicv_init(struct kvm *kvm, bool enable)
7513 {
7514 if (enable)
7515 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7516 &kvm->arch.apicv_inhibit_reasons);
7517 else
7518 set_bit(APICV_INHIBIT_REASON_DISABLE,
7519 &kvm->arch.apicv_inhibit_reasons);
7520 }
7521 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7522
7523 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7524 {
7525 struct kvm_vcpu *target = NULL;
7526 struct kvm_apic_map *map;
7527
7528 rcu_read_lock();
7529 map = rcu_dereference(kvm->arch.apic_map);
7530
7531 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7532 target = map->phys_map[dest_id]->vcpu;
7533
7534 rcu_read_unlock();
7535
7536 if (target && READ_ONCE(target->ready))
7537 kvm_vcpu_yield_to(target);
7538 }
7539
7540 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7541 {
7542 unsigned long nr, a0, a1, a2, a3, ret;
7543 int op_64_bit;
7544
7545 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7546 return kvm_hv_hypercall(vcpu);
7547
7548 nr = kvm_rax_read(vcpu);
7549 a0 = kvm_rbx_read(vcpu);
7550 a1 = kvm_rcx_read(vcpu);
7551 a2 = kvm_rdx_read(vcpu);
7552 a3 = kvm_rsi_read(vcpu);
7553
7554 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7555
7556 op_64_bit = is_64_bit_mode(vcpu);
7557 if (!op_64_bit) {
7558 nr &= 0xFFFFFFFF;
7559 a0 &= 0xFFFFFFFF;
7560 a1 &= 0xFFFFFFFF;
7561 a2 &= 0xFFFFFFFF;
7562 a3 &= 0xFFFFFFFF;
7563 }
7564
7565 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7566 ret = -KVM_EPERM;
7567 goto out;
7568 }
7569
7570 switch (nr) {
7571 case KVM_HC_VAPIC_POLL_IRQ:
7572 ret = 0;
7573 break;
7574 case KVM_HC_KICK_CPU:
7575 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7576 kvm_sched_yield(vcpu->kvm, a1);
7577 ret = 0;
7578 break;
7579 #ifdef CONFIG_X86_64
7580 case KVM_HC_CLOCK_PAIRING:
7581 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7582 break;
7583 #endif
7584 case KVM_HC_SEND_IPI:
7585 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7586 break;
7587 case KVM_HC_SCHED_YIELD:
7588 kvm_sched_yield(vcpu->kvm, a0);
7589 ret = 0;
7590 break;
7591 default:
7592 ret = -KVM_ENOSYS;
7593 break;
7594 }
7595 out:
7596 if (!op_64_bit)
7597 ret = (u32)ret;
7598 kvm_rax_write(vcpu, ret);
7599
7600 ++vcpu->stat.hypercalls;
7601 return kvm_skip_emulated_instruction(vcpu);
7602 }
7603 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7604
7605 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7606 {
7607 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7608 char instruction[3];
7609 unsigned long rip = kvm_rip_read(vcpu);
7610
7611 kvm_x86_ops.patch_hypercall(vcpu, instruction);
7612
7613 return emulator_write_emulated(ctxt, rip, instruction, 3,
7614 &ctxt->exception);
7615 }
7616
7617 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7618 {
7619 return vcpu->run->request_interrupt_window &&
7620 likely(!pic_in_kernel(vcpu->kvm));
7621 }
7622
7623 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7624 {
7625 struct kvm_run *kvm_run = vcpu->run;
7626
7627 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7628 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7629 kvm_run->cr8 = kvm_get_cr8(vcpu);
7630 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7631 kvm_run->ready_for_interrupt_injection =
7632 pic_in_kernel(vcpu->kvm) ||
7633 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7634 }
7635
7636 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7637 {
7638 int max_irr, tpr;
7639
7640 if (!kvm_x86_ops.update_cr8_intercept)
7641 return;
7642
7643 if (!lapic_in_kernel(vcpu))
7644 return;
7645
7646 if (vcpu->arch.apicv_active)
7647 return;
7648
7649 if (!vcpu->arch.apic->vapic_addr)
7650 max_irr = kvm_lapic_find_highest_irr(vcpu);
7651 else
7652 max_irr = -1;
7653
7654 if (max_irr != -1)
7655 max_irr >>= 4;
7656
7657 tpr = kvm_lapic_get_cr8(vcpu);
7658
7659 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7660 }
7661
7662 static int inject_pending_event(struct kvm_vcpu *vcpu)
7663 {
7664 int r;
7665
7666 /* try to reinject previous events if any */
7667
7668 if (vcpu->arch.exception.injected)
7669 kvm_x86_ops.queue_exception(vcpu);
7670 /*
7671 * Do not inject an NMI or interrupt if there is a pending
7672 * exception. Exceptions and interrupts are recognized at
7673 * instruction boundaries, i.e. the start of an instruction.
7674 * Trap-like exceptions, e.g. #DB, have higher priority than
7675 * NMIs and interrupts, i.e. traps are recognized before an
7676 * NMI/interrupt that's pending on the same instruction.
7677 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7678 * priority, but are only generated (pended) during instruction
7679 * execution, i.e. a pending fault-like exception means the
7680 * fault occurred on the *previous* instruction and must be
7681 * serviced prior to recognizing any new events in order to
7682 * fully complete the previous instruction.
7683 */
7684 else if (!vcpu->arch.exception.pending) {
7685 if (vcpu->arch.nmi_injected)
7686 kvm_x86_ops.set_nmi(vcpu);
7687 else if (vcpu->arch.interrupt.injected)
7688 kvm_x86_ops.set_irq(vcpu);
7689 }
7690
7691 /*
7692 * Call check_nested_events() even if we reinjected a previous event
7693 * in order for caller to determine if it should require immediate-exit
7694 * from L2 to L1 due to pending L1 events which require exit
7695 * from L2 to L1.
7696 */
7697 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7698 r = kvm_x86_ops.check_nested_events(vcpu);
7699 if (r != 0)
7700 return r;
7701 }
7702
7703 /* try to inject new event if pending */
7704 if (vcpu->arch.exception.pending) {
7705 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7706 vcpu->arch.exception.has_error_code,
7707 vcpu->arch.exception.error_code);
7708
7709 WARN_ON_ONCE(vcpu->arch.exception.injected);
7710 vcpu->arch.exception.pending = false;
7711 vcpu->arch.exception.injected = true;
7712
7713 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7714 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7715 X86_EFLAGS_RF);
7716
7717 if (vcpu->arch.exception.nr == DB_VECTOR) {
7718 /*
7719 * This code assumes that nSVM doesn't use
7720 * check_nested_events(). If it does, the
7721 * DR6/DR7 changes should happen before L1
7722 * gets a #VMEXIT for an intercepted #DB in
7723 * L2. (Under VMX, on the other hand, the
7724 * DR6/DR7 changes should not happen in the
7725 * event of a VM-exit to L1 for an intercepted
7726 * #DB in L2.)
7727 */
7728 kvm_deliver_exception_payload(vcpu);
7729 if (vcpu->arch.dr7 & DR7_GD) {
7730 vcpu->arch.dr7 &= ~DR7_GD;
7731 kvm_update_dr7(vcpu);
7732 }
7733 }
7734
7735 kvm_x86_ops.queue_exception(vcpu);
7736 }
7737
7738 /* Don't consider new event if we re-injected an event */
7739 if (kvm_event_needs_reinjection(vcpu))
7740 return 0;
7741
7742 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7743 kvm_x86_ops.smi_allowed(vcpu)) {
7744 vcpu->arch.smi_pending = false;
7745 ++vcpu->arch.smi_count;
7746 enter_smm(vcpu);
7747 } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) {
7748 --vcpu->arch.nmi_pending;
7749 vcpu->arch.nmi_injected = true;
7750 kvm_x86_ops.set_nmi(vcpu);
7751 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7752 /*
7753 * Because interrupts can be injected asynchronously, we are
7754 * calling check_nested_events again here to avoid a race condition.
7755 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7756 * proposal and current concerns. Perhaps we should be setting
7757 * KVM_REQ_EVENT only on certain events and not unconditionally?
7758 */
7759 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7760 r = kvm_x86_ops.check_nested_events(vcpu);
7761 if (r != 0)
7762 return r;
7763 }
7764 if (kvm_x86_ops.interrupt_allowed(vcpu)) {
7765 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7766 false);
7767 kvm_x86_ops.set_irq(vcpu);
7768 }
7769 }
7770
7771 return 0;
7772 }
7773
7774 static void process_nmi(struct kvm_vcpu *vcpu)
7775 {
7776 unsigned limit = 2;
7777
7778 /*
7779 * x86 is limited to one NMI running, and one NMI pending after it.
7780 * If an NMI is already in progress, limit further NMIs to just one.
7781 * Otherwise, allow two (and we'll inject the first one immediately).
7782 */
7783 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7784 limit = 1;
7785
7786 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7787 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7788 kvm_make_request(KVM_REQ_EVENT, vcpu);
7789 }
7790
7791 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7792 {
7793 u32 flags = 0;
7794 flags |= seg->g << 23;
7795 flags |= seg->db << 22;
7796 flags |= seg->l << 21;
7797 flags |= seg->avl << 20;
7798 flags |= seg->present << 15;
7799 flags |= seg->dpl << 13;
7800 flags |= seg->s << 12;
7801 flags |= seg->type << 8;
7802 return flags;
7803 }
7804
7805 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7806 {
7807 struct kvm_segment seg;
7808 int offset;
7809
7810 kvm_get_segment(vcpu, &seg, n);
7811 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7812
7813 if (n < 3)
7814 offset = 0x7f84 + n * 12;
7815 else
7816 offset = 0x7f2c + (n - 3) * 12;
7817
7818 put_smstate(u32, buf, offset + 8, seg.base);
7819 put_smstate(u32, buf, offset + 4, seg.limit);
7820 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7821 }
7822
7823 #ifdef CONFIG_X86_64
7824 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7825 {
7826 struct kvm_segment seg;
7827 int offset;
7828 u16 flags;
7829
7830 kvm_get_segment(vcpu, &seg, n);
7831 offset = 0x7e00 + n * 16;
7832
7833 flags = enter_smm_get_segment_flags(&seg) >> 8;
7834 put_smstate(u16, buf, offset, seg.selector);
7835 put_smstate(u16, buf, offset + 2, flags);
7836 put_smstate(u32, buf, offset + 4, seg.limit);
7837 put_smstate(u64, buf, offset + 8, seg.base);
7838 }
7839 #endif
7840
7841 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7842 {
7843 struct desc_ptr dt;
7844 struct kvm_segment seg;
7845 unsigned long val;
7846 int i;
7847
7848 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7849 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7850 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7851 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7852
7853 for (i = 0; i < 8; i++)
7854 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7855
7856 kvm_get_dr(vcpu, 6, &val);
7857 put_smstate(u32, buf, 0x7fcc, (u32)val);
7858 kvm_get_dr(vcpu, 7, &val);
7859 put_smstate(u32, buf, 0x7fc8, (u32)val);
7860
7861 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7862 put_smstate(u32, buf, 0x7fc4, seg.selector);
7863 put_smstate(u32, buf, 0x7f64, seg.base);
7864 put_smstate(u32, buf, 0x7f60, seg.limit);
7865 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7866
7867 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7868 put_smstate(u32, buf, 0x7fc0, seg.selector);
7869 put_smstate(u32, buf, 0x7f80, seg.base);
7870 put_smstate(u32, buf, 0x7f7c, seg.limit);
7871 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7872
7873 kvm_x86_ops.get_gdt(vcpu, &dt);
7874 put_smstate(u32, buf, 0x7f74, dt.address);
7875 put_smstate(u32, buf, 0x7f70, dt.size);
7876
7877 kvm_x86_ops.get_idt(vcpu, &dt);
7878 put_smstate(u32, buf, 0x7f58, dt.address);
7879 put_smstate(u32, buf, 0x7f54, dt.size);
7880
7881 for (i = 0; i < 6; i++)
7882 enter_smm_save_seg_32(vcpu, buf, i);
7883
7884 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7885
7886 /* revision id */
7887 put_smstate(u32, buf, 0x7efc, 0x00020000);
7888 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7889 }
7890
7891 #ifdef CONFIG_X86_64
7892 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7893 {
7894 struct desc_ptr dt;
7895 struct kvm_segment seg;
7896 unsigned long val;
7897 int i;
7898
7899 for (i = 0; i < 16; i++)
7900 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7901
7902 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7903 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7904
7905 kvm_get_dr(vcpu, 6, &val);
7906 put_smstate(u64, buf, 0x7f68, val);
7907 kvm_get_dr(vcpu, 7, &val);
7908 put_smstate(u64, buf, 0x7f60, val);
7909
7910 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7911 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7912 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7913
7914 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7915
7916 /* revision id */
7917 put_smstate(u32, buf, 0x7efc, 0x00020064);
7918
7919 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7920
7921 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7922 put_smstate(u16, buf, 0x7e90, seg.selector);
7923 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7924 put_smstate(u32, buf, 0x7e94, seg.limit);
7925 put_smstate(u64, buf, 0x7e98, seg.base);
7926
7927 kvm_x86_ops.get_idt(vcpu, &dt);
7928 put_smstate(u32, buf, 0x7e84, dt.size);
7929 put_smstate(u64, buf, 0x7e88, dt.address);
7930
7931 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7932 put_smstate(u16, buf, 0x7e70, seg.selector);
7933 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7934 put_smstate(u32, buf, 0x7e74, seg.limit);
7935 put_smstate(u64, buf, 0x7e78, seg.base);
7936
7937 kvm_x86_ops.get_gdt(vcpu, &dt);
7938 put_smstate(u32, buf, 0x7e64, dt.size);
7939 put_smstate(u64, buf, 0x7e68, dt.address);
7940
7941 for (i = 0; i < 6; i++)
7942 enter_smm_save_seg_64(vcpu, buf, i);
7943 }
7944 #endif
7945
7946 static void enter_smm(struct kvm_vcpu *vcpu)
7947 {
7948 struct kvm_segment cs, ds;
7949 struct desc_ptr dt;
7950 char buf[512];
7951 u32 cr0;
7952
7953 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7954 memset(buf, 0, 512);
7955 #ifdef CONFIG_X86_64
7956 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7957 enter_smm_save_state_64(vcpu, buf);
7958 else
7959 #endif
7960 enter_smm_save_state_32(vcpu, buf);
7961
7962 /*
7963 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7964 * vCPU state (e.g. leave guest mode) after we've saved the state into
7965 * the SMM state-save area.
7966 */
7967 kvm_x86_ops.pre_enter_smm(vcpu, buf);
7968
7969 vcpu->arch.hflags |= HF_SMM_MASK;
7970 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7971
7972 if (kvm_x86_ops.get_nmi_mask(vcpu))
7973 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7974 else
7975 kvm_x86_ops.set_nmi_mask(vcpu, true);
7976
7977 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7978 kvm_rip_write(vcpu, 0x8000);
7979
7980 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7981 kvm_x86_ops.set_cr0(vcpu, cr0);
7982 vcpu->arch.cr0 = cr0;
7983
7984 kvm_x86_ops.set_cr4(vcpu, 0);
7985
7986 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7987 dt.address = dt.size = 0;
7988 kvm_x86_ops.set_idt(vcpu, &dt);
7989
7990 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7991
7992 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7993 cs.base = vcpu->arch.smbase;
7994
7995 ds.selector = 0;
7996 ds.base = 0;
7997
7998 cs.limit = ds.limit = 0xffffffff;
7999 cs.type = ds.type = 0x3;
8000 cs.dpl = ds.dpl = 0;
8001 cs.db = ds.db = 0;
8002 cs.s = ds.s = 1;
8003 cs.l = ds.l = 0;
8004 cs.g = ds.g = 1;
8005 cs.avl = ds.avl = 0;
8006 cs.present = ds.present = 1;
8007 cs.unusable = ds.unusable = 0;
8008 cs.padding = ds.padding = 0;
8009
8010 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8011 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8012 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8013 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8014 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8015 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8016
8017 #ifdef CONFIG_X86_64
8018 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8019 kvm_x86_ops.set_efer(vcpu, 0);
8020 #endif
8021
8022 kvm_update_cpuid(vcpu);
8023 kvm_mmu_reset_context(vcpu);
8024 }
8025
8026 static void process_smi(struct kvm_vcpu *vcpu)
8027 {
8028 vcpu->arch.smi_pending = true;
8029 kvm_make_request(KVM_REQ_EVENT, vcpu);
8030 }
8031
8032 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8033 unsigned long *vcpu_bitmap)
8034 {
8035 cpumask_var_t cpus;
8036
8037 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8038
8039 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8040 vcpu_bitmap, cpus);
8041
8042 free_cpumask_var(cpus);
8043 }
8044
8045 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8046 {
8047 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8048 }
8049
8050 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8051 {
8052 if (!lapic_in_kernel(vcpu))
8053 return;
8054
8055 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8056 kvm_apic_update_apicv(vcpu);
8057 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8058 }
8059 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8060
8061 /*
8062 * NOTE: Do not hold any lock prior to calling this.
8063 *
8064 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8065 * locked, because it calls __x86_set_memory_region() which does
8066 * synchronize_srcu(&kvm->srcu).
8067 */
8068 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8069 {
8070 unsigned long old, new, expected;
8071
8072 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8073 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8074 return;
8075
8076 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8077 do {
8078 expected = new = old;
8079 if (activate)
8080 __clear_bit(bit, &new);
8081 else
8082 __set_bit(bit, &new);
8083 if (new == old)
8084 break;
8085 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8086 } while (old != expected);
8087
8088 if (!!old == !!new)
8089 return;
8090
8091 trace_kvm_apicv_update_request(activate, bit);
8092 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8093 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8094 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8095 }
8096 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8097
8098 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8099 {
8100 if (!kvm_apic_present(vcpu))
8101 return;
8102
8103 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8104
8105 if (irqchip_split(vcpu->kvm))
8106 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8107 else {
8108 if (vcpu->arch.apicv_active)
8109 kvm_x86_ops.sync_pir_to_irr(vcpu);
8110 if (ioapic_in_kernel(vcpu->kvm))
8111 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8112 }
8113
8114 if (is_guest_mode(vcpu))
8115 vcpu->arch.load_eoi_exitmap_pending = true;
8116 else
8117 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8118 }
8119
8120 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8121 {
8122 u64 eoi_exit_bitmap[4];
8123
8124 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8125 return;
8126
8127 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8128 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8129 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8130 }
8131
8132 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8133 unsigned long start, unsigned long end,
8134 bool blockable)
8135 {
8136 unsigned long apic_address;
8137
8138 /*
8139 * The physical address of apic access page is stored in the VMCS.
8140 * Update it when it becomes invalid.
8141 */
8142 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8143 if (start <= apic_address && apic_address < end)
8144 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8145
8146 return 0;
8147 }
8148
8149 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8150 {
8151 struct page *page = NULL;
8152
8153 if (!lapic_in_kernel(vcpu))
8154 return;
8155
8156 if (!kvm_x86_ops.set_apic_access_page_addr)
8157 return;
8158
8159 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8160 if (is_error_page(page))
8161 return;
8162 kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page));
8163
8164 /*
8165 * Do not pin apic access page in memory, the MMU notifier
8166 * will call us again if it is migrated or swapped out.
8167 */
8168 put_page(page);
8169 }
8170
8171 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8172 {
8173 smp_send_reschedule(vcpu->cpu);
8174 }
8175 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8176
8177 /*
8178 * Returns 1 to let vcpu_run() continue the guest execution loop without
8179 * exiting to the userspace. Otherwise, the value will be returned to the
8180 * userspace.
8181 */
8182 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8183 {
8184 int r;
8185 bool req_int_win =
8186 dm_request_for_irq_injection(vcpu) &&
8187 kvm_cpu_accept_dm_intr(vcpu);
8188 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8189
8190 bool req_immediate_exit = false;
8191
8192 if (kvm_request_pending(vcpu)) {
8193 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8194 if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) {
8195 r = 0;
8196 goto out;
8197 }
8198 }
8199 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8200 kvm_mmu_unload(vcpu);
8201 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8202 __kvm_migrate_timers(vcpu);
8203 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8204 kvm_gen_update_masterclock(vcpu->kvm);
8205 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8206 kvm_gen_kvmclock_update(vcpu);
8207 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8208 r = kvm_guest_time_update(vcpu);
8209 if (unlikely(r))
8210 goto out;
8211 }
8212 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8213 kvm_mmu_sync_roots(vcpu);
8214 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8215 kvm_mmu_load_pgd(vcpu);
8216 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8217 kvm_vcpu_flush_tlb(vcpu, true);
8218 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8219 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8220 r = 0;
8221 goto out;
8222 }
8223 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8224 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8225 vcpu->mmio_needed = 0;
8226 r = 0;
8227 goto out;
8228 }
8229 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8230 /* Page is swapped out. Do synthetic halt */
8231 vcpu->arch.apf.halted = true;
8232 r = 1;
8233 goto out;
8234 }
8235 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8236 record_steal_time(vcpu);
8237 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8238 process_smi(vcpu);
8239 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8240 process_nmi(vcpu);
8241 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8242 kvm_pmu_handle_event(vcpu);
8243 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8244 kvm_pmu_deliver_pmi(vcpu);
8245 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8246 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8247 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8248 vcpu->arch.ioapic_handled_vectors)) {
8249 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8250 vcpu->run->eoi.vector =
8251 vcpu->arch.pending_ioapic_eoi;
8252 r = 0;
8253 goto out;
8254 }
8255 }
8256 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8257 vcpu_scan_ioapic(vcpu);
8258 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8259 vcpu_load_eoi_exitmap(vcpu);
8260 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8261 kvm_vcpu_reload_apic_access_page(vcpu);
8262 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8263 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8264 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8265 r = 0;
8266 goto out;
8267 }
8268 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8269 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8270 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8271 r = 0;
8272 goto out;
8273 }
8274 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8275 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8276 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8277 r = 0;
8278 goto out;
8279 }
8280
8281 /*
8282 * KVM_REQ_HV_STIMER has to be processed after
8283 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8284 * depend on the guest clock being up-to-date
8285 */
8286 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8287 kvm_hv_process_stimers(vcpu);
8288 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8289 kvm_vcpu_update_apicv(vcpu);
8290 }
8291
8292 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8293 ++vcpu->stat.req_event;
8294 kvm_apic_accept_events(vcpu);
8295 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8296 r = 1;
8297 goto out;
8298 }
8299
8300 if (inject_pending_event(vcpu) != 0)
8301 req_immediate_exit = true;
8302 else {
8303 /* Enable SMI/NMI/IRQ window open exits if needed.
8304 *
8305 * SMIs have three cases:
8306 * 1) They can be nested, and then there is nothing to
8307 * do here because RSM will cause a vmexit anyway.
8308 * 2) There is an ISA-specific reason why SMI cannot be
8309 * injected, and the moment when this changes can be
8310 * intercepted.
8311 * 3) Or the SMI can be pending because
8312 * inject_pending_event has completed the injection
8313 * of an IRQ or NMI from the previous vmexit, and
8314 * then we request an immediate exit to inject the
8315 * SMI.
8316 */
8317 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8318 if (!kvm_x86_ops.enable_smi_window(vcpu))
8319 req_immediate_exit = true;
8320 if (vcpu->arch.nmi_pending)
8321 kvm_x86_ops.enable_nmi_window(vcpu);
8322 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8323 kvm_x86_ops.enable_irq_window(vcpu);
8324 WARN_ON(vcpu->arch.exception.pending);
8325 }
8326
8327 if (kvm_lapic_enabled(vcpu)) {
8328 update_cr8_intercept(vcpu);
8329 kvm_lapic_sync_to_vapic(vcpu);
8330 }
8331 }
8332
8333 r = kvm_mmu_reload(vcpu);
8334 if (unlikely(r)) {
8335 goto cancel_injection;
8336 }
8337
8338 preempt_disable();
8339
8340 kvm_x86_ops.prepare_guest_switch(vcpu);
8341
8342 /*
8343 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8344 * IPI are then delayed after guest entry, which ensures that they
8345 * result in virtual interrupt delivery.
8346 */
8347 local_irq_disable();
8348 vcpu->mode = IN_GUEST_MODE;
8349
8350 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8351
8352 /*
8353 * 1) We should set ->mode before checking ->requests. Please see
8354 * the comment in kvm_vcpu_exiting_guest_mode().
8355 *
8356 * 2) For APICv, we should set ->mode before checking PID.ON. This
8357 * pairs with the memory barrier implicit in pi_test_and_set_on
8358 * (see vmx_deliver_posted_interrupt).
8359 *
8360 * 3) This also orders the write to mode from any reads to the page
8361 * tables done while the VCPU is running. Please see the comment
8362 * in kvm_flush_remote_tlbs.
8363 */
8364 smp_mb__after_srcu_read_unlock();
8365
8366 /*
8367 * This handles the case where a posted interrupt was
8368 * notified with kvm_vcpu_kick.
8369 */
8370 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8371 kvm_x86_ops.sync_pir_to_irr(vcpu);
8372
8373 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8374 || need_resched() || signal_pending(current)) {
8375 vcpu->mode = OUTSIDE_GUEST_MODE;
8376 smp_wmb();
8377 local_irq_enable();
8378 preempt_enable();
8379 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8380 r = 1;
8381 goto cancel_injection;
8382 }
8383
8384 if (req_immediate_exit) {
8385 kvm_make_request(KVM_REQ_EVENT, vcpu);
8386 kvm_x86_ops.request_immediate_exit(vcpu);
8387 }
8388
8389 trace_kvm_entry(vcpu->vcpu_id);
8390 guest_enter_irqoff();
8391
8392 fpregs_assert_state_consistent();
8393 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8394 switch_fpu_return();
8395
8396 if (unlikely(vcpu->arch.switch_db_regs)) {
8397 set_debugreg(0, 7);
8398 set_debugreg(vcpu->arch.eff_db[0], 0);
8399 set_debugreg(vcpu->arch.eff_db[1], 1);
8400 set_debugreg(vcpu->arch.eff_db[2], 2);
8401 set_debugreg(vcpu->arch.eff_db[3], 3);
8402 set_debugreg(vcpu->arch.dr6, 6);
8403 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8404 }
8405
8406 kvm_x86_ops.run(vcpu);
8407
8408 /*
8409 * Do this here before restoring debug registers on the host. And
8410 * since we do this before handling the vmexit, a DR access vmexit
8411 * can (a) read the correct value of the debug registers, (b) set
8412 * KVM_DEBUGREG_WONT_EXIT again.
8413 */
8414 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8415 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8416 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8417 kvm_update_dr0123(vcpu);
8418 kvm_update_dr6(vcpu);
8419 kvm_update_dr7(vcpu);
8420 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8421 }
8422
8423 /*
8424 * If the guest has used debug registers, at least dr7
8425 * will be disabled while returning to the host.
8426 * If we don't have active breakpoints in the host, we don't
8427 * care about the messed up debug address registers. But if
8428 * we have some of them active, restore the old state.
8429 */
8430 if (hw_breakpoint_active())
8431 hw_breakpoint_restore();
8432
8433 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8434
8435 vcpu->mode = OUTSIDE_GUEST_MODE;
8436 smp_wmb();
8437
8438 kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath);
8439
8440 /*
8441 * Consume any pending interrupts, including the possible source of
8442 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8443 * An instruction is required after local_irq_enable() to fully unblock
8444 * interrupts on processors that implement an interrupt shadow, the
8445 * stat.exits increment will do nicely.
8446 */
8447 kvm_before_interrupt(vcpu);
8448 local_irq_enable();
8449 ++vcpu->stat.exits;
8450 local_irq_disable();
8451 kvm_after_interrupt(vcpu);
8452
8453 guest_exit_irqoff();
8454 if (lapic_in_kernel(vcpu)) {
8455 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8456 if (delta != S64_MIN) {
8457 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8458 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8459 }
8460 }
8461
8462 local_irq_enable();
8463 preempt_enable();
8464
8465 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8466
8467 /*
8468 * Profile KVM exit RIPs:
8469 */
8470 if (unlikely(prof_on == KVM_PROFILING)) {
8471 unsigned long rip = kvm_rip_read(vcpu);
8472 profile_hit(KVM_PROFILING, (void *)rip);
8473 }
8474
8475 if (unlikely(vcpu->arch.tsc_always_catchup))
8476 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8477
8478 if (vcpu->arch.apic_attention)
8479 kvm_lapic_sync_from_vapic(vcpu);
8480
8481 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8482 return r;
8483
8484 cancel_injection:
8485 kvm_x86_ops.cancel_injection(vcpu);
8486 if (unlikely(vcpu->arch.apic_attention))
8487 kvm_lapic_sync_from_vapic(vcpu);
8488 out:
8489 return r;
8490 }
8491
8492 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8493 {
8494 if (!kvm_arch_vcpu_runnable(vcpu) &&
8495 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8496 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8497 kvm_vcpu_block(vcpu);
8498 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8499
8500 if (kvm_x86_ops.post_block)
8501 kvm_x86_ops.post_block(vcpu);
8502
8503 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8504 return 1;
8505 }
8506
8507 kvm_apic_accept_events(vcpu);
8508 switch(vcpu->arch.mp_state) {
8509 case KVM_MP_STATE_HALTED:
8510 vcpu->arch.pv.pv_unhalted = false;
8511 vcpu->arch.mp_state =
8512 KVM_MP_STATE_RUNNABLE;
8513 /* fall through */
8514 case KVM_MP_STATE_RUNNABLE:
8515 vcpu->arch.apf.halted = false;
8516 break;
8517 case KVM_MP_STATE_INIT_RECEIVED:
8518 break;
8519 default:
8520 return -EINTR;
8521 }
8522 return 1;
8523 }
8524
8525 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8526 {
8527 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events)
8528 kvm_x86_ops.check_nested_events(vcpu);
8529
8530 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8531 !vcpu->arch.apf.halted);
8532 }
8533
8534 static int vcpu_run(struct kvm_vcpu *vcpu)
8535 {
8536 int r;
8537 struct kvm *kvm = vcpu->kvm;
8538
8539 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8540 vcpu->arch.l1tf_flush_l1d = true;
8541
8542 for (;;) {
8543 if (kvm_vcpu_running(vcpu)) {
8544 r = vcpu_enter_guest(vcpu);
8545 } else {
8546 r = vcpu_block(kvm, vcpu);
8547 }
8548
8549 if (r <= 0)
8550 break;
8551
8552 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8553 if (kvm_cpu_has_pending_timer(vcpu))
8554 kvm_inject_pending_timer_irqs(vcpu);
8555
8556 if (dm_request_for_irq_injection(vcpu) &&
8557 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8558 r = 0;
8559 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8560 ++vcpu->stat.request_irq_exits;
8561 break;
8562 }
8563
8564 kvm_check_async_pf_completion(vcpu);
8565
8566 if (signal_pending(current)) {
8567 r = -EINTR;
8568 vcpu->run->exit_reason = KVM_EXIT_INTR;
8569 ++vcpu->stat.signal_exits;
8570 break;
8571 }
8572 if (need_resched()) {
8573 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8574 cond_resched();
8575 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8576 }
8577 }
8578
8579 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8580
8581 return r;
8582 }
8583
8584 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8585 {
8586 int r;
8587
8588 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8589 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8590 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8591 return r;
8592 }
8593
8594 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8595 {
8596 BUG_ON(!vcpu->arch.pio.count);
8597
8598 return complete_emulated_io(vcpu);
8599 }
8600
8601 /*
8602 * Implements the following, as a state machine:
8603 *
8604 * read:
8605 * for each fragment
8606 * for each mmio piece in the fragment
8607 * write gpa, len
8608 * exit
8609 * copy data
8610 * execute insn
8611 *
8612 * write:
8613 * for each fragment
8614 * for each mmio piece in the fragment
8615 * write gpa, len
8616 * copy data
8617 * exit
8618 */
8619 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8620 {
8621 struct kvm_run *run = vcpu->run;
8622 struct kvm_mmio_fragment *frag;
8623 unsigned len;
8624
8625 BUG_ON(!vcpu->mmio_needed);
8626
8627 /* Complete previous fragment */
8628 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8629 len = min(8u, frag->len);
8630 if (!vcpu->mmio_is_write)
8631 memcpy(frag->data, run->mmio.data, len);
8632
8633 if (frag->len <= 8) {
8634 /* Switch to the next fragment. */
8635 frag++;
8636 vcpu->mmio_cur_fragment++;
8637 } else {
8638 /* Go forward to the next mmio piece. */
8639 frag->data += len;
8640 frag->gpa += len;
8641 frag->len -= len;
8642 }
8643
8644 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8645 vcpu->mmio_needed = 0;
8646
8647 /* FIXME: return into emulator if single-stepping. */
8648 if (vcpu->mmio_is_write)
8649 return 1;
8650 vcpu->mmio_read_completed = 1;
8651 return complete_emulated_io(vcpu);
8652 }
8653
8654 run->exit_reason = KVM_EXIT_MMIO;
8655 run->mmio.phys_addr = frag->gpa;
8656 if (vcpu->mmio_is_write)
8657 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8658 run->mmio.len = min(8u, frag->len);
8659 run->mmio.is_write = vcpu->mmio_is_write;
8660 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8661 return 0;
8662 }
8663
8664 static void kvm_save_current_fpu(struct fpu *fpu)
8665 {
8666 /*
8667 * If the target FPU state is not resident in the CPU registers, just
8668 * memcpy() from current, else save CPU state directly to the target.
8669 */
8670 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8671 memcpy(&fpu->state, &current->thread.fpu.state,
8672 fpu_kernel_xstate_size);
8673 else
8674 copy_fpregs_to_fpstate(fpu);
8675 }
8676
8677 /* Swap (qemu) user FPU context for the guest FPU context. */
8678 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8679 {
8680 fpregs_lock();
8681
8682 kvm_save_current_fpu(vcpu->arch.user_fpu);
8683
8684 /* PKRU is separately restored in kvm_x86_ops.run. */
8685 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8686 ~XFEATURE_MASK_PKRU);
8687
8688 fpregs_mark_activate();
8689 fpregs_unlock();
8690
8691 trace_kvm_fpu(1);
8692 }
8693
8694 /* When vcpu_run ends, restore user space FPU context. */
8695 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8696 {
8697 fpregs_lock();
8698
8699 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8700
8701 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8702
8703 fpregs_mark_activate();
8704 fpregs_unlock();
8705
8706 ++vcpu->stat.fpu_reload;
8707 trace_kvm_fpu(0);
8708 }
8709
8710 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8711 {
8712 int r;
8713
8714 vcpu_load(vcpu);
8715 kvm_sigset_activate(vcpu);
8716 kvm_load_guest_fpu(vcpu);
8717
8718 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8719 if (kvm_run->immediate_exit) {
8720 r = -EINTR;
8721 goto out;
8722 }
8723 kvm_vcpu_block(vcpu);
8724 kvm_apic_accept_events(vcpu);
8725 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8726 r = -EAGAIN;
8727 if (signal_pending(current)) {
8728 r = -EINTR;
8729 vcpu->run->exit_reason = KVM_EXIT_INTR;
8730 ++vcpu->stat.signal_exits;
8731 }
8732 goto out;
8733 }
8734
8735 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8736 r = -EINVAL;
8737 goto out;
8738 }
8739
8740 if (vcpu->run->kvm_dirty_regs) {
8741 r = sync_regs(vcpu);
8742 if (r != 0)
8743 goto out;
8744 }
8745
8746 /* re-sync apic's tpr */
8747 if (!lapic_in_kernel(vcpu)) {
8748 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8749 r = -EINVAL;
8750 goto out;
8751 }
8752 }
8753
8754 if (unlikely(vcpu->arch.complete_userspace_io)) {
8755 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8756 vcpu->arch.complete_userspace_io = NULL;
8757 r = cui(vcpu);
8758 if (r <= 0)
8759 goto out;
8760 } else
8761 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8762
8763 if (kvm_run->immediate_exit)
8764 r = -EINTR;
8765 else
8766 r = vcpu_run(vcpu);
8767
8768 out:
8769 kvm_put_guest_fpu(vcpu);
8770 if (vcpu->run->kvm_valid_regs)
8771 store_regs(vcpu);
8772 post_kvm_run_save(vcpu);
8773 kvm_sigset_deactivate(vcpu);
8774
8775 vcpu_put(vcpu);
8776 return r;
8777 }
8778
8779 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8780 {
8781 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8782 /*
8783 * We are here if userspace calls get_regs() in the middle of
8784 * instruction emulation. Registers state needs to be copied
8785 * back from emulation context to vcpu. Userspace shouldn't do
8786 * that usually, but some bad designed PV devices (vmware
8787 * backdoor interface) need this to work
8788 */
8789 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8790 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8791 }
8792 regs->rax = kvm_rax_read(vcpu);
8793 regs->rbx = kvm_rbx_read(vcpu);
8794 regs->rcx = kvm_rcx_read(vcpu);
8795 regs->rdx = kvm_rdx_read(vcpu);
8796 regs->rsi = kvm_rsi_read(vcpu);
8797 regs->rdi = kvm_rdi_read(vcpu);
8798 regs->rsp = kvm_rsp_read(vcpu);
8799 regs->rbp = kvm_rbp_read(vcpu);
8800 #ifdef CONFIG_X86_64
8801 regs->r8 = kvm_r8_read(vcpu);
8802 regs->r9 = kvm_r9_read(vcpu);
8803 regs->r10 = kvm_r10_read(vcpu);
8804 regs->r11 = kvm_r11_read(vcpu);
8805 regs->r12 = kvm_r12_read(vcpu);
8806 regs->r13 = kvm_r13_read(vcpu);
8807 regs->r14 = kvm_r14_read(vcpu);
8808 regs->r15 = kvm_r15_read(vcpu);
8809 #endif
8810
8811 regs->rip = kvm_rip_read(vcpu);
8812 regs->rflags = kvm_get_rflags(vcpu);
8813 }
8814
8815 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8816 {
8817 vcpu_load(vcpu);
8818 __get_regs(vcpu, regs);
8819 vcpu_put(vcpu);
8820 return 0;
8821 }
8822
8823 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8824 {
8825 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8826 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8827
8828 kvm_rax_write(vcpu, regs->rax);
8829 kvm_rbx_write(vcpu, regs->rbx);
8830 kvm_rcx_write(vcpu, regs->rcx);
8831 kvm_rdx_write(vcpu, regs->rdx);
8832 kvm_rsi_write(vcpu, regs->rsi);
8833 kvm_rdi_write(vcpu, regs->rdi);
8834 kvm_rsp_write(vcpu, regs->rsp);
8835 kvm_rbp_write(vcpu, regs->rbp);
8836 #ifdef CONFIG_X86_64
8837 kvm_r8_write(vcpu, regs->r8);
8838 kvm_r9_write(vcpu, regs->r9);
8839 kvm_r10_write(vcpu, regs->r10);
8840 kvm_r11_write(vcpu, regs->r11);
8841 kvm_r12_write(vcpu, regs->r12);
8842 kvm_r13_write(vcpu, regs->r13);
8843 kvm_r14_write(vcpu, regs->r14);
8844 kvm_r15_write(vcpu, regs->r15);
8845 #endif
8846
8847 kvm_rip_write(vcpu, regs->rip);
8848 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8849
8850 vcpu->arch.exception.pending = false;
8851
8852 kvm_make_request(KVM_REQ_EVENT, vcpu);
8853 }
8854
8855 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8856 {
8857 vcpu_load(vcpu);
8858 __set_regs(vcpu, regs);
8859 vcpu_put(vcpu);
8860 return 0;
8861 }
8862
8863 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8864 {
8865 struct kvm_segment cs;
8866
8867 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8868 *db = cs.db;
8869 *l = cs.l;
8870 }
8871 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8872
8873 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8874 {
8875 struct desc_ptr dt;
8876
8877 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8878 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8879 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8880 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8881 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8882 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8883
8884 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8885 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8886
8887 kvm_x86_ops.get_idt(vcpu, &dt);
8888 sregs->idt.limit = dt.size;
8889 sregs->idt.base = dt.address;
8890 kvm_x86_ops.get_gdt(vcpu, &dt);
8891 sregs->gdt.limit = dt.size;
8892 sregs->gdt.base = dt.address;
8893
8894 sregs->cr0 = kvm_read_cr0(vcpu);
8895 sregs->cr2 = vcpu->arch.cr2;
8896 sregs->cr3 = kvm_read_cr3(vcpu);
8897 sregs->cr4 = kvm_read_cr4(vcpu);
8898 sregs->cr8 = kvm_get_cr8(vcpu);
8899 sregs->efer = vcpu->arch.efer;
8900 sregs->apic_base = kvm_get_apic_base(vcpu);
8901
8902 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8903
8904 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8905 set_bit(vcpu->arch.interrupt.nr,
8906 (unsigned long *)sregs->interrupt_bitmap);
8907 }
8908
8909 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8910 struct kvm_sregs *sregs)
8911 {
8912 vcpu_load(vcpu);
8913 __get_sregs(vcpu, sregs);
8914 vcpu_put(vcpu);
8915 return 0;
8916 }
8917
8918 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8919 struct kvm_mp_state *mp_state)
8920 {
8921 vcpu_load(vcpu);
8922 if (kvm_mpx_supported())
8923 kvm_load_guest_fpu(vcpu);
8924
8925 kvm_apic_accept_events(vcpu);
8926 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8927 vcpu->arch.pv.pv_unhalted)
8928 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8929 else
8930 mp_state->mp_state = vcpu->arch.mp_state;
8931
8932 if (kvm_mpx_supported())
8933 kvm_put_guest_fpu(vcpu);
8934 vcpu_put(vcpu);
8935 return 0;
8936 }
8937
8938 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8939 struct kvm_mp_state *mp_state)
8940 {
8941 int ret = -EINVAL;
8942
8943 vcpu_load(vcpu);
8944
8945 if (!lapic_in_kernel(vcpu) &&
8946 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8947 goto out;
8948
8949 /*
8950 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8951 * INIT state; latched init should be reported using
8952 * KVM_SET_VCPU_EVENTS, so reject it here.
8953 */
8954 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8955 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8956 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8957 goto out;
8958
8959 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8960 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8961 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8962 } else
8963 vcpu->arch.mp_state = mp_state->mp_state;
8964 kvm_make_request(KVM_REQ_EVENT, vcpu);
8965
8966 ret = 0;
8967 out:
8968 vcpu_put(vcpu);
8969 return ret;
8970 }
8971
8972 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8973 int reason, bool has_error_code, u32 error_code)
8974 {
8975 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8976 int ret;
8977
8978 init_emulate_ctxt(vcpu);
8979
8980 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8981 has_error_code, error_code);
8982 if (ret) {
8983 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8984 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8985 vcpu->run->internal.ndata = 0;
8986 return 0;
8987 }
8988
8989 kvm_rip_write(vcpu, ctxt->eip);
8990 kvm_set_rflags(vcpu, ctxt->eflags);
8991 return 1;
8992 }
8993 EXPORT_SYMBOL_GPL(kvm_task_switch);
8994
8995 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8996 {
8997 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8998 /*
8999 * When EFER.LME and CR0.PG are set, the processor is in
9000 * 64-bit mode (though maybe in a 32-bit code segment).
9001 * CR4.PAE and EFER.LMA must be set.
9002 */
9003 if (!(sregs->cr4 & X86_CR4_PAE)
9004 || !(sregs->efer & EFER_LMA))
9005 return -EINVAL;
9006 } else {
9007 /*
9008 * Not in 64-bit mode: EFER.LMA is clear and the code
9009 * segment cannot be 64-bit.
9010 */
9011 if (sregs->efer & EFER_LMA || sregs->cs.l)
9012 return -EINVAL;
9013 }
9014
9015 return kvm_valid_cr4(vcpu, sregs->cr4);
9016 }
9017
9018 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9019 {
9020 struct msr_data apic_base_msr;
9021 int mmu_reset_needed = 0;
9022 int cpuid_update_needed = 0;
9023 int pending_vec, max_bits, idx;
9024 struct desc_ptr dt;
9025 int ret = -EINVAL;
9026
9027 if (kvm_valid_sregs(vcpu, sregs))
9028 goto out;
9029
9030 apic_base_msr.data = sregs->apic_base;
9031 apic_base_msr.host_initiated = true;
9032 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9033 goto out;
9034
9035 dt.size = sregs->idt.limit;
9036 dt.address = sregs->idt.base;
9037 kvm_x86_ops.set_idt(vcpu, &dt);
9038 dt.size = sregs->gdt.limit;
9039 dt.address = sregs->gdt.base;
9040 kvm_x86_ops.set_gdt(vcpu, &dt);
9041
9042 vcpu->arch.cr2 = sregs->cr2;
9043 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9044 vcpu->arch.cr3 = sregs->cr3;
9045 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9046
9047 kvm_set_cr8(vcpu, sregs->cr8);
9048
9049 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9050 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9051
9052 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9053 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9054 vcpu->arch.cr0 = sregs->cr0;
9055
9056 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9057 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9058 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9059 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9060 if (cpuid_update_needed)
9061 kvm_update_cpuid(vcpu);
9062
9063 idx = srcu_read_lock(&vcpu->kvm->srcu);
9064 if (is_pae_paging(vcpu)) {
9065 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9066 mmu_reset_needed = 1;
9067 }
9068 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9069
9070 if (mmu_reset_needed)
9071 kvm_mmu_reset_context(vcpu);
9072
9073 max_bits = KVM_NR_INTERRUPTS;
9074 pending_vec = find_first_bit(
9075 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9076 if (pending_vec < max_bits) {
9077 kvm_queue_interrupt(vcpu, pending_vec, false);
9078 pr_debug("Set back pending irq %d\n", pending_vec);
9079 }
9080
9081 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9082 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9083 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9084 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9085 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9086 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9087
9088 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9089 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9090
9091 update_cr8_intercept(vcpu);
9092
9093 /* Older userspace won't unhalt the vcpu on reset. */
9094 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9095 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9096 !is_protmode(vcpu))
9097 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9098
9099 kvm_make_request(KVM_REQ_EVENT, vcpu);
9100
9101 ret = 0;
9102 out:
9103 return ret;
9104 }
9105
9106 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9107 struct kvm_sregs *sregs)
9108 {
9109 int ret;
9110
9111 vcpu_load(vcpu);
9112 ret = __set_sregs(vcpu, sregs);
9113 vcpu_put(vcpu);
9114 return ret;
9115 }
9116
9117 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9118 struct kvm_guest_debug *dbg)
9119 {
9120 unsigned long rflags;
9121 int i, r;
9122
9123 vcpu_load(vcpu);
9124
9125 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9126 r = -EBUSY;
9127 if (vcpu->arch.exception.pending)
9128 goto out;
9129 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9130 kvm_queue_exception(vcpu, DB_VECTOR);
9131 else
9132 kvm_queue_exception(vcpu, BP_VECTOR);
9133 }
9134
9135 /*
9136 * Read rflags as long as potentially injected trace flags are still
9137 * filtered out.
9138 */
9139 rflags = kvm_get_rflags(vcpu);
9140
9141 vcpu->guest_debug = dbg->control;
9142 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9143 vcpu->guest_debug = 0;
9144
9145 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9146 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9147 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9148 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9149 } else {
9150 for (i = 0; i < KVM_NR_DB_REGS; i++)
9151 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9152 }
9153 kvm_update_dr7(vcpu);
9154
9155 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9156 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9157 get_segment_base(vcpu, VCPU_SREG_CS);
9158
9159 /*
9160 * Trigger an rflags update that will inject or remove the trace
9161 * flags.
9162 */
9163 kvm_set_rflags(vcpu, rflags);
9164
9165 kvm_x86_ops.update_bp_intercept(vcpu);
9166
9167 r = 0;
9168
9169 out:
9170 vcpu_put(vcpu);
9171 return r;
9172 }
9173
9174 /*
9175 * Translate a guest virtual address to a guest physical address.
9176 */
9177 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9178 struct kvm_translation *tr)
9179 {
9180 unsigned long vaddr = tr->linear_address;
9181 gpa_t gpa;
9182 int idx;
9183
9184 vcpu_load(vcpu);
9185
9186 idx = srcu_read_lock(&vcpu->kvm->srcu);
9187 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9188 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9189 tr->physical_address = gpa;
9190 tr->valid = gpa != UNMAPPED_GVA;
9191 tr->writeable = 1;
9192 tr->usermode = 0;
9193
9194 vcpu_put(vcpu);
9195 return 0;
9196 }
9197
9198 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9199 {
9200 struct fxregs_state *fxsave;
9201
9202 vcpu_load(vcpu);
9203
9204 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9205 memcpy(fpu->fpr, fxsave->st_space, 128);
9206 fpu->fcw = fxsave->cwd;
9207 fpu->fsw = fxsave->swd;
9208 fpu->ftwx = fxsave->twd;
9209 fpu->last_opcode = fxsave->fop;
9210 fpu->last_ip = fxsave->rip;
9211 fpu->last_dp = fxsave->rdp;
9212 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9213
9214 vcpu_put(vcpu);
9215 return 0;
9216 }
9217
9218 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9219 {
9220 struct fxregs_state *fxsave;
9221
9222 vcpu_load(vcpu);
9223
9224 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9225
9226 memcpy(fxsave->st_space, fpu->fpr, 128);
9227 fxsave->cwd = fpu->fcw;
9228 fxsave->swd = fpu->fsw;
9229 fxsave->twd = fpu->ftwx;
9230 fxsave->fop = fpu->last_opcode;
9231 fxsave->rip = fpu->last_ip;
9232 fxsave->rdp = fpu->last_dp;
9233 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9234
9235 vcpu_put(vcpu);
9236 return 0;
9237 }
9238
9239 static void store_regs(struct kvm_vcpu *vcpu)
9240 {
9241 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9242
9243 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9244 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9245
9246 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9247 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9248
9249 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9250 kvm_vcpu_ioctl_x86_get_vcpu_events(
9251 vcpu, &vcpu->run->s.regs.events);
9252 }
9253
9254 static int sync_regs(struct kvm_vcpu *vcpu)
9255 {
9256 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9257 return -EINVAL;
9258
9259 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9260 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9261 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9262 }
9263 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9264 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9265 return -EINVAL;
9266 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9267 }
9268 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9269 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9270 vcpu, &vcpu->run->s.regs.events))
9271 return -EINVAL;
9272 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9273 }
9274
9275 return 0;
9276 }
9277
9278 static void fx_init(struct kvm_vcpu *vcpu)
9279 {
9280 fpstate_init(&vcpu->arch.guest_fpu->state);
9281 if (boot_cpu_has(X86_FEATURE_XSAVES))
9282 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9283 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9284
9285 /*
9286 * Ensure guest xcr0 is valid for loading
9287 */
9288 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9289
9290 vcpu->arch.cr0 |= X86_CR0_ET;
9291 }
9292
9293 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9294 {
9295 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9296 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9297 "guest TSC will not be reliable\n");
9298
9299 return 0;
9300 }
9301
9302 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9303 {
9304 struct page *page;
9305 int r;
9306
9307 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9308 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9309 else
9310 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9311
9312 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9313
9314 r = kvm_mmu_create(vcpu);
9315 if (r < 0)
9316 return r;
9317
9318 if (irqchip_in_kernel(vcpu->kvm)) {
9319 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9320 if (r < 0)
9321 goto fail_mmu_destroy;
9322 if (kvm_apicv_activated(vcpu->kvm))
9323 vcpu->arch.apicv_active = true;
9324 } else
9325 static_key_slow_inc(&kvm_no_apic_vcpu);
9326
9327 r = -ENOMEM;
9328
9329 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9330 if (!page)
9331 goto fail_free_lapic;
9332 vcpu->arch.pio_data = page_address(page);
9333
9334 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9335 GFP_KERNEL_ACCOUNT);
9336 if (!vcpu->arch.mce_banks)
9337 goto fail_free_pio_data;
9338 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9339
9340 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9341 GFP_KERNEL_ACCOUNT))
9342 goto fail_free_mce_banks;
9343
9344 if (!alloc_emulate_ctxt(vcpu))
9345 goto free_wbinvd_dirty_mask;
9346
9347 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9348 GFP_KERNEL_ACCOUNT);
9349 if (!vcpu->arch.user_fpu) {
9350 pr_err("kvm: failed to allocate userspace's fpu\n");
9351 goto free_emulate_ctxt;
9352 }
9353
9354 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9355 GFP_KERNEL_ACCOUNT);
9356 if (!vcpu->arch.guest_fpu) {
9357 pr_err("kvm: failed to allocate vcpu's fpu\n");
9358 goto free_user_fpu;
9359 }
9360 fx_init(vcpu);
9361
9362 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9363
9364 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9365
9366 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9367
9368 kvm_async_pf_hash_reset(vcpu);
9369 kvm_pmu_init(vcpu);
9370
9371 vcpu->arch.pending_external_vector = -1;
9372 vcpu->arch.preempted_in_kernel = false;
9373
9374 kvm_hv_vcpu_init(vcpu);
9375
9376 r = kvm_x86_ops.vcpu_create(vcpu);
9377 if (r)
9378 goto free_guest_fpu;
9379
9380 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9381 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9382 kvm_vcpu_mtrr_init(vcpu);
9383 vcpu_load(vcpu);
9384 kvm_vcpu_reset(vcpu, false);
9385 kvm_init_mmu(vcpu, false);
9386 vcpu_put(vcpu);
9387 return 0;
9388
9389 free_guest_fpu:
9390 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9391 free_user_fpu:
9392 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9393 free_emulate_ctxt:
9394 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9395 free_wbinvd_dirty_mask:
9396 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9397 fail_free_mce_banks:
9398 kfree(vcpu->arch.mce_banks);
9399 fail_free_pio_data:
9400 free_page((unsigned long)vcpu->arch.pio_data);
9401 fail_free_lapic:
9402 kvm_free_lapic(vcpu);
9403 fail_mmu_destroy:
9404 kvm_mmu_destroy(vcpu);
9405 return r;
9406 }
9407
9408 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9409 {
9410 struct msr_data msr;
9411 struct kvm *kvm = vcpu->kvm;
9412
9413 kvm_hv_vcpu_postcreate(vcpu);
9414
9415 if (mutex_lock_killable(&vcpu->mutex))
9416 return;
9417 vcpu_load(vcpu);
9418 msr.data = 0x0;
9419 msr.index = MSR_IA32_TSC;
9420 msr.host_initiated = true;
9421 kvm_write_tsc(vcpu, &msr);
9422 vcpu_put(vcpu);
9423
9424 /* poll control enabled by default */
9425 vcpu->arch.msr_kvm_poll_control = 1;
9426
9427 mutex_unlock(&vcpu->mutex);
9428
9429 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9430 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9431 KVMCLOCK_SYNC_PERIOD);
9432 }
9433
9434 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9435 {
9436 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9437 int idx;
9438
9439 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9440
9441 kvmclock_reset(vcpu);
9442
9443 kvm_x86_ops.vcpu_free(vcpu);
9444
9445 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9446 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9447 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9448 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9449
9450 kvm_hv_vcpu_uninit(vcpu);
9451 kvm_pmu_destroy(vcpu);
9452 kfree(vcpu->arch.mce_banks);
9453 kvm_free_lapic(vcpu);
9454 idx = srcu_read_lock(&vcpu->kvm->srcu);
9455 kvm_mmu_destroy(vcpu);
9456 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9457 free_page((unsigned long)vcpu->arch.pio_data);
9458 if (!lapic_in_kernel(vcpu))
9459 static_key_slow_dec(&kvm_no_apic_vcpu);
9460 }
9461
9462 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9463 {
9464 kvm_lapic_reset(vcpu, init_event);
9465
9466 vcpu->arch.hflags = 0;
9467
9468 vcpu->arch.smi_pending = 0;
9469 vcpu->arch.smi_count = 0;
9470 atomic_set(&vcpu->arch.nmi_queued, 0);
9471 vcpu->arch.nmi_pending = 0;
9472 vcpu->arch.nmi_injected = false;
9473 kvm_clear_interrupt_queue(vcpu);
9474 kvm_clear_exception_queue(vcpu);
9475
9476 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9477 kvm_update_dr0123(vcpu);
9478 vcpu->arch.dr6 = DR6_INIT;
9479 kvm_update_dr6(vcpu);
9480 vcpu->arch.dr7 = DR7_FIXED_1;
9481 kvm_update_dr7(vcpu);
9482
9483 vcpu->arch.cr2 = 0;
9484
9485 kvm_make_request(KVM_REQ_EVENT, vcpu);
9486 vcpu->arch.apf.msr_val = 0;
9487 vcpu->arch.st.msr_val = 0;
9488
9489 kvmclock_reset(vcpu);
9490
9491 kvm_clear_async_pf_completion_queue(vcpu);
9492 kvm_async_pf_hash_reset(vcpu);
9493 vcpu->arch.apf.halted = false;
9494
9495 if (kvm_mpx_supported()) {
9496 void *mpx_state_buffer;
9497
9498 /*
9499 * To avoid have the INIT path from kvm_apic_has_events() that be
9500 * called with loaded FPU and does not let userspace fix the state.
9501 */
9502 if (init_event)
9503 kvm_put_guest_fpu(vcpu);
9504 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9505 XFEATURE_BNDREGS);
9506 if (mpx_state_buffer)
9507 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9508 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9509 XFEATURE_BNDCSR);
9510 if (mpx_state_buffer)
9511 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9512 if (init_event)
9513 kvm_load_guest_fpu(vcpu);
9514 }
9515
9516 if (!init_event) {
9517 kvm_pmu_reset(vcpu);
9518 vcpu->arch.smbase = 0x30000;
9519
9520 vcpu->arch.msr_misc_features_enables = 0;
9521
9522 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9523 }
9524
9525 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9526 vcpu->arch.regs_avail = ~0;
9527 vcpu->arch.regs_dirty = ~0;
9528
9529 vcpu->arch.ia32_xss = 0;
9530
9531 kvm_x86_ops.vcpu_reset(vcpu, init_event);
9532 }
9533
9534 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9535 {
9536 struct kvm_segment cs;
9537
9538 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9539 cs.selector = vector << 8;
9540 cs.base = vector << 12;
9541 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9542 kvm_rip_write(vcpu, 0);
9543 }
9544
9545 int kvm_arch_hardware_enable(void)
9546 {
9547 struct kvm *kvm;
9548 struct kvm_vcpu *vcpu;
9549 int i;
9550 int ret;
9551 u64 local_tsc;
9552 u64 max_tsc = 0;
9553 bool stable, backwards_tsc = false;
9554
9555 kvm_shared_msr_cpu_online();
9556 ret = kvm_x86_ops.hardware_enable();
9557 if (ret != 0)
9558 return ret;
9559
9560 local_tsc = rdtsc();
9561 stable = !kvm_check_tsc_unstable();
9562 list_for_each_entry(kvm, &vm_list, vm_list) {
9563 kvm_for_each_vcpu(i, vcpu, kvm) {
9564 if (!stable && vcpu->cpu == smp_processor_id())
9565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9566 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9567 backwards_tsc = true;
9568 if (vcpu->arch.last_host_tsc > max_tsc)
9569 max_tsc = vcpu->arch.last_host_tsc;
9570 }
9571 }
9572 }
9573
9574 /*
9575 * Sometimes, even reliable TSCs go backwards. This happens on
9576 * platforms that reset TSC during suspend or hibernate actions, but
9577 * maintain synchronization. We must compensate. Fortunately, we can
9578 * detect that condition here, which happens early in CPU bringup,
9579 * before any KVM threads can be running. Unfortunately, we can't
9580 * bring the TSCs fully up to date with real time, as we aren't yet far
9581 * enough into CPU bringup that we know how much real time has actually
9582 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9583 * variables that haven't been updated yet.
9584 *
9585 * So we simply find the maximum observed TSC above, then record the
9586 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9587 * the adjustment will be applied. Note that we accumulate
9588 * adjustments, in case multiple suspend cycles happen before some VCPU
9589 * gets a chance to run again. In the event that no KVM threads get a
9590 * chance to run, we will miss the entire elapsed period, as we'll have
9591 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9592 * loose cycle time. This isn't too big a deal, since the loss will be
9593 * uniform across all VCPUs (not to mention the scenario is extremely
9594 * unlikely). It is possible that a second hibernate recovery happens
9595 * much faster than a first, causing the observed TSC here to be
9596 * smaller; this would require additional padding adjustment, which is
9597 * why we set last_host_tsc to the local tsc observed here.
9598 *
9599 * N.B. - this code below runs only on platforms with reliable TSC,
9600 * as that is the only way backwards_tsc is set above. Also note
9601 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9602 * have the same delta_cyc adjustment applied if backwards_tsc
9603 * is detected. Note further, this adjustment is only done once,
9604 * as we reset last_host_tsc on all VCPUs to stop this from being
9605 * called multiple times (one for each physical CPU bringup).
9606 *
9607 * Platforms with unreliable TSCs don't have to deal with this, they
9608 * will be compensated by the logic in vcpu_load, which sets the TSC to
9609 * catchup mode. This will catchup all VCPUs to real time, but cannot
9610 * guarantee that they stay in perfect synchronization.
9611 */
9612 if (backwards_tsc) {
9613 u64 delta_cyc = max_tsc - local_tsc;
9614 list_for_each_entry(kvm, &vm_list, vm_list) {
9615 kvm->arch.backwards_tsc_observed = true;
9616 kvm_for_each_vcpu(i, vcpu, kvm) {
9617 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9618 vcpu->arch.last_host_tsc = local_tsc;
9619 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9620 }
9621
9622 /*
9623 * We have to disable TSC offset matching.. if you were
9624 * booting a VM while issuing an S4 host suspend....
9625 * you may have some problem. Solving this issue is
9626 * left as an exercise to the reader.
9627 */
9628 kvm->arch.last_tsc_nsec = 0;
9629 kvm->arch.last_tsc_write = 0;
9630 }
9631
9632 }
9633 return 0;
9634 }
9635
9636 void kvm_arch_hardware_disable(void)
9637 {
9638 kvm_x86_ops.hardware_disable();
9639 drop_user_return_notifiers();
9640 }
9641
9642 int kvm_arch_hardware_setup(void *opaque)
9643 {
9644 struct kvm_x86_init_ops *ops = opaque;
9645 int r;
9646
9647 rdmsrl_safe(MSR_EFER, &host_efer);
9648
9649 if (boot_cpu_has(X86_FEATURE_XSAVES))
9650 rdmsrl(MSR_IA32_XSS, host_xss);
9651
9652 r = ops->hardware_setup();
9653 if (r != 0)
9654 return r;
9655
9656 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9657
9658 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9659 supported_xss = 0;
9660
9661 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9662
9663 if (kvm_has_tsc_control) {
9664 /*
9665 * Make sure the user can only configure tsc_khz values that
9666 * fit into a signed integer.
9667 * A min value is not calculated because it will always
9668 * be 1 on all machines.
9669 */
9670 u64 max = min(0x7fffffffULL,
9671 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9672 kvm_max_guest_tsc_khz = max;
9673
9674 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9675 }
9676
9677 kvm_init_msr_list();
9678 return 0;
9679 }
9680
9681 void kvm_arch_hardware_unsetup(void)
9682 {
9683 kvm_x86_ops.hardware_unsetup();
9684 }
9685
9686 int kvm_arch_check_processor_compat(void *opaque)
9687 {
9688 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9689 struct kvm_x86_init_ops *ops = opaque;
9690
9691 WARN_ON(!irqs_disabled());
9692
9693 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9694 return -EIO;
9695
9696 return ops->check_processor_compatibility();
9697 }
9698
9699 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9700 {
9701 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9702 }
9703 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9704
9705 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9706 {
9707 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9708 }
9709
9710 struct static_key kvm_no_apic_vcpu __read_mostly;
9711 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9712
9713 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9714 {
9715 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9716
9717 vcpu->arch.l1tf_flush_l1d = true;
9718 if (pmu->version && unlikely(pmu->event_count)) {
9719 pmu->need_cleanup = true;
9720 kvm_make_request(KVM_REQ_PMU, vcpu);
9721 }
9722 kvm_x86_ops.sched_in(vcpu, cpu);
9723 }
9724
9725 void kvm_arch_free_vm(struct kvm *kvm)
9726 {
9727 kfree(kvm->arch.hyperv.hv_pa_pg);
9728 vfree(kvm);
9729 }
9730
9731
9732 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9733 {
9734 if (type)
9735 return -EINVAL;
9736
9737 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9738 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9739 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9740 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9741 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9742 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9743
9744 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9745 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9746 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9747 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9748 &kvm->arch.irq_sources_bitmap);
9749
9750 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9751 mutex_init(&kvm->arch.apic_map_lock);
9752 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9753
9754 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9755 pvclock_update_vm_gtod_copy(kvm);
9756
9757 kvm->arch.guest_can_read_msr_platform_info = true;
9758
9759 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9760 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9761
9762 kvm_hv_init_vm(kvm);
9763 kvm_page_track_init(kvm);
9764 kvm_mmu_init_vm(kvm);
9765
9766 return kvm_x86_ops.vm_init(kvm);
9767 }
9768
9769 int kvm_arch_post_init_vm(struct kvm *kvm)
9770 {
9771 return kvm_mmu_post_init_vm(kvm);
9772 }
9773
9774 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9775 {
9776 vcpu_load(vcpu);
9777 kvm_mmu_unload(vcpu);
9778 vcpu_put(vcpu);
9779 }
9780
9781 static void kvm_free_vcpus(struct kvm *kvm)
9782 {
9783 unsigned int i;
9784 struct kvm_vcpu *vcpu;
9785
9786 /*
9787 * Unpin any mmu pages first.
9788 */
9789 kvm_for_each_vcpu(i, vcpu, kvm) {
9790 kvm_clear_async_pf_completion_queue(vcpu);
9791 kvm_unload_vcpu_mmu(vcpu);
9792 }
9793 kvm_for_each_vcpu(i, vcpu, kvm)
9794 kvm_vcpu_destroy(vcpu);
9795
9796 mutex_lock(&kvm->lock);
9797 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9798 kvm->vcpus[i] = NULL;
9799
9800 atomic_set(&kvm->online_vcpus, 0);
9801 mutex_unlock(&kvm->lock);
9802 }
9803
9804 void kvm_arch_sync_events(struct kvm *kvm)
9805 {
9806 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9807 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9808 kvm_free_pit(kvm);
9809 }
9810
9811 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9812 {
9813 int i, r;
9814 unsigned long hva, uninitialized_var(old_npages);
9815 struct kvm_memslots *slots = kvm_memslots(kvm);
9816 struct kvm_memory_slot *slot;
9817
9818 /* Called with kvm->slots_lock held. */
9819 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9820 return -EINVAL;
9821
9822 slot = id_to_memslot(slots, id);
9823 if (size) {
9824 if (slot && slot->npages)
9825 return -EEXIST;
9826
9827 /*
9828 * MAP_SHARED to prevent internal slot pages from being moved
9829 * by fork()/COW.
9830 */
9831 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9832 MAP_SHARED | MAP_ANONYMOUS, 0);
9833 if (IS_ERR((void *)hva))
9834 return PTR_ERR((void *)hva);
9835 } else {
9836 if (!slot || !slot->npages)
9837 return 0;
9838
9839 /*
9840 * Stuff a non-canonical value to catch use-after-delete. This
9841 * ends up being 0 on 32-bit KVM, but there's no better
9842 * alternative.
9843 */
9844 hva = (unsigned long)(0xdeadull << 48);
9845 old_npages = slot->npages;
9846 }
9847
9848 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9849 struct kvm_userspace_memory_region m;
9850
9851 m.slot = id | (i << 16);
9852 m.flags = 0;
9853 m.guest_phys_addr = gpa;
9854 m.userspace_addr = hva;
9855 m.memory_size = size;
9856 r = __kvm_set_memory_region(kvm, &m);
9857 if (r < 0)
9858 return r;
9859 }
9860
9861 if (!size)
9862 vm_munmap(hva, old_npages * PAGE_SIZE);
9863
9864 return 0;
9865 }
9866 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9867
9868 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9869 {
9870 kvm_mmu_pre_destroy_vm(kvm);
9871 }
9872
9873 void kvm_arch_destroy_vm(struct kvm *kvm)
9874 {
9875 if (current->mm == kvm->mm) {
9876 /*
9877 * Free memory regions allocated on behalf of userspace,
9878 * unless the the memory map has changed due to process exit
9879 * or fd copying.
9880 */
9881 mutex_lock(&kvm->slots_lock);
9882 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9883 0, 0);
9884 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9885 0, 0);
9886 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9887 mutex_unlock(&kvm->slots_lock);
9888 }
9889 if (kvm_x86_ops.vm_destroy)
9890 kvm_x86_ops.vm_destroy(kvm);
9891 kvm_pic_destroy(kvm);
9892 kvm_ioapic_destroy(kvm);
9893 kvm_free_vcpus(kvm);
9894 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9895 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9896 kvm_mmu_uninit_vm(kvm);
9897 kvm_page_track_cleanup(kvm);
9898 kvm_hv_destroy_vm(kvm);
9899 }
9900
9901 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9902 {
9903 int i;
9904
9905 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9906 kvfree(slot->arch.rmap[i]);
9907 slot->arch.rmap[i] = NULL;
9908
9909 if (i == 0)
9910 continue;
9911
9912 kvfree(slot->arch.lpage_info[i - 1]);
9913 slot->arch.lpage_info[i - 1] = NULL;
9914 }
9915
9916 kvm_page_track_free_memslot(slot);
9917 }
9918
9919 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9920 unsigned long npages)
9921 {
9922 int i;
9923
9924 /*
9925 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
9926 * old arrays will be freed by __kvm_set_memory_region() if installing
9927 * the new memslot is successful.
9928 */
9929 memset(&slot->arch, 0, sizeof(slot->arch));
9930
9931 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9932 struct kvm_lpage_info *linfo;
9933 unsigned long ugfn;
9934 int lpages;
9935 int level = i + 1;
9936
9937 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9938 slot->base_gfn, level) + 1;
9939
9940 slot->arch.rmap[i] =
9941 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9942 GFP_KERNEL_ACCOUNT);
9943 if (!slot->arch.rmap[i])
9944 goto out_free;
9945 if (i == 0)
9946 continue;
9947
9948 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9949 if (!linfo)
9950 goto out_free;
9951
9952 slot->arch.lpage_info[i - 1] = linfo;
9953
9954 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9955 linfo[0].disallow_lpage = 1;
9956 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9957 linfo[lpages - 1].disallow_lpage = 1;
9958 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9959 /*
9960 * If the gfn and userspace address are not aligned wrt each
9961 * other, disable large page support for this slot.
9962 */
9963 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9964 unsigned long j;
9965
9966 for (j = 0; j < lpages; ++j)
9967 linfo[j].disallow_lpage = 1;
9968 }
9969 }
9970
9971 if (kvm_page_track_create_memslot(slot, npages))
9972 goto out_free;
9973
9974 return 0;
9975
9976 out_free:
9977 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9978 kvfree(slot->arch.rmap[i]);
9979 slot->arch.rmap[i] = NULL;
9980 if (i == 0)
9981 continue;
9982
9983 kvfree(slot->arch.lpage_info[i - 1]);
9984 slot->arch.lpage_info[i - 1] = NULL;
9985 }
9986 return -ENOMEM;
9987 }
9988
9989 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9990 {
9991 struct kvm_vcpu *vcpu;
9992 int i;
9993
9994 /*
9995 * memslots->generation has been incremented.
9996 * mmio generation may have reached its maximum value.
9997 */
9998 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9999
10000 /* Force re-initialization of steal_time cache */
10001 kvm_for_each_vcpu(i, vcpu, kvm)
10002 kvm_vcpu_kick(vcpu);
10003 }
10004
10005 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10006 struct kvm_memory_slot *memslot,
10007 const struct kvm_userspace_memory_region *mem,
10008 enum kvm_mr_change change)
10009 {
10010 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10011 return kvm_alloc_memslot_metadata(memslot,
10012 mem->memory_size >> PAGE_SHIFT);
10013 return 0;
10014 }
10015
10016 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10017 struct kvm_memory_slot *new)
10018 {
10019 /* Still write protect RO slot */
10020 if (new->flags & KVM_MEM_READONLY) {
10021 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
10022 return;
10023 }
10024
10025 /*
10026 * Call kvm_x86_ops dirty logging hooks when they are valid.
10027 *
10028 * kvm_x86_ops.slot_disable_log_dirty is called when:
10029 *
10030 * - KVM_MR_CREATE with dirty logging is disabled
10031 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10032 *
10033 * The reason is, in case of PML, we need to set D-bit for any slots
10034 * with dirty logging disabled in order to eliminate unnecessary GPA
10035 * logging in PML buffer (and potential PML buffer full VMEXIT). This
10036 * guarantees leaving PML enabled during guest's lifetime won't have
10037 * any additional overhead from PML when guest is running with dirty
10038 * logging disabled for memory slots.
10039 *
10040 * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot
10041 * to dirty logging mode.
10042 *
10043 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10044 *
10045 * In case of write protect:
10046 *
10047 * Write protect all pages for dirty logging.
10048 *
10049 * All the sptes including the large sptes which point to this
10050 * slot are set to readonly. We can not create any new large
10051 * spte on this slot until the end of the logging.
10052 *
10053 * See the comments in fast_page_fault().
10054 */
10055 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10056 if (kvm_x86_ops.slot_enable_log_dirty) {
10057 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10058 } else {
10059 int level =
10060 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10061 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
10062
10063 /*
10064 * If we're with initial-all-set, we don't need
10065 * to write protect any small page because
10066 * they're reported as dirty already. However
10067 * we still need to write-protect huge pages
10068 * so that the page split can happen lazily on
10069 * the first write to the huge page.
10070 */
10071 kvm_mmu_slot_remove_write_access(kvm, new, level);
10072 }
10073 } else {
10074 if (kvm_x86_ops.slot_disable_log_dirty)
10075 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10076 }
10077 }
10078
10079 void kvm_arch_commit_memory_region(struct kvm *kvm,
10080 const struct kvm_userspace_memory_region *mem,
10081 struct kvm_memory_slot *old,
10082 const struct kvm_memory_slot *new,
10083 enum kvm_mr_change change)
10084 {
10085 if (!kvm->arch.n_requested_mmu_pages)
10086 kvm_mmu_change_mmu_pages(kvm,
10087 kvm_mmu_calculate_default_mmu_pages(kvm));
10088
10089 /*
10090 * Dirty logging tracks sptes in 4k granularity, meaning that large
10091 * sptes have to be split. If live migration is successful, the guest
10092 * in the source machine will be destroyed and large sptes will be
10093 * created in the destination. However, if the guest continues to run
10094 * in the source machine (for example if live migration fails), small
10095 * sptes will remain around and cause bad performance.
10096 *
10097 * Scan sptes if dirty logging has been stopped, dropping those
10098 * which can be collapsed into a single large-page spte. Later
10099 * page faults will create the large-page sptes.
10100 *
10101 * There is no need to do this in any of the following cases:
10102 * CREATE: No dirty mappings will already exist.
10103 * MOVE/DELETE: The old mappings will already have been cleaned up by
10104 * kvm_arch_flush_shadow_memslot()
10105 */
10106 if (change == KVM_MR_FLAGS_ONLY &&
10107 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10108 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10109 kvm_mmu_zap_collapsible_sptes(kvm, new);
10110
10111 /*
10112 * Set up write protection and/or dirty logging for the new slot.
10113 *
10114 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10115 * been zapped so no dirty logging staff is needed for old slot. For
10116 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10117 * new and it's also covered when dealing with the new slot.
10118 *
10119 * FIXME: const-ify all uses of struct kvm_memory_slot.
10120 */
10121 if (change != KVM_MR_DELETE)
10122 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10123
10124 /* Free the arrays associated with the old memslot. */
10125 if (change == KVM_MR_MOVE)
10126 kvm_arch_free_memslot(kvm, old);
10127 }
10128
10129 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10130 {
10131 kvm_mmu_zap_all(kvm);
10132 }
10133
10134 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10135 struct kvm_memory_slot *slot)
10136 {
10137 kvm_page_track_flush_slot(kvm, slot);
10138 }
10139
10140 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10141 {
10142 return (is_guest_mode(vcpu) &&
10143 kvm_x86_ops.guest_apic_has_interrupt &&
10144 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10145 }
10146
10147 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10148 {
10149 if (!list_empty_careful(&vcpu->async_pf.done))
10150 return true;
10151
10152 if (kvm_apic_has_events(vcpu))
10153 return true;
10154
10155 if (vcpu->arch.pv.pv_unhalted)
10156 return true;
10157
10158 if (vcpu->arch.exception.pending)
10159 return true;
10160
10161 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10162 (vcpu->arch.nmi_pending &&
10163 kvm_x86_ops.nmi_allowed(vcpu)))
10164 return true;
10165
10166 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10167 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10168 return true;
10169
10170 if (kvm_arch_interrupt_allowed(vcpu) &&
10171 (kvm_cpu_has_interrupt(vcpu) ||
10172 kvm_guest_apic_has_interrupt(vcpu)))
10173 return true;
10174
10175 if (kvm_hv_has_stimer_pending(vcpu))
10176 return true;
10177
10178 return false;
10179 }
10180
10181 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10182 {
10183 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10184 }
10185
10186 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10187 {
10188 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10189 return true;
10190
10191 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10192 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10193 kvm_test_request(KVM_REQ_EVENT, vcpu))
10194 return true;
10195
10196 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10197 return true;
10198
10199 return false;
10200 }
10201
10202 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10203 {
10204 return vcpu->arch.preempted_in_kernel;
10205 }
10206
10207 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10208 {
10209 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10210 }
10211
10212 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10213 {
10214 return kvm_x86_ops.interrupt_allowed(vcpu);
10215 }
10216
10217 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10218 {
10219 if (is_64_bit_mode(vcpu))
10220 return kvm_rip_read(vcpu);
10221 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10222 kvm_rip_read(vcpu));
10223 }
10224 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10225
10226 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10227 {
10228 return kvm_get_linear_rip(vcpu) == linear_rip;
10229 }
10230 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10231
10232 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10233 {
10234 unsigned long rflags;
10235
10236 rflags = kvm_x86_ops.get_rflags(vcpu);
10237 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10238 rflags &= ~X86_EFLAGS_TF;
10239 return rflags;
10240 }
10241 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10242
10243 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10244 {
10245 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10246 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10247 rflags |= X86_EFLAGS_TF;
10248 kvm_x86_ops.set_rflags(vcpu, rflags);
10249 }
10250
10251 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10252 {
10253 __kvm_set_rflags(vcpu, rflags);
10254 kvm_make_request(KVM_REQ_EVENT, vcpu);
10255 }
10256 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10257
10258 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10259 {
10260 int r;
10261
10262 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10263 work->wakeup_all)
10264 return;
10265
10266 r = kvm_mmu_reload(vcpu);
10267 if (unlikely(r))
10268 return;
10269
10270 if (!vcpu->arch.mmu->direct_map &&
10271 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10272 return;
10273
10274 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10275 }
10276
10277 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10278 {
10279 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10280 }
10281
10282 static inline u32 kvm_async_pf_next_probe(u32 key)
10283 {
10284 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10285 }
10286
10287 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10288 {
10289 u32 key = kvm_async_pf_hash_fn(gfn);
10290
10291 while (vcpu->arch.apf.gfns[key] != ~0)
10292 key = kvm_async_pf_next_probe(key);
10293
10294 vcpu->arch.apf.gfns[key] = gfn;
10295 }
10296
10297 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10298 {
10299 int i;
10300 u32 key = kvm_async_pf_hash_fn(gfn);
10301
10302 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10303 (vcpu->arch.apf.gfns[key] != gfn &&
10304 vcpu->arch.apf.gfns[key] != ~0); i++)
10305 key = kvm_async_pf_next_probe(key);
10306
10307 return key;
10308 }
10309
10310 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10311 {
10312 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10313 }
10314
10315 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10316 {
10317 u32 i, j, k;
10318
10319 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10320 while (true) {
10321 vcpu->arch.apf.gfns[i] = ~0;
10322 do {
10323 j = kvm_async_pf_next_probe(j);
10324 if (vcpu->arch.apf.gfns[j] == ~0)
10325 return;
10326 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10327 /*
10328 * k lies cyclically in ]i,j]
10329 * | i.k.j |
10330 * |....j i.k.| or |.k..j i...|
10331 */
10332 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10333 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10334 i = j;
10335 }
10336 }
10337
10338 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10339 {
10340
10341 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10342 sizeof(val));
10343 }
10344
10345 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10346 {
10347
10348 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10349 sizeof(u32));
10350 }
10351
10352 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10353 {
10354 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10355 return false;
10356
10357 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10358 (vcpu->arch.apf.send_user_only &&
10359 kvm_x86_ops.get_cpl(vcpu) == 0))
10360 return false;
10361
10362 return true;
10363 }
10364
10365 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10366 {
10367 if (unlikely(!lapic_in_kernel(vcpu) ||
10368 kvm_event_needs_reinjection(vcpu) ||
10369 vcpu->arch.exception.pending))
10370 return false;
10371
10372 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10373 return false;
10374
10375 /*
10376 * If interrupts are off we cannot even use an artificial
10377 * halt state.
10378 */
10379 return kvm_x86_ops.interrupt_allowed(vcpu);
10380 }
10381
10382 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10383 struct kvm_async_pf *work)
10384 {
10385 struct x86_exception fault;
10386
10387 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10388 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10389
10390 if (kvm_can_deliver_async_pf(vcpu) &&
10391 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10392 fault.vector = PF_VECTOR;
10393 fault.error_code_valid = true;
10394 fault.error_code = 0;
10395 fault.nested_page_fault = false;
10396 fault.address = work->arch.token;
10397 fault.async_page_fault = true;
10398 kvm_inject_page_fault(vcpu, &fault);
10399 } else {
10400 /*
10401 * It is not possible to deliver a paravirtualized asynchronous
10402 * page fault, but putting the guest in an artificial halt state
10403 * can be beneficial nevertheless: if an interrupt arrives, we
10404 * can deliver it timely and perhaps the guest will schedule
10405 * another process. When the instruction that triggered a page
10406 * fault is retried, hopefully the page will be ready in the host.
10407 */
10408 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10409 }
10410 }
10411
10412 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10413 struct kvm_async_pf *work)
10414 {
10415 struct x86_exception fault;
10416 u32 val;
10417
10418 if (work->wakeup_all)
10419 work->arch.token = ~0; /* broadcast wakeup */
10420 else
10421 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10422 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10423
10424 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10425 !apf_get_user(vcpu, &val)) {
10426 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10427 vcpu->arch.exception.pending &&
10428 vcpu->arch.exception.nr == PF_VECTOR &&
10429 !apf_put_user(vcpu, 0)) {
10430 vcpu->arch.exception.injected = false;
10431 vcpu->arch.exception.pending = false;
10432 vcpu->arch.exception.nr = 0;
10433 vcpu->arch.exception.has_error_code = false;
10434 vcpu->arch.exception.error_code = 0;
10435 vcpu->arch.exception.has_payload = false;
10436 vcpu->arch.exception.payload = 0;
10437 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10438 fault.vector = PF_VECTOR;
10439 fault.error_code_valid = true;
10440 fault.error_code = 0;
10441 fault.nested_page_fault = false;
10442 fault.address = work->arch.token;
10443 fault.async_page_fault = true;
10444 kvm_inject_page_fault(vcpu, &fault);
10445 }
10446 }
10447 vcpu->arch.apf.halted = false;
10448 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10449 }
10450
10451 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10452 {
10453 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10454 return true;
10455 else
10456 return kvm_can_do_async_pf(vcpu);
10457 }
10458
10459 void kvm_arch_start_assignment(struct kvm *kvm)
10460 {
10461 atomic_inc(&kvm->arch.assigned_device_count);
10462 }
10463 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10464
10465 void kvm_arch_end_assignment(struct kvm *kvm)
10466 {
10467 atomic_dec(&kvm->arch.assigned_device_count);
10468 }
10469 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10470
10471 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10472 {
10473 return atomic_read(&kvm->arch.assigned_device_count);
10474 }
10475 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10476
10477 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10478 {
10479 atomic_inc(&kvm->arch.noncoherent_dma_count);
10480 }
10481 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10482
10483 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10484 {
10485 atomic_dec(&kvm->arch.noncoherent_dma_count);
10486 }
10487 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10488
10489 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10490 {
10491 return atomic_read(&kvm->arch.noncoherent_dma_count);
10492 }
10493 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10494
10495 bool kvm_arch_has_irq_bypass(void)
10496 {
10497 return true;
10498 }
10499
10500 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10501 struct irq_bypass_producer *prod)
10502 {
10503 struct kvm_kernel_irqfd *irqfd =
10504 container_of(cons, struct kvm_kernel_irqfd, consumer);
10505
10506 irqfd->producer = prod;
10507
10508 return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10509 prod->irq, irqfd->gsi, 1);
10510 }
10511
10512 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10513 struct irq_bypass_producer *prod)
10514 {
10515 int ret;
10516 struct kvm_kernel_irqfd *irqfd =
10517 container_of(cons, struct kvm_kernel_irqfd, consumer);
10518
10519 WARN_ON(irqfd->producer != prod);
10520 irqfd->producer = NULL;
10521
10522 /*
10523 * When producer of consumer is unregistered, we change back to
10524 * remapped mode, so we can re-use the current implementation
10525 * when the irq is masked/disabled or the consumer side (KVM
10526 * int this case doesn't want to receive the interrupts.
10527 */
10528 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10529 if (ret)
10530 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10531 " fails: %d\n", irqfd->consumer.token, ret);
10532 }
10533
10534 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10535 uint32_t guest_irq, bool set)
10536 {
10537 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10538 }
10539
10540 bool kvm_vector_hashing_enabled(void)
10541 {
10542 return vector_hashing;
10543 }
10544
10545 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10546 {
10547 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10548 }
10549 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10550
10551 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10552 {
10553 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10554
10555 /* The STIBP bit doesn't fault even if it's not advertised */
10556 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10557 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10558 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10559 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10560 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10561 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10562
10563 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10564 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10565 bits &= ~SPEC_CTRL_SSBD;
10566 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10567 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10568 bits &= ~SPEC_CTRL_SSBD;
10569
10570 return bits;
10571 }
10572 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10573
10574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
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