]> git.ipfire.org Git - thirdparty/kernel/linux.git/blob - arch/x86/kvm/x86.c
projects / thirdparty / kernel / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'v4.9-rc1' into x86/fpu, to resolve conflict
[thirdparty/kernel/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68
69 #define CREATE_TRACE_POINTS
70 #include "trace.h"
71
72 #define MAX_IO_MSRS 256
73 #define KVM_MAX_MCE_BANKS 32
74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
76
77 #define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
80 /* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84 #ifdef CONFIG_X86_64
85 static
86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
87 #else
88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #endif
90
91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
93
94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
96
97 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
98 static void process_nmi(struct kvm_vcpu *vcpu);
99 static void enter_smm(struct kvm_vcpu *vcpu);
100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
101
102 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
103 EXPORT_SYMBOL_GPL(kvm_x86_ops);
104
105 static bool __read_mostly ignore_msrs = 0;
106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
107
108 unsigned int min_timer_period_us = 500;
109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
111 static bool __read_mostly kvmclock_periodic_sync = true;
112 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
114 bool __read_mostly kvm_has_tsc_control;
115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
116 u32 __read_mostly kvm_max_guest_tsc_khz;
117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120 u64 __read_mostly kvm_max_tsc_scaling_ratio;
121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
122 u64 __read_mostly kvm_default_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
124
125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
126 static u32 __read_mostly tsc_tolerance_ppm = 250;
127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
130 unsigned int __read_mostly lapic_timer_advance_ns = 0;
131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
133 static bool __read_mostly vector_hashing = true;
134 module_param(vector_hashing, bool, S_IRUGO);
135
136 static bool __read_mostly backwards_tsc_observed = false;
137
138 #define KVM_NR_SHARED_MSRS 16
139
140 struct kvm_shared_msrs_global {
141 int nr;
142 u32 msrs[KVM_NR_SHARED_MSRS];
143 };
144
145 struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
152 };
153
154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
155 static struct kvm_shared_msrs __percpu *shared_msrs;
156
157 struct kvm_stats_debugfs_item debugfs_entries[] = {
158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
168 { "halt_exits", VCPU_STAT(halt_exits) },
169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
173 { "hypercalls", VCPU_STAT(hypercalls) },
174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
181 { "irq_injections", VCPU_STAT(irq_injections) },
182 { "nmi_injections", VCPU_STAT(nmi_injections) },
183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
190 { "mmu_unsync", VM_STAT(mmu_unsync) },
191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
192 { "largepages", VM_STAT(lpages) },
193 { NULL }
194 };
195
196 u64 __read_mostly host_xcr0;
197
198 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
199
200 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201 {
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205 }
206
207 static void kvm_on_user_return(struct user_return_notifier *urn)
208 {
209 unsigned slot;
210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
212 struct kvm_shared_msr_values *values;
213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223 }
224
225 static void shared_msr_update(unsigned slot, u32 msr)
226 {
227 u64 value;
228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
230
231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240 }
241
242 void kvm_define_shared_msr(unsigned slot, u32 msr)
243 {
244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
245 shared_msrs_global.msrs[slot] = msr;
246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
248 }
249 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251 static void kvm_shared_msr_cpu_online(void)
252 {
253 unsigned i;
254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
256 shared_msr_update(i, shared_msrs_global.msrs[i]);
257 }
258
259 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
260 {
261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
263 int err;
264
265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
266 return 0;
267 smsr->values[slot].curr = value;
268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
277 return 0;
278 }
279 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
281 static void drop_user_return_notifiers(void)
282 {
283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288 }
289
290 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291 {
292 return vcpu->arch.apic_base;
293 }
294 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
296 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297 {
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
316 }
317 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
319 asmlinkage __visible void kvm_spurious_fault(void)
320 {
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323 }
324 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
326 #define EXCPT_BENIGN 0
327 #define EXCPT_CONTRIBUTORY 1
328 #define EXCPT_PF 2
329
330 static int exception_class(int vector)
331 {
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345 }
346
347 #define EXCPT_FAULT 0
348 #define EXCPT_TRAP 1
349 #define EXCPT_ABORT 2
350 #define EXCPT_INTERRUPT 3
351
352 static int exception_type(int vector)
353 {
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370 }
371
372 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
375 {
376 u32 prev_nr;
377 int class1, class2;
378
379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
381 if (!vcpu->arch.exception.pending) {
382 queue:
383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
389 vcpu->arch.exception.reinject = reinject;
390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414 }
415
416 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417 {
418 kvm_multiple_exception(vcpu, nr, false, 0, false);
419 }
420 EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
422 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423 {
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425 }
426 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
428 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
429 {
430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434 }
435 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
436
437 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
438 {
439 ++vcpu->stat.pf_guest;
440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
442 }
443 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
444
445 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
446 {
447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
449 else
450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
451
452 return fault->nested_page_fault;
453 }
454
455 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456 {
457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
459 }
460 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
462 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463 {
464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
465 }
466 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
468 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469 {
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471 }
472 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
474 /*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
479 {
480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
484 }
485 EXPORT_SYMBOL_GPL(kvm_require_cpl);
486
487 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488 {
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494 }
495 EXPORT_SYMBOL_GPL(kvm_require_dr);
496
497 /*
498 * This function will be used to read from the physical memory of the currently
499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
500 * can read from guest physical or from the guest's guest physical memory.
501 */
502 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505 {
506 struct x86_exception exception;
507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
518 }
519 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
521 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
522 void *data, int offset, int len, u32 access)
523 {
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526 }
527
528 /*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
531 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
532 {
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
538
539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
547 if ((pdpte[i] & PT_PRESENT_MASK) &&
548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
561 out:
562
563 return ret;
564 }
565 EXPORT_SYMBOL_GPL(load_pdptrs);
566
567 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568 {
569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
570 bool changed = true;
571 int offset;
572 gfn_t gfn;
573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
586 if (r < 0)
587 goto out;
588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
589 out:
590
591 return changed;
592 }
593
594 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
595 {
596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
598
599 cr0 |= X86_CR0_ET;
600
601 #ifdef CONFIG_X86_64
602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
604 #endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
607
608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
610
611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615 #ifdef CONFIG_X86_64
616 if ((vcpu->arch.efer & EFER_LME)) {
617 int cs_db, cs_l;
618
619 if (!is_pae(vcpu))
620 return 1;
621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
622 if (cs_l)
623 return 1;
624 } else
625 #endif
626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
627 kvm_read_cr3(vcpu)))
628 return 1;
629 }
630
631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
634 kvm_x86_ops->set_cr0(vcpu, cr0);
635
636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
637 kvm_clear_async_pf_completion_queue(vcpu);
638 kvm_async_pf_hash_reset(vcpu);
639 }
640
641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
643
644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
649 return 0;
650 }
651 EXPORT_SYMBOL_GPL(kvm_set_cr0);
652
653 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
654 {
655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
656 }
657 EXPORT_SYMBOL_GPL(kvm_lmsw);
658
659 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660 {
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667 }
668
669 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670 {
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676 }
677
678 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
679 {
680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
682 u64 valid_bits;
683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
687 if (!(xcr0 & XFEATURE_MASK_FP))
688 return 1;
689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
690 return 1;
691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
698 if (xcr0 & ~valid_bits)
699 return 1;
700
701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
703 return 1;
704
705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
707 return 1;
708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
709 return 1;
710 }
711 vcpu->arch.xcr0 = xcr0;
712
713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
714 kvm_update_cpuid(vcpu);
715 return 0;
716 }
717
718 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719 {
720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726 }
727 EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
729 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
730 {
731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
734
735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
737
738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
748 return 1;
749
750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
753 if (is_long_mode(vcpu)) {
754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
760 return 1;
761
762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
772 return 1;
773
774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
776 kvm_mmu_reset_context(vcpu);
777
778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
779 kvm_update_cpuid(vcpu);
780
781 return 0;
782 }
783 EXPORT_SYMBOL_GPL(kvm_set_cr4);
784
785 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
786 {
787 #ifdef CONFIG_X86_64
788 cr3 &= ~CR3_PCID_INVD;
789 #endif
790
791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
792 kvm_mmu_sync_roots(vcpu);
793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
794 return 0;
795 }
796
797 if (is_long_mode(vcpu)) {
798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
802 return 1;
803
804 vcpu->arch.cr3 = cr3;
805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
806 kvm_mmu_new_cr3(vcpu);
807 return 0;
808 }
809 EXPORT_SYMBOL_GPL(kvm_set_cr3);
810
811 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
812 {
813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
815 if (lapic_in_kernel(vcpu))
816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
818 vcpu->arch.cr8 = cr8;
819 return 0;
820 }
821 EXPORT_SYMBOL_GPL(kvm_set_cr8);
822
823 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
824 {
825 if (lapic_in_kernel(vcpu))
826 return kvm_lapic_get_cr8(vcpu);
827 else
828 return vcpu->arch.cr8;
829 }
830 EXPORT_SYMBOL_GPL(kvm_get_cr8);
831
832 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833 {
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841 }
842
843 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844 {
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847 }
848
849 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850 {
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
861 }
862
863 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864 {
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870 }
871
872 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
873 {
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
881 /* fall through */
882 case 6:
883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
886 kvm_update_dr6(vcpu);
887 break;
888 case 5:
889 /* fall through */
890 default: /* 7 */
891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
894 kvm_update_dr7(vcpu);
895 break;
896 }
897
898 return 0;
899 }
900
901 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902 {
903 if (__kvm_set_dr(vcpu, dr, val)) {
904 kvm_inject_gp(vcpu, 0);
905 return 1;
906 }
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(kvm_set_dr);
910
911 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
912 {
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
918 /* fall through */
919 case 6:
920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
924 break;
925 case 5:
926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
931 return 0;
932 }
933 EXPORT_SYMBOL_GPL(kvm_get_dr);
934
935 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936 {
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947 }
948 EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
950 /*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
955 * capabilities of the host cpu. This capabilities test skips MSRs that are
956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
958 */
959
960 static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
962 MSR_STAR,
963 #ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965 #endif
966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
968 };
969
970 static unsigned num_msrs_to_save;
971
972 static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
979 HV_X64_MSR_RESET,
980 HV_X64_MSR_VP_INDEX,
981 HV_X64_MSR_VP_RUNTIME,
982 HV_X64_MSR_SCONTROL,
983 HV_X64_MSR_STIMER0_CONFIG,
984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
987 MSR_IA32_TSC_ADJUST,
988 MSR_IA32_TSCDEADLINE,
989 MSR_IA32_MISC_ENABLE,
990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
992 MSR_IA32_MCG_EXT_CTL,
993 MSR_IA32_SMBASE,
994 };
995
996 static unsigned num_emulated_msrs;
997
998 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
999 {
1000 if (efer & efer_reserved_bits)
1001 return false;
1002
1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1008 return false;
1009 }
1010
1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024 {
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
1034 efer &= ~EFER_LMA;
1035 efer |= vcpu->arch.efer & EFER_LMA;
1036
1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
1043 return 0;
1044 }
1045
1046 void kvm_enable_efer_bits(u64 mask)
1047 {
1048 efer_reserved_bits &= ~mask;
1049 }
1050 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
1052 /*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
1057 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1058 {
1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
1084 return kvm_x86_ops->set_msr(vcpu, msr);
1085 }
1086 EXPORT_SYMBOL_GPL(kvm_set_msr);
1087
1088 /*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
1091 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092 {
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104 }
1105
1106 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107 {
1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
1114 }
1115
1116 #ifdef CONFIG_X86_64
1117 struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
1128 u64 boot_ns;
1129 u64 nsec_base;
1130 };
1131
1132 static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134 static void update_pvclock_gtod(struct timekeeper *tk)
1135 {
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1137 u64 boot_ns;
1138
1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
1149
1150 vdata->boot_ns = boot_ns;
1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1152
1153 write_seqcount_end(&vdata->seq);
1154 }
1155 #endif
1156
1157 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158 {
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165 }
1166
1167 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168 {
1169 int version;
1170 int r;
1171 struct pvclock_wall_clock wc;
1172 struct timespec64 boot;
1173
1174 if (!wall_clock)
1175 return;
1176
1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
1185
1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
1188
1189 /*
1190 * The guest calculates current wall clock time by adding
1191 * system time (updated by kvm_guest_time_update below) to the
1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
1195 getboottime64(&boot);
1196
1197 if (kvm->arch.kvmclock_offset) {
1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
1200 }
1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1209 }
1210
1211 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212 {
1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
1215 }
1216
1217 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1218 s8 *pshift, u32 *pmultiplier)
1219 {
1220 uint64_t scaled64;
1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
1238 shift++;
1239 }
1240
1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
1243
1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1246 }
1247
1248 #ifdef CONFIG_X86_64
1249 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1250 #endif
1251
1252 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1253 static unsigned long max_tsc_khz;
1254
1255 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1256 {
1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1260 }
1261
1262 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263 {
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296 }
1297
1298 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1299 {
1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
1302
1303 /* tsc_khz can be zero if TSC calibration fails */
1304 if (user_tsc_khz == 0) {
1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1307 return -1;
1308 }
1309
1310 /* Compute a scale to convert nanoseconds in TSC cycles */
1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1326 use_scaling = 1;
1327 }
1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1329 }
1330
1331 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332 {
1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
1336 tsc += vcpu->arch.this_tsc_write;
1337 return tsc;
1338 }
1339
1340 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1341 {
1342 #ifdef CONFIG_X86_64
1343 bool vcpus_matched;
1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365 #endif
1366 }
1367
1368 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369 {
1370 u64 curr_offset = vcpu->arch.tsc_offset;
1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372 }
1373
1374 /*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385 {
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387 }
1388
1389 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390 {
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398 }
1399 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
1401 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402 {
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408 }
1409
1410 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411 {
1412 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1413 }
1414 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
1416 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1417 {
1418 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1419 vcpu->arch.tsc_offset = offset;
1420 }
1421
1422 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1423 {
1424 struct kvm *kvm = vcpu->kvm;
1425 u64 offset, ns, elapsed;
1426 unsigned long flags;
1427 s64 usdiff;
1428 bool matched;
1429 bool already_matched;
1430 u64 data = msr->data;
1431
1432 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1433 offset = kvm_compute_tsc_offset(vcpu, data);
1434 ns = ktime_get_boot_ns();
1435 elapsed = ns - kvm->arch.last_tsc_nsec;
1436
1437 if (vcpu->arch.virtual_tsc_khz) {
1438 int faulted = 0;
1439
1440 /* n.b - signed multiplication and division required */
1441 usdiff = data - kvm->arch.last_tsc_write;
1442 #ifdef CONFIG_X86_64
1443 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1444 #else
1445 /* do_div() only does unsigned */
1446 asm("1: idivl %[divisor]\n"
1447 "2: xor %%edx, %%edx\n"
1448 " movl $0, %[faulted]\n"
1449 "3:\n"
1450 ".section .fixup,\"ax\"\n"
1451 "4: movl $1, %[faulted]\n"
1452 " jmp 3b\n"
1453 ".previous\n"
1454
1455 _ASM_EXTABLE(1b, 4b)
1456
1457 : "=A"(usdiff), [faulted] "=r" (faulted)
1458 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1459
1460 #endif
1461 do_div(elapsed, 1000);
1462 usdiff -= elapsed;
1463 if (usdiff < 0)
1464 usdiff = -usdiff;
1465
1466 /* idivl overflow => difference is larger than USEC_PER_SEC */
1467 if (faulted)
1468 usdiff = USEC_PER_SEC;
1469 } else
1470 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1471
1472 /*
1473 * Special case: TSC write with a small delta (1 second) of virtual
1474 * cycle time against real time is interpreted as an attempt to
1475 * synchronize the CPU.
1476 *
1477 * For a reliable TSC, we can match TSC offsets, and for an unstable
1478 * TSC, we add elapsed time in this computation. We could let the
1479 * compensation code attempt to catch up if we fall behind, but
1480 * it's better to try to match offsets from the beginning.
1481 */
1482 if (usdiff < USEC_PER_SEC &&
1483 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1484 if (!check_tsc_unstable()) {
1485 offset = kvm->arch.cur_tsc_offset;
1486 pr_debug("kvm: matched tsc offset for %llu\n", data);
1487 } else {
1488 u64 delta = nsec_to_cycles(vcpu, elapsed);
1489 data += delta;
1490 offset = kvm_compute_tsc_offset(vcpu, data);
1491 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1492 }
1493 matched = true;
1494 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1495 } else {
1496 /*
1497 * We split periods of matched TSC writes into generations.
1498 * For each generation, we track the original measured
1499 * nanosecond time, offset, and write, so if TSCs are in
1500 * sync, we can match exact offset, and if not, we can match
1501 * exact software computation in compute_guest_tsc()
1502 *
1503 * These values are tracked in kvm->arch.cur_xxx variables.
1504 */
1505 kvm->arch.cur_tsc_generation++;
1506 kvm->arch.cur_tsc_nsec = ns;
1507 kvm->arch.cur_tsc_write = data;
1508 kvm->arch.cur_tsc_offset = offset;
1509 matched = false;
1510 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1511 kvm->arch.cur_tsc_generation, data);
1512 }
1513
1514 /*
1515 * We also track th most recent recorded KHZ, write and time to
1516 * allow the matching interval to be extended at each write.
1517 */
1518 kvm->arch.last_tsc_nsec = ns;
1519 kvm->arch.last_tsc_write = data;
1520 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1521
1522 vcpu->arch.last_guest_tsc = data;
1523
1524 /* Keep track of which generation this VCPU has synchronized to */
1525 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1526 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1527 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1528
1529 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1530 update_ia32_tsc_adjust_msr(vcpu, offset);
1531 kvm_vcpu_write_tsc_offset(vcpu, offset);
1532 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1533
1534 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1535 if (!matched) {
1536 kvm->arch.nr_vcpus_matched_tsc = 0;
1537 } else if (!already_matched) {
1538 kvm->arch.nr_vcpus_matched_tsc++;
1539 }
1540
1541 kvm_track_tsc_matching(vcpu);
1542 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1543 }
1544
1545 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1546
1547 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1548 s64 adjustment)
1549 {
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551 }
1552
1553 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1554 {
1555 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1556 WARN_ON(adjustment < 0);
1557 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1558 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1559 }
1560
1561 #ifdef CONFIG_X86_64
1562
1563 static cycle_t read_tsc(void)
1564 {
1565 cycle_t ret = (cycle_t)rdtsc_ordered();
1566 u64 last = pvclock_gtod_data.clock.cycle_last;
1567
1568 if (likely(ret >= last))
1569 return ret;
1570
1571 /*
1572 * GCC likes to generate cmov here, but this branch is extremely
1573 * predictable (it's just a function of time and the likely is
1574 * very likely) and there's a data dependence, so force GCC
1575 * to generate a branch instead. I don't barrier() because
1576 * we don't actually need a barrier, and if this function
1577 * ever gets inlined it will generate worse code.
1578 */
1579 asm volatile ("");
1580 return last;
1581 }
1582
1583 static inline u64 vgettsc(cycle_t *cycle_now)
1584 {
1585 long v;
1586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1587
1588 *cycle_now = read_tsc();
1589
1590 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1591 return v * gtod->clock.mult;
1592 }
1593
1594 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1595 {
1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1597 unsigned long seq;
1598 int mode;
1599 u64 ns;
1600
1601 do {
1602 seq = read_seqcount_begin(&gtod->seq);
1603 mode = gtod->clock.vclock_mode;
1604 ns = gtod->nsec_base;
1605 ns += vgettsc(cycle_now);
1606 ns >>= gtod->clock.shift;
1607 ns += gtod->boot_ns;
1608 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1609 *t = ns;
1610
1611 return mode;
1612 }
1613
1614 /* returns true if host is using tsc clocksource */
1615 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1616 {
1617 /* checked again under seqlock below */
1618 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1619 return false;
1620
1621 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1622 }
1623 #endif
1624
1625 /*
1626 *
1627 * Assuming a stable TSC across physical CPUS, and a stable TSC
1628 * across virtual CPUs, the following condition is possible.
1629 * Each numbered line represents an event visible to both
1630 * CPUs at the next numbered event.
1631 *
1632 * "timespecX" represents host monotonic time. "tscX" represents
1633 * RDTSC value.
1634 *
1635 * VCPU0 on CPU0 | VCPU1 on CPU1
1636 *
1637 * 1. read timespec0,tsc0
1638 * 2. | timespec1 = timespec0 + N
1639 * | tsc1 = tsc0 + M
1640 * 3. transition to guest | transition to guest
1641 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1642 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1643 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1644 *
1645 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1646 *
1647 * - ret0 < ret1
1648 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1649 * ...
1650 * - 0 < N - M => M < N
1651 *
1652 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1653 * always the case (the difference between two distinct xtime instances
1654 * might be smaller then the difference between corresponding TSC reads,
1655 * when updating guest vcpus pvclock areas).
1656 *
1657 * To avoid that problem, do not allow visibility of distinct
1658 * system_timestamp/tsc_timestamp values simultaneously: use a master
1659 * copy of host monotonic time values. Update that master copy
1660 * in lockstep.
1661 *
1662 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1663 *
1664 */
1665
1666 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1667 {
1668 #ifdef CONFIG_X86_64
1669 struct kvm_arch *ka = &kvm->arch;
1670 int vclock_mode;
1671 bool host_tsc_clocksource, vcpus_matched;
1672
1673 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1674 atomic_read(&kvm->online_vcpus));
1675
1676 /*
1677 * If the host uses TSC clock, then passthrough TSC as stable
1678 * to the guest.
1679 */
1680 host_tsc_clocksource = kvm_get_time_and_clockread(
1681 &ka->master_kernel_ns,
1682 &ka->master_cycle_now);
1683
1684 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1685 && !backwards_tsc_observed
1686 && !ka->boot_vcpu_runs_old_kvmclock;
1687
1688 if (ka->use_master_clock)
1689 atomic_set(&kvm_guest_has_master_clock, 1);
1690
1691 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1692 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1693 vcpus_matched);
1694 #endif
1695 }
1696
1697 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1698 {
1699 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1700 }
1701
1702 static void kvm_gen_update_masterclock(struct kvm *kvm)
1703 {
1704 #ifdef CONFIG_X86_64
1705 int i;
1706 struct kvm_vcpu *vcpu;
1707 struct kvm_arch *ka = &kvm->arch;
1708
1709 spin_lock(&ka->pvclock_gtod_sync_lock);
1710 kvm_make_mclock_inprogress_request(kvm);
1711 /* no guest entries from this point */
1712 pvclock_update_vm_gtod_copy(kvm);
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm)
1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1716
1717 /* guest entries allowed */
1718 kvm_for_each_vcpu(i, vcpu, kvm)
1719 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1720
1721 spin_unlock(&ka->pvclock_gtod_sync_lock);
1722 #endif
1723 }
1724
1725 static u64 __get_kvmclock_ns(struct kvm *kvm)
1726 {
1727 struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, 0);
1728 struct kvm_arch *ka = &kvm->arch;
1729 s64 ns;
1730
1731 if (vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT) {
1732 u64 tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1733 ns = __pvclock_read_cycles(&vcpu->arch.hv_clock, tsc);
1734 } else {
1735 ns = ktime_get_boot_ns() + ka->kvmclock_offset;
1736 }
1737
1738 return ns;
1739 }
1740
1741 u64 get_kvmclock_ns(struct kvm *kvm)
1742 {
1743 unsigned long flags;
1744 s64 ns;
1745
1746 local_irq_save(flags);
1747 ns = __get_kvmclock_ns(kvm);
1748 local_irq_restore(flags);
1749
1750 return ns;
1751 }
1752
1753 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1754 {
1755 struct kvm_vcpu_arch *vcpu = &v->arch;
1756 struct pvclock_vcpu_time_info guest_hv_clock;
1757
1758 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1759 &guest_hv_clock, sizeof(guest_hv_clock))))
1760 return;
1761
1762 /* This VCPU is paused, but it's legal for a guest to read another
1763 * VCPU's kvmclock, so we really have to follow the specification where
1764 * it says that version is odd if data is being modified, and even after
1765 * it is consistent.
1766 *
1767 * Version field updates must be kept separate. This is because
1768 * kvm_write_guest_cached might use a "rep movs" instruction, and
1769 * writes within a string instruction are weakly ordered. So there
1770 * are three writes overall.
1771 *
1772 * As a small optimization, only write the version field in the first
1773 * and third write. The vcpu->pv_time cache is still valid, because the
1774 * version field is the first in the struct.
1775 */
1776 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1777
1778 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1779 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1780 &vcpu->hv_clock,
1781 sizeof(vcpu->hv_clock.version));
1782
1783 smp_wmb();
1784
1785 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1786 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1787
1788 if (vcpu->pvclock_set_guest_stopped_request) {
1789 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1790 vcpu->pvclock_set_guest_stopped_request = false;
1791 }
1792
1793 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1794
1795 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1796 &vcpu->hv_clock,
1797 sizeof(vcpu->hv_clock));
1798
1799 smp_wmb();
1800
1801 vcpu->hv_clock.version++;
1802 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1803 &vcpu->hv_clock,
1804 sizeof(vcpu->hv_clock.version));
1805 }
1806
1807 static int kvm_guest_time_update(struct kvm_vcpu *v)
1808 {
1809 unsigned long flags, tgt_tsc_khz;
1810 struct kvm_vcpu_arch *vcpu = &v->arch;
1811 struct kvm_arch *ka = &v->kvm->arch;
1812 s64 kernel_ns;
1813 u64 tsc_timestamp, host_tsc;
1814 u8 pvclock_flags;
1815 bool use_master_clock;
1816
1817 kernel_ns = 0;
1818 host_tsc = 0;
1819
1820 /*
1821 * If the host uses TSC clock, then passthrough TSC as stable
1822 * to the guest.
1823 */
1824 spin_lock(&ka->pvclock_gtod_sync_lock);
1825 use_master_clock = ka->use_master_clock;
1826 if (use_master_clock) {
1827 host_tsc = ka->master_cycle_now;
1828 kernel_ns = ka->master_kernel_ns;
1829 }
1830 spin_unlock(&ka->pvclock_gtod_sync_lock);
1831
1832 /* Keep irq disabled to prevent changes to the clock */
1833 local_irq_save(flags);
1834 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1835 if (unlikely(tgt_tsc_khz == 0)) {
1836 local_irq_restore(flags);
1837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1838 return 1;
1839 }
1840 if (!use_master_clock) {
1841 host_tsc = rdtsc();
1842 kernel_ns = ktime_get_boot_ns();
1843 }
1844
1845 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1846
1847 /*
1848 * We may have to catch up the TSC to match elapsed wall clock
1849 * time for two reasons, even if kvmclock is used.
1850 * 1) CPU could have been running below the maximum TSC rate
1851 * 2) Broken TSC compensation resets the base at each VCPU
1852 * entry to avoid unknown leaps of TSC even when running
1853 * again on the same CPU. This may cause apparent elapsed
1854 * time to disappear, and the guest to stand still or run
1855 * very slowly.
1856 */
1857 if (vcpu->tsc_catchup) {
1858 u64 tsc = compute_guest_tsc(v, kernel_ns);
1859 if (tsc > tsc_timestamp) {
1860 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1861 tsc_timestamp = tsc;
1862 }
1863 }
1864
1865 local_irq_restore(flags);
1866
1867 /* With all the info we got, fill in the values */
1868
1869 if (kvm_has_tsc_control)
1870 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1871
1872 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1873 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1874 &vcpu->hv_clock.tsc_shift,
1875 &vcpu->hv_clock.tsc_to_system_mul);
1876 vcpu->hw_tsc_khz = tgt_tsc_khz;
1877 }
1878
1879 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1880 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1881 vcpu->last_guest_tsc = tsc_timestamp;
1882
1883 /* If the host uses TSC clocksource, then it is stable */
1884 pvclock_flags = 0;
1885 if (use_master_clock)
1886 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1887
1888 vcpu->hv_clock.flags = pvclock_flags;
1889
1890 if (vcpu->pv_time_enabled)
1891 kvm_setup_pvclock_page(v);
1892 if (v == kvm_get_vcpu(v->kvm, 0))
1893 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1894 return 0;
1895 }
1896
1897 /*
1898 * kvmclock updates which are isolated to a given vcpu, such as
1899 * vcpu->cpu migration, should not allow system_timestamp from
1900 * the rest of the vcpus to remain static. Otherwise ntp frequency
1901 * correction applies to one vcpu's system_timestamp but not
1902 * the others.
1903 *
1904 * So in those cases, request a kvmclock update for all vcpus.
1905 * We need to rate-limit these requests though, as they can
1906 * considerably slow guests that have a large number of vcpus.
1907 * The time for a remote vcpu to update its kvmclock is bound
1908 * by the delay we use to rate-limit the updates.
1909 */
1910
1911 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1912
1913 static void kvmclock_update_fn(struct work_struct *work)
1914 {
1915 int i;
1916 struct delayed_work *dwork = to_delayed_work(work);
1917 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1918 kvmclock_update_work);
1919 struct kvm *kvm = container_of(ka, struct kvm, arch);
1920 struct kvm_vcpu *vcpu;
1921
1922 kvm_for_each_vcpu(i, vcpu, kvm) {
1923 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1924 kvm_vcpu_kick(vcpu);
1925 }
1926 }
1927
1928 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1929 {
1930 struct kvm *kvm = v->kvm;
1931
1932 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1933 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1934 KVMCLOCK_UPDATE_DELAY);
1935 }
1936
1937 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1938
1939 static void kvmclock_sync_fn(struct work_struct *work)
1940 {
1941 struct delayed_work *dwork = to_delayed_work(work);
1942 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1943 kvmclock_sync_work);
1944 struct kvm *kvm = container_of(ka, struct kvm, arch);
1945
1946 if (!kvmclock_periodic_sync)
1947 return;
1948
1949 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1950 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1951 KVMCLOCK_SYNC_PERIOD);
1952 }
1953
1954 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1955 {
1956 u64 mcg_cap = vcpu->arch.mcg_cap;
1957 unsigned bank_num = mcg_cap & 0xff;
1958
1959 switch (msr) {
1960 case MSR_IA32_MCG_STATUS:
1961 vcpu->arch.mcg_status = data;
1962 break;
1963 case MSR_IA32_MCG_CTL:
1964 if (!(mcg_cap & MCG_CTL_P))
1965 return 1;
1966 if (data != 0 && data != ~(u64)0)
1967 return -1;
1968 vcpu->arch.mcg_ctl = data;
1969 break;
1970 default:
1971 if (msr >= MSR_IA32_MC0_CTL &&
1972 msr < MSR_IA32_MCx_CTL(bank_num)) {
1973 u32 offset = msr - MSR_IA32_MC0_CTL;
1974 /* only 0 or all 1s can be written to IA32_MCi_CTL
1975 * some Linux kernels though clear bit 10 in bank 4 to
1976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1977 * this to avoid an uncatched #GP in the guest
1978 */
1979 if ((offset & 0x3) == 0 &&
1980 data != 0 && (data | (1 << 10)) != ~(u64)0)
1981 return -1;
1982 vcpu->arch.mce_banks[offset] = data;
1983 break;
1984 }
1985 return 1;
1986 }
1987 return 0;
1988 }
1989
1990 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1991 {
1992 struct kvm *kvm = vcpu->kvm;
1993 int lm = is_long_mode(vcpu);
1994 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1995 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1996 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1997 : kvm->arch.xen_hvm_config.blob_size_32;
1998 u32 page_num = data & ~PAGE_MASK;
1999 u64 page_addr = data & PAGE_MASK;
2000 u8 *page;
2001 int r;
2002
2003 r = -E2BIG;
2004 if (page_num >= blob_size)
2005 goto out;
2006 r = -ENOMEM;
2007 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2008 if (IS_ERR(page)) {
2009 r = PTR_ERR(page);
2010 goto out;
2011 }
2012 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2013 goto out_free;
2014 r = 0;
2015 out_free:
2016 kfree(page);
2017 out:
2018 return r;
2019 }
2020
2021 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2022 {
2023 gpa_t gpa = data & ~0x3f;
2024
2025 /* Bits 2:5 are reserved, Should be zero */
2026 if (data & 0x3c)
2027 return 1;
2028
2029 vcpu->arch.apf.msr_val = data;
2030
2031 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2032 kvm_clear_async_pf_completion_queue(vcpu);
2033 kvm_async_pf_hash_reset(vcpu);
2034 return 0;
2035 }
2036
2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2038 sizeof(u32)))
2039 return 1;
2040
2041 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2042 kvm_async_pf_wakeup_all(vcpu);
2043 return 0;
2044 }
2045
2046 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2047 {
2048 vcpu->arch.pv_time_enabled = false;
2049 }
2050
2051 static void record_steal_time(struct kvm_vcpu *vcpu)
2052 {
2053 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2054 return;
2055
2056 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2057 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2058 return;
2059
2060 if (vcpu->arch.st.steal.version & 1)
2061 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2062
2063 vcpu->arch.st.steal.version += 1;
2064
2065 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2066 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2067
2068 smp_wmb();
2069
2070 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2071 vcpu->arch.st.last_steal;
2072 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2073
2074 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2075 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2076
2077 smp_wmb();
2078
2079 vcpu->arch.st.steal.version += 1;
2080
2081 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2082 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2083 }
2084
2085 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2086 {
2087 bool pr = false;
2088 u32 msr = msr_info->index;
2089 u64 data = msr_info->data;
2090
2091 switch (msr) {
2092 case MSR_AMD64_NB_CFG:
2093 case MSR_IA32_UCODE_REV:
2094 case MSR_IA32_UCODE_WRITE:
2095 case MSR_VM_HSAVE_PA:
2096 case MSR_AMD64_PATCH_LOADER:
2097 case MSR_AMD64_BU_CFG2:
2098 break;
2099
2100 case MSR_EFER:
2101 return set_efer(vcpu, data);
2102 case MSR_K7_HWCR:
2103 data &= ~(u64)0x40; /* ignore flush filter disable */
2104 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2105 data &= ~(u64)0x8; /* ignore TLB cache disable */
2106 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2107 if (data != 0) {
2108 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2109 data);
2110 return 1;
2111 }
2112 break;
2113 case MSR_FAM10H_MMIO_CONF_BASE:
2114 if (data != 0) {
2115 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2116 "0x%llx\n", data);
2117 return 1;
2118 }
2119 break;
2120 case MSR_IA32_DEBUGCTLMSR:
2121 if (!data) {
2122 /* We support the non-activated case already */
2123 break;
2124 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2125 /* Values other than LBR and BTF are vendor-specific,
2126 thus reserved and should throw a #GP */
2127 return 1;
2128 }
2129 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2130 __func__, data);
2131 break;
2132 case 0x200 ... 0x2ff:
2133 return kvm_mtrr_set_msr(vcpu, msr, data);
2134 case MSR_IA32_APICBASE:
2135 return kvm_set_apic_base(vcpu, msr_info);
2136 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2137 return kvm_x2apic_msr_write(vcpu, msr, data);
2138 case MSR_IA32_TSCDEADLINE:
2139 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2140 break;
2141 case MSR_IA32_TSC_ADJUST:
2142 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2143 if (!msr_info->host_initiated) {
2144 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2145 adjust_tsc_offset_guest(vcpu, adj);
2146 }
2147 vcpu->arch.ia32_tsc_adjust_msr = data;
2148 }
2149 break;
2150 case MSR_IA32_MISC_ENABLE:
2151 vcpu->arch.ia32_misc_enable_msr = data;
2152 break;
2153 case MSR_IA32_SMBASE:
2154 if (!msr_info->host_initiated)
2155 return 1;
2156 vcpu->arch.smbase = data;
2157 break;
2158 case MSR_KVM_WALL_CLOCK_NEW:
2159 case MSR_KVM_WALL_CLOCK:
2160 vcpu->kvm->arch.wall_clock = data;
2161 kvm_write_wall_clock(vcpu->kvm, data);
2162 break;
2163 case MSR_KVM_SYSTEM_TIME_NEW:
2164 case MSR_KVM_SYSTEM_TIME: {
2165 u64 gpa_offset;
2166 struct kvm_arch *ka = &vcpu->kvm->arch;
2167
2168 kvmclock_reset(vcpu);
2169
2170 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2171 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2172
2173 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2174 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2175 &vcpu->requests);
2176
2177 ka->boot_vcpu_runs_old_kvmclock = tmp;
2178 }
2179
2180 vcpu->arch.time = data;
2181 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2182
2183 /* we verify if the enable bit is set... */
2184 if (!(data & 1))
2185 break;
2186
2187 gpa_offset = data & ~(PAGE_MASK | 1);
2188
2189 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2190 &vcpu->arch.pv_time, data & ~1ULL,
2191 sizeof(struct pvclock_vcpu_time_info)))
2192 vcpu->arch.pv_time_enabled = false;
2193 else
2194 vcpu->arch.pv_time_enabled = true;
2195
2196 break;
2197 }
2198 case MSR_KVM_ASYNC_PF_EN:
2199 if (kvm_pv_enable_async_pf(vcpu, data))
2200 return 1;
2201 break;
2202 case MSR_KVM_STEAL_TIME:
2203
2204 if (unlikely(!sched_info_on()))
2205 return 1;
2206
2207 if (data & KVM_STEAL_RESERVED_MASK)
2208 return 1;
2209
2210 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2211 data & KVM_STEAL_VALID_BITS,
2212 sizeof(struct kvm_steal_time)))
2213 return 1;
2214
2215 vcpu->arch.st.msr_val = data;
2216
2217 if (!(data & KVM_MSR_ENABLED))
2218 break;
2219
2220 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2221
2222 break;
2223 case MSR_KVM_PV_EOI_EN:
2224 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2225 return 1;
2226 break;
2227
2228 case MSR_IA32_MCG_CTL:
2229 case MSR_IA32_MCG_STATUS:
2230 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2231 return set_msr_mce(vcpu, msr, data);
2232
2233 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2234 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2235 pr = true; /* fall through */
2236 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2237 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2238 if (kvm_pmu_is_valid_msr(vcpu, msr))
2239 return kvm_pmu_set_msr(vcpu, msr_info);
2240
2241 if (pr || data != 0)
2242 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2243 "0x%x data 0x%llx\n", msr, data);
2244 break;
2245 case MSR_K7_CLK_CTL:
2246 /*
2247 * Ignore all writes to this no longer documented MSR.
2248 * Writes are only relevant for old K7 processors,
2249 * all pre-dating SVM, but a recommended workaround from
2250 * AMD for these chips. It is possible to specify the
2251 * affected processor models on the command line, hence
2252 * the need to ignore the workaround.
2253 */
2254 break;
2255 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2256 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2257 case HV_X64_MSR_CRASH_CTL:
2258 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2259 return kvm_hv_set_msr_common(vcpu, msr, data,
2260 msr_info->host_initiated);
2261 case MSR_IA32_BBL_CR_CTL3:
2262 /* Drop writes to this legacy MSR -- see rdmsr
2263 * counterpart for further detail.
2264 */
2265 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2266 break;
2267 case MSR_AMD64_OSVW_ID_LENGTH:
2268 if (!guest_cpuid_has_osvw(vcpu))
2269 return 1;
2270 vcpu->arch.osvw.length = data;
2271 break;
2272 case MSR_AMD64_OSVW_STATUS:
2273 if (!guest_cpuid_has_osvw(vcpu))
2274 return 1;
2275 vcpu->arch.osvw.status = data;
2276 break;
2277 default:
2278 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2279 return xen_hvm_config(vcpu, data);
2280 if (kvm_pmu_is_valid_msr(vcpu, msr))
2281 return kvm_pmu_set_msr(vcpu, msr_info);
2282 if (!ignore_msrs) {
2283 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2284 msr, data);
2285 return 1;
2286 } else {
2287 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2288 msr, data);
2289 break;
2290 }
2291 }
2292 return 0;
2293 }
2294 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2295
2296
2297 /*
2298 * Reads an msr value (of 'msr_index') into 'pdata'.
2299 * Returns 0 on success, non-0 otherwise.
2300 * Assumes vcpu_load() was already called.
2301 */
2302 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2303 {
2304 return kvm_x86_ops->get_msr(vcpu, msr);
2305 }
2306 EXPORT_SYMBOL_GPL(kvm_get_msr);
2307
2308 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2309 {
2310 u64 data;
2311 u64 mcg_cap = vcpu->arch.mcg_cap;
2312 unsigned bank_num = mcg_cap & 0xff;
2313
2314 switch (msr) {
2315 case MSR_IA32_P5_MC_ADDR:
2316 case MSR_IA32_P5_MC_TYPE:
2317 data = 0;
2318 break;
2319 case MSR_IA32_MCG_CAP:
2320 data = vcpu->arch.mcg_cap;
2321 break;
2322 case MSR_IA32_MCG_CTL:
2323 if (!(mcg_cap & MCG_CTL_P))
2324 return 1;
2325 data = vcpu->arch.mcg_ctl;
2326 break;
2327 case MSR_IA32_MCG_STATUS:
2328 data = vcpu->arch.mcg_status;
2329 break;
2330 default:
2331 if (msr >= MSR_IA32_MC0_CTL &&
2332 msr < MSR_IA32_MCx_CTL(bank_num)) {
2333 u32 offset = msr - MSR_IA32_MC0_CTL;
2334 data = vcpu->arch.mce_banks[offset];
2335 break;
2336 }
2337 return 1;
2338 }
2339 *pdata = data;
2340 return 0;
2341 }
2342
2343 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2344 {
2345 switch (msr_info->index) {
2346 case MSR_IA32_PLATFORM_ID:
2347 case MSR_IA32_EBL_CR_POWERON:
2348 case MSR_IA32_DEBUGCTLMSR:
2349 case MSR_IA32_LASTBRANCHFROMIP:
2350 case MSR_IA32_LASTBRANCHTOIP:
2351 case MSR_IA32_LASTINTFROMIP:
2352 case MSR_IA32_LASTINTTOIP:
2353 case MSR_K8_SYSCFG:
2354 case MSR_K8_TSEG_ADDR:
2355 case MSR_K8_TSEG_MASK:
2356 case MSR_K7_HWCR:
2357 case MSR_VM_HSAVE_PA:
2358 case MSR_K8_INT_PENDING_MSG:
2359 case MSR_AMD64_NB_CFG:
2360 case MSR_FAM10H_MMIO_CONF_BASE:
2361 case MSR_AMD64_BU_CFG2:
2362 case MSR_IA32_PERF_CTL:
2363 msr_info->data = 0;
2364 break;
2365 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2366 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2367 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2368 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2369 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2370 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2371 msr_info->data = 0;
2372 break;
2373 case MSR_IA32_UCODE_REV:
2374 msr_info->data = 0x100000000ULL;
2375 break;
2376 case MSR_MTRRcap:
2377 case 0x200 ... 0x2ff:
2378 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2379 case 0xcd: /* fsb frequency */
2380 msr_info->data = 3;
2381 break;
2382 /*
2383 * MSR_EBC_FREQUENCY_ID
2384 * Conservative value valid for even the basic CPU models.
2385 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2386 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2387 * and 266MHz for model 3, or 4. Set Core Clock
2388 * Frequency to System Bus Frequency Ratio to 1 (bits
2389 * 31:24) even though these are only valid for CPU
2390 * models > 2, however guests may end up dividing or
2391 * multiplying by zero otherwise.
2392 */
2393 case MSR_EBC_FREQUENCY_ID:
2394 msr_info->data = 1 << 24;
2395 break;
2396 case MSR_IA32_APICBASE:
2397 msr_info->data = kvm_get_apic_base(vcpu);
2398 break;
2399 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2400 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2401 break;
2402 case MSR_IA32_TSCDEADLINE:
2403 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2404 break;
2405 case MSR_IA32_TSC_ADJUST:
2406 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2407 break;
2408 case MSR_IA32_MISC_ENABLE:
2409 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2410 break;
2411 case MSR_IA32_SMBASE:
2412 if (!msr_info->host_initiated)
2413 return 1;
2414 msr_info->data = vcpu->arch.smbase;
2415 break;
2416 case MSR_IA32_PERF_STATUS:
2417 /* TSC increment by tick */
2418 msr_info->data = 1000ULL;
2419 /* CPU multiplier */
2420 msr_info->data |= (((uint64_t)4ULL) << 40);
2421 break;
2422 case MSR_EFER:
2423 msr_info->data = vcpu->arch.efer;
2424 break;
2425 case MSR_KVM_WALL_CLOCK:
2426 case MSR_KVM_WALL_CLOCK_NEW:
2427 msr_info->data = vcpu->kvm->arch.wall_clock;
2428 break;
2429 case MSR_KVM_SYSTEM_TIME:
2430 case MSR_KVM_SYSTEM_TIME_NEW:
2431 msr_info->data = vcpu->arch.time;
2432 break;
2433 case MSR_KVM_ASYNC_PF_EN:
2434 msr_info->data = vcpu->arch.apf.msr_val;
2435 break;
2436 case MSR_KVM_STEAL_TIME:
2437 msr_info->data = vcpu->arch.st.msr_val;
2438 break;
2439 case MSR_KVM_PV_EOI_EN:
2440 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2441 break;
2442 case MSR_IA32_P5_MC_ADDR:
2443 case MSR_IA32_P5_MC_TYPE:
2444 case MSR_IA32_MCG_CAP:
2445 case MSR_IA32_MCG_CTL:
2446 case MSR_IA32_MCG_STATUS:
2447 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2448 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2449 case MSR_K7_CLK_CTL:
2450 /*
2451 * Provide expected ramp-up count for K7. All other
2452 * are set to zero, indicating minimum divisors for
2453 * every field.
2454 *
2455 * This prevents guest kernels on AMD host with CPU
2456 * type 6, model 8 and higher from exploding due to
2457 * the rdmsr failing.
2458 */
2459 msr_info->data = 0x20000000;
2460 break;
2461 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2462 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2463 case HV_X64_MSR_CRASH_CTL:
2464 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2465 return kvm_hv_get_msr_common(vcpu,
2466 msr_info->index, &msr_info->data);
2467 break;
2468 case MSR_IA32_BBL_CR_CTL3:
2469 /* This legacy MSR exists but isn't fully documented in current
2470 * silicon. It is however accessed by winxp in very narrow
2471 * scenarios where it sets bit #19, itself documented as
2472 * a "reserved" bit. Best effort attempt to source coherent
2473 * read data here should the balance of the register be
2474 * interpreted by the guest:
2475 *
2476 * L2 cache control register 3: 64GB range, 256KB size,
2477 * enabled, latency 0x1, configured
2478 */
2479 msr_info->data = 0xbe702111;
2480 break;
2481 case MSR_AMD64_OSVW_ID_LENGTH:
2482 if (!guest_cpuid_has_osvw(vcpu))
2483 return 1;
2484 msr_info->data = vcpu->arch.osvw.length;
2485 break;
2486 case MSR_AMD64_OSVW_STATUS:
2487 if (!guest_cpuid_has_osvw(vcpu))
2488 return 1;
2489 msr_info->data = vcpu->arch.osvw.status;
2490 break;
2491 default:
2492 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2493 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2494 if (!ignore_msrs) {
2495 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2496 return 1;
2497 } else {
2498 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2499 msr_info->data = 0;
2500 }
2501 break;
2502 }
2503 return 0;
2504 }
2505 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2506
2507 /*
2508 * Read or write a bunch of msrs. All parameters are kernel addresses.
2509 *
2510 * @return number of msrs set successfully.
2511 */
2512 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2513 struct kvm_msr_entry *entries,
2514 int (*do_msr)(struct kvm_vcpu *vcpu,
2515 unsigned index, u64 *data))
2516 {
2517 int i, idx;
2518
2519 idx = srcu_read_lock(&vcpu->kvm->srcu);
2520 for (i = 0; i < msrs->nmsrs; ++i)
2521 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2522 break;
2523 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2524
2525 return i;
2526 }
2527
2528 /*
2529 * Read or write a bunch of msrs. Parameters are user addresses.
2530 *
2531 * @return number of msrs set successfully.
2532 */
2533 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2534 int (*do_msr)(struct kvm_vcpu *vcpu,
2535 unsigned index, u64 *data),
2536 int writeback)
2537 {
2538 struct kvm_msrs msrs;
2539 struct kvm_msr_entry *entries;
2540 int r, n;
2541 unsigned size;
2542
2543 r = -EFAULT;
2544 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2545 goto out;
2546
2547 r = -E2BIG;
2548 if (msrs.nmsrs >= MAX_IO_MSRS)
2549 goto out;
2550
2551 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2552 entries = memdup_user(user_msrs->entries, size);
2553 if (IS_ERR(entries)) {
2554 r = PTR_ERR(entries);
2555 goto out;
2556 }
2557
2558 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2559 if (r < 0)
2560 goto out_free;
2561
2562 r = -EFAULT;
2563 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2564 goto out_free;
2565
2566 r = n;
2567
2568 out_free:
2569 kfree(entries);
2570 out:
2571 return r;
2572 }
2573
2574 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2575 {
2576 int r;
2577
2578 switch (ext) {
2579 case KVM_CAP_IRQCHIP:
2580 case KVM_CAP_HLT:
2581 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2582 case KVM_CAP_SET_TSS_ADDR:
2583 case KVM_CAP_EXT_CPUID:
2584 case KVM_CAP_EXT_EMUL_CPUID:
2585 case KVM_CAP_CLOCKSOURCE:
2586 case KVM_CAP_PIT:
2587 case KVM_CAP_NOP_IO_DELAY:
2588 case KVM_CAP_MP_STATE:
2589 case KVM_CAP_SYNC_MMU:
2590 case KVM_CAP_USER_NMI:
2591 case KVM_CAP_REINJECT_CONTROL:
2592 case KVM_CAP_IRQ_INJECT_STATUS:
2593 case KVM_CAP_IOEVENTFD:
2594 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2595 case KVM_CAP_PIT2:
2596 case KVM_CAP_PIT_STATE2:
2597 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2598 case KVM_CAP_XEN_HVM:
2599 case KVM_CAP_ADJUST_CLOCK:
2600 case KVM_CAP_VCPU_EVENTS:
2601 case KVM_CAP_HYPERV:
2602 case KVM_CAP_HYPERV_VAPIC:
2603 case KVM_CAP_HYPERV_SPIN:
2604 case KVM_CAP_HYPERV_SYNIC:
2605 case KVM_CAP_PCI_SEGMENT:
2606 case KVM_CAP_DEBUGREGS:
2607 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2608 case KVM_CAP_XSAVE:
2609 case KVM_CAP_ASYNC_PF:
2610 case KVM_CAP_GET_TSC_KHZ:
2611 case KVM_CAP_KVMCLOCK_CTRL:
2612 case KVM_CAP_READONLY_MEM:
2613 case KVM_CAP_HYPERV_TIME:
2614 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2615 case KVM_CAP_TSC_DEADLINE_TIMER:
2616 case KVM_CAP_ENABLE_CAP_VM:
2617 case KVM_CAP_DISABLE_QUIRKS:
2618 case KVM_CAP_SET_BOOT_CPU_ID:
2619 case KVM_CAP_SPLIT_IRQCHIP:
2620 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2621 case KVM_CAP_ASSIGN_DEV_IRQ:
2622 case KVM_CAP_PCI_2_3:
2623 #endif
2624 r = 1;
2625 break;
2626 case KVM_CAP_X86_SMM:
2627 /* SMBASE is usually relocated above 1M on modern chipsets,
2628 * and SMM handlers might indeed rely on 4G segment limits,
2629 * so do not report SMM to be available if real mode is
2630 * emulated via vm86 mode. Still, do not go to great lengths
2631 * to avoid userspace's usage of the feature, because it is a
2632 * fringe case that is not enabled except via specific settings
2633 * of the module parameters.
2634 */
2635 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2636 break;
2637 case KVM_CAP_COALESCED_MMIO:
2638 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2639 break;
2640 case KVM_CAP_VAPIC:
2641 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2642 break;
2643 case KVM_CAP_NR_VCPUS:
2644 r = KVM_SOFT_MAX_VCPUS;
2645 break;
2646 case KVM_CAP_MAX_VCPUS:
2647 r = KVM_MAX_VCPUS;
2648 break;
2649 case KVM_CAP_NR_MEMSLOTS:
2650 r = KVM_USER_MEM_SLOTS;
2651 break;
2652 case KVM_CAP_PV_MMU: /* obsolete */
2653 r = 0;
2654 break;
2655 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2656 case KVM_CAP_IOMMU:
2657 r = iommu_present(&pci_bus_type);
2658 break;
2659 #endif
2660 case KVM_CAP_MCE:
2661 r = KVM_MAX_MCE_BANKS;
2662 break;
2663 case KVM_CAP_XCRS:
2664 r = boot_cpu_has(X86_FEATURE_XSAVE);
2665 break;
2666 case KVM_CAP_TSC_CONTROL:
2667 r = kvm_has_tsc_control;
2668 break;
2669 case KVM_CAP_X2APIC_API:
2670 r = KVM_X2APIC_API_VALID_FLAGS;
2671 break;
2672 default:
2673 r = 0;
2674 break;
2675 }
2676 return r;
2677
2678 }
2679
2680 long kvm_arch_dev_ioctl(struct file *filp,
2681 unsigned int ioctl, unsigned long arg)
2682 {
2683 void __user *argp = (void __user *)arg;
2684 long r;
2685
2686 switch (ioctl) {
2687 case KVM_GET_MSR_INDEX_LIST: {
2688 struct kvm_msr_list __user *user_msr_list = argp;
2689 struct kvm_msr_list msr_list;
2690 unsigned n;
2691
2692 r = -EFAULT;
2693 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2694 goto out;
2695 n = msr_list.nmsrs;
2696 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2697 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2698 goto out;
2699 r = -E2BIG;
2700 if (n < msr_list.nmsrs)
2701 goto out;
2702 r = -EFAULT;
2703 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2704 num_msrs_to_save * sizeof(u32)))
2705 goto out;
2706 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2707 &emulated_msrs,
2708 num_emulated_msrs * sizeof(u32)))
2709 goto out;
2710 r = 0;
2711 break;
2712 }
2713 case KVM_GET_SUPPORTED_CPUID:
2714 case KVM_GET_EMULATED_CPUID: {
2715 struct kvm_cpuid2 __user *cpuid_arg = argp;
2716 struct kvm_cpuid2 cpuid;
2717
2718 r = -EFAULT;
2719 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2720 goto out;
2721
2722 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2723 ioctl);
2724 if (r)
2725 goto out;
2726
2727 r = -EFAULT;
2728 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2729 goto out;
2730 r = 0;
2731 break;
2732 }
2733 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2734 r = -EFAULT;
2735 if (copy_to_user(argp, &kvm_mce_cap_supported,
2736 sizeof(kvm_mce_cap_supported)))
2737 goto out;
2738 r = 0;
2739 break;
2740 }
2741 default:
2742 r = -EINVAL;
2743 }
2744 out:
2745 return r;
2746 }
2747
2748 static void wbinvd_ipi(void *garbage)
2749 {
2750 wbinvd();
2751 }
2752
2753 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2754 {
2755 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2756 }
2757
2758 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2759 {
2760 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2761 }
2762
2763 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2764 {
2765 /* Address WBINVD may be executed by guest */
2766 if (need_emulate_wbinvd(vcpu)) {
2767 if (kvm_x86_ops->has_wbinvd_exit())
2768 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2769 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2770 smp_call_function_single(vcpu->cpu,
2771 wbinvd_ipi, NULL, 1);
2772 }
2773
2774 kvm_x86_ops->vcpu_load(vcpu, cpu);
2775
2776 /* Apply any externally detected TSC adjustments (due to suspend) */
2777 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2778 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2779 vcpu->arch.tsc_offset_adjustment = 0;
2780 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2781 }
2782
2783 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2784 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2785 rdtsc() - vcpu->arch.last_host_tsc;
2786 if (tsc_delta < 0)
2787 mark_tsc_unstable("KVM discovered backwards TSC");
2788
2789 if (check_tsc_unstable()) {
2790 u64 offset = kvm_compute_tsc_offset(vcpu,
2791 vcpu->arch.last_guest_tsc);
2792 kvm_vcpu_write_tsc_offset(vcpu, offset);
2793 vcpu->arch.tsc_catchup = 1;
2794 }
2795 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2796 kvm_x86_ops->set_hv_timer(vcpu,
2797 kvm_get_lapic_tscdeadline_msr(vcpu)))
2798 kvm_lapic_switch_to_sw_timer(vcpu);
2799 /*
2800 * On a host with synchronized TSC, there is no need to update
2801 * kvmclock on vcpu->cpu migration
2802 */
2803 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2804 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2805 if (vcpu->cpu != cpu)
2806 kvm_migrate_timers(vcpu);
2807 vcpu->cpu = cpu;
2808 }
2809
2810 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2811 }
2812
2813 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2814 {
2815 kvm_x86_ops->vcpu_put(vcpu);
2816 kvm_put_guest_fpu(vcpu);
2817 vcpu->arch.last_host_tsc = rdtsc();
2818 }
2819
2820 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2821 struct kvm_lapic_state *s)
2822 {
2823 if (vcpu->arch.apicv_active)
2824 kvm_x86_ops->sync_pir_to_irr(vcpu);
2825
2826 return kvm_apic_get_state(vcpu, s);
2827 }
2828
2829 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2830 struct kvm_lapic_state *s)
2831 {
2832 int r;
2833
2834 r = kvm_apic_set_state(vcpu, s);
2835 if (r)
2836 return r;
2837 update_cr8_intercept(vcpu);
2838
2839 return 0;
2840 }
2841
2842 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2843 {
2844 return (!lapic_in_kernel(vcpu) ||
2845 kvm_apic_accept_pic_intr(vcpu));
2846 }
2847
2848 /*
2849 * if userspace requested an interrupt window, check that the
2850 * interrupt window is open.
2851 *
2852 * No need to exit to userspace if we already have an interrupt queued.
2853 */
2854 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2855 {
2856 return kvm_arch_interrupt_allowed(vcpu) &&
2857 !kvm_cpu_has_interrupt(vcpu) &&
2858 !kvm_event_needs_reinjection(vcpu) &&
2859 kvm_cpu_accept_dm_intr(vcpu);
2860 }
2861
2862 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2863 struct kvm_interrupt *irq)
2864 {
2865 if (irq->irq >= KVM_NR_INTERRUPTS)
2866 return -EINVAL;
2867
2868 if (!irqchip_in_kernel(vcpu->kvm)) {
2869 kvm_queue_interrupt(vcpu, irq->irq, false);
2870 kvm_make_request(KVM_REQ_EVENT, vcpu);
2871 return 0;
2872 }
2873
2874 /*
2875 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2876 * fail for in-kernel 8259.
2877 */
2878 if (pic_in_kernel(vcpu->kvm))
2879 return -ENXIO;
2880
2881 if (vcpu->arch.pending_external_vector != -1)
2882 return -EEXIST;
2883
2884 vcpu->arch.pending_external_vector = irq->irq;
2885 kvm_make_request(KVM_REQ_EVENT, vcpu);
2886 return 0;
2887 }
2888
2889 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2890 {
2891 kvm_inject_nmi(vcpu);
2892
2893 return 0;
2894 }
2895
2896 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2897 {
2898 kvm_make_request(KVM_REQ_SMI, vcpu);
2899
2900 return 0;
2901 }
2902
2903 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2904 struct kvm_tpr_access_ctl *tac)
2905 {
2906 if (tac->flags)
2907 return -EINVAL;
2908 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2909 return 0;
2910 }
2911
2912 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2913 u64 mcg_cap)
2914 {
2915 int r;
2916 unsigned bank_num = mcg_cap & 0xff, bank;
2917
2918 r = -EINVAL;
2919 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2920 goto out;
2921 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
2922 goto out;
2923 r = 0;
2924 vcpu->arch.mcg_cap = mcg_cap;
2925 /* Init IA32_MCG_CTL to all 1s */
2926 if (mcg_cap & MCG_CTL_P)
2927 vcpu->arch.mcg_ctl = ~(u64)0;
2928 /* Init IA32_MCi_CTL to all 1s */
2929 for (bank = 0; bank < bank_num; bank++)
2930 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2931
2932 if (kvm_x86_ops->setup_mce)
2933 kvm_x86_ops->setup_mce(vcpu);
2934 out:
2935 return r;
2936 }
2937
2938 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2939 struct kvm_x86_mce *mce)
2940 {
2941 u64 mcg_cap = vcpu->arch.mcg_cap;
2942 unsigned bank_num = mcg_cap & 0xff;
2943 u64 *banks = vcpu->arch.mce_banks;
2944
2945 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2946 return -EINVAL;
2947 /*
2948 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2949 * reporting is disabled
2950 */
2951 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2952 vcpu->arch.mcg_ctl != ~(u64)0)
2953 return 0;
2954 banks += 4 * mce->bank;
2955 /*
2956 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2957 * reporting is disabled for the bank
2958 */
2959 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2960 return 0;
2961 if (mce->status & MCI_STATUS_UC) {
2962 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2963 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2964 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2965 return 0;
2966 }
2967 if (banks[1] & MCI_STATUS_VAL)
2968 mce->status |= MCI_STATUS_OVER;
2969 banks[2] = mce->addr;
2970 banks[3] = mce->misc;
2971 vcpu->arch.mcg_status = mce->mcg_status;
2972 banks[1] = mce->status;
2973 kvm_queue_exception(vcpu, MC_VECTOR);
2974 } else if (!(banks[1] & MCI_STATUS_VAL)
2975 || !(banks[1] & MCI_STATUS_UC)) {
2976 if (banks[1] & MCI_STATUS_VAL)
2977 mce->status |= MCI_STATUS_OVER;
2978 banks[2] = mce->addr;
2979 banks[3] = mce->misc;
2980 banks[1] = mce->status;
2981 } else
2982 banks[1] |= MCI_STATUS_OVER;
2983 return 0;
2984 }
2985
2986 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2987 struct kvm_vcpu_events *events)
2988 {
2989 process_nmi(vcpu);
2990 events->exception.injected =
2991 vcpu->arch.exception.pending &&
2992 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2993 events->exception.nr = vcpu->arch.exception.nr;
2994 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2995 events->exception.pad = 0;
2996 events->exception.error_code = vcpu->arch.exception.error_code;
2997
2998 events->interrupt.injected =
2999 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3000 events->interrupt.nr = vcpu->arch.interrupt.nr;
3001 events->interrupt.soft = 0;
3002 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3003
3004 events->nmi.injected = vcpu->arch.nmi_injected;
3005 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3006 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3007 events->nmi.pad = 0;
3008
3009 events->sipi_vector = 0; /* never valid when reporting to user space */
3010
3011 events->smi.smm = is_smm(vcpu);
3012 events->smi.pending = vcpu->arch.smi_pending;
3013 events->smi.smm_inside_nmi =
3014 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3015 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3016
3017 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3018 | KVM_VCPUEVENT_VALID_SHADOW
3019 | KVM_VCPUEVENT_VALID_SMM);
3020 memset(&events->reserved, 0, sizeof(events->reserved));
3021 }
3022
3023 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3024 struct kvm_vcpu_events *events)
3025 {
3026 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3027 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3028 | KVM_VCPUEVENT_VALID_SHADOW
3029 | KVM_VCPUEVENT_VALID_SMM))
3030 return -EINVAL;
3031
3032 if (events->exception.injected &&
3033 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3034 return -EINVAL;
3035
3036 process_nmi(vcpu);
3037 vcpu->arch.exception.pending = events->exception.injected;
3038 vcpu->arch.exception.nr = events->exception.nr;
3039 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3040 vcpu->arch.exception.error_code = events->exception.error_code;
3041
3042 vcpu->arch.interrupt.pending = events->interrupt.injected;
3043 vcpu->arch.interrupt.nr = events->interrupt.nr;
3044 vcpu->arch.interrupt.soft = events->interrupt.soft;
3045 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3046 kvm_x86_ops->set_interrupt_shadow(vcpu,
3047 events->interrupt.shadow);
3048
3049 vcpu->arch.nmi_injected = events->nmi.injected;
3050 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3051 vcpu->arch.nmi_pending = events->nmi.pending;
3052 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3053
3054 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3055 lapic_in_kernel(vcpu))
3056 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3057
3058 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3059 if (events->smi.smm)
3060 vcpu->arch.hflags |= HF_SMM_MASK;
3061 else
3062 vcpu->arch.hflags &= ~HF_SMM_MASK;
3063 vcpu->arch.smi_pending = events->smi.pending;
3064 if (events->smi.smm_inside_nmi)
3065 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3066 else
3067 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3068 if (lapic_in_kernel(vcpu)) {
3069 if (events->smi.latched_init)
3070 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3071 else
3072 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3073 }
3074 }
3075
3076 kvm_make_request(KVM_REQ_EVENT, vcpu);
3077
3078 return 0;
3079 }
3080
3081 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3082 struct kvm_debugregs *dbgregs)
3083 {
3084 unsigned long val;
3085
3086 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3087 kvm_get_dr(vcpu, 6, &val);
3088 dbgregs->dr6 = val;
3089 dbgregs->dr7 = vcpu->arch.dr7;
3090 dbgregs->flags = 0;
3091 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3092 }
3093
3094 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3095 struct kvm_debugregs *dbgregs)
3096 {
3097 if (dbgregs->flags)
3098 return -EINVAL;
3099
3100 if (dbgregs->dr6 & ~0xffffffffull)
3101 return -EINVAL;
3102 if (dbgregs->dr7 & ~0xffffffffull)
3103 return -EINVAL;
3104
3105 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3106 kvm_update_dr0123(vcpu);
3107 vcpu->arch.dr6 = dbgregs->dr6;
3108 kvm_update_dr6(vcpu);
3109 vcpu->arch.dr7 = dbgregs->dr7;
3110 kvm_update_dr7(vcpu);
3111
3112 return 0;
3113 }
3114
3115 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3116
3117 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3118 {
3119 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3120 u64 xstate_bv = xsave->header.xfeatures;
3121 u64 valid;
3122
3123 /*
3124 * Copy legacy XSAVE area, to avoid complications with CPUID
3125 * leaves 0 and 1 in the loop below.
3126 */
3127 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3128
3129 /* Set XSTATE_BV */
3130 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3131
3132 /*
3133 * Copy each region from the possibly compacted offset to the
3134 * non-compacted offset.
3135 */
3136 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3137 while (valid) {
3138 u64 feature = valid & -valid;
3139 int index = fls64(feature) - 1;
3140 void *src = get_xsave_addr(xsave, feature);
3141
3142 if (src) {
3143 u32 size, offset, ecx, edx;
3144 cpuid_count(XSTATE_CPUID, index,
3145 &size, &offset, &ecx, &edx);
3146 memcpy(dest + offset, src, size);
3147 }
3148
3149 valid -= feature;
3150 }
3151 }
3152
3153 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3154 {
3155 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3156 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3157 u64 valid;
3158
3159 /*
3160 * Copy legacy XSAVE area, to avoid complications with CPUID
3161 * leaves 0 and 1 in the loop below.
3162 */
3163 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3164
3165 /* Set XSTATE_BV and possibly XCOMP_BV. */
3166 xsave->header.xfeatures = xstate_bv;
3167 if (boot_cpu_has(X86_FEATURE_XSAVES))
3168 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3169
3170 /*
3171 * Copy each region from the non-compacted offset to the
3172 * possibly compacted offset.
3173 */
3174 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3175 while (valid) {
3176 u64 feature = valid & -valid;
3177 int index = fls64(feature) - 1;
3178 void *dest = get_xsave_addr(xsave, feature);
3179
3180 if (dest) {
3181 u32 size, offset, ecx, edx;
3182 cpuid_count(XSTATE_CPUID, index,
3183 &size, &offset, &ecx, &edx);
3184 memcpy(dest, src + offset, size);
3185 }
3186
3187 valid -= feature;
3188 }
3189 }
3190
3191 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3192 struct kvm_xsave *guest_xsave)
3193 {
3194 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3195 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3196 fill_xsave((u8 *) guest_xsave->region, vcpu);
3197 } else {
3198 memcpy(guest_xsave->region,
3199 &vcpu->arch.guest_fpu.state.fxsave,
3200 sizeof(struct fxregs_state));
3201 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3202 XFEATURE_MASK_FPSSE;
3203 }
3204 }
3205
3206 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3207 struct kvm_xsave *guest_xsave)
3208 {
3209 u64 xstate_bv =
3210 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3211
3212 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3213 /*
3214 * Here we allow setting states that are not present in
3215 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3216 * with old userspace.
3217 */
3218 if (xstate_bv & ~kvm_supported_xcr0())
3219 return -EINVAL;
3220 load_xsave(vcpu, (u8 *)guest_xsave->region);
3221 } else {
3222 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3223 return -EINVAL;
3224 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3225 guest_xsave->region, sizeof(struct fxregs_state));
3226 }
3227 return 0;
3228 }
3229
3230 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3231 struct kvm_xcrs *guest_xcrs)
3232 {
3233 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3234 guest_xcrs->nr_xcrs = 0;
3235 return;
3236 }
3237
3238 guest_xcrs->nr_xcrs = 1;
3239 guest_xcrs->flags = 0;
3240 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3241 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3242 }
3243
3244 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3245 struct kvm_xcrs *guest_xcrs)
3246 {
3247 int i, r = 0;
3248
3249 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3250 return -EINVAL;
3251
3252 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3253 return -EINVAL;
3254
3255 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3256 /* Only support XCR0 currently */
3257 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3258 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3259 guest_xcrs->xcrs[i].value);
3260 break;
3261 }
3262 if (r)
3263 r = -EINVAL;
3264 return r;
3265 }
3266
3267 /*
3268 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3269 * stopped by the hypervisor. This function will be called from the host only.
3270 * EINVAL is returned when the host attempts to set the flag for a guest that
3271 * does not support pv clocks.
3272 */
3273 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3274 {
3275 if (!vcpu->arch.pv_time_enabled)
3276 return -EINVAL;
3277 vcpu->arch.pvclock_set_guest_stopped_request = true;
3278 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3279 return 0;
3280 }
3281
3282 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3283 struct kvm_enable_cap *cap)
3284 {
3285 if (cap->flags)
3286 return -EINVAL;
3287
3288 switch (cap->cap) {
3289 case KVM_CAP_HYPERV_SYNIC:
3290 return kvm_hv_activate_synic(vcpu);
3291 default:
3292 return -EINVAL;
3293 }
3294 }
3295
3296 long kvm_arch_vcpu_ioctl(struct file *filp,
3297 unsigned int ioctl, unsigned long arg)
3298 {
3299 struct kvm_vcpu *vcpu = filp->private_data;
3300 void __user *argp = (void __user *)arg;
3301 int r;
3302 union {
3303 struct kvm_lapic_state *lapic;
3304 struct kvm_xsave *xsave;
3305 struct kvm_xcrs *xcrs;
3306 void *buffer;
3307 } u;
3308
3309 u.buffer = NULL;
3310 switch (ioctl) {
3311 case KVM_GET_LAPIC: {
3312 r = -EINVAL;
3313 if (!lapic_in_kernel(vcpu))
3314 goto out;
3315 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3316
3317 r = -ENOMEM;
3318 if (!u.lapic)
3319 goto out;
3320 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3321 if (r)
3322 goto out;
3323 r = -EFAULT;
3324 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3325 goto out;
3326 r = 0;
3327 break;
3328 }
3329 case KVM_SET_LAPIC: {
3330 r = -EINVAL;
3331 if (!lapic_in_kernel(vcpu))
3332 goto out;
3333 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3334 if (IS_ERR(u.lapic))
3335 return PTR_ERR(u.lapic);
3336
3337 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3338 break;
3339 }
3340 case KVM_INTERRUPT: {
3341 struct kvm_interrupt irq;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&irq, argp, sizeof irq))
3345 goto out;
3346 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3347 break;
3348 }
3349 case KVM_NMI: {
3350 r = kvm_vcpu_ioctl_nmi(vcpu);
3351 break;
3352 }
3353 case KVM_SMI: {
3354 r = kvm_vcpu_ioctl_smi(vcpu);
3355 break;
3356 }
3357 case KVM_SET_CPUID: {
3358 struct kvm_cpuid __user *cpuid_arg = argp;
3359 struct kvm_cpuid cpuid;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3363 goto out;
3364 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3365 break;
3366 }
3367 case KVM_SET_CPUID2: {
3368 struct kvm_cpuid2 __user *cpuid_arg = argp;
3369 struct kvm_cpuid2 cpuid;
3370
3371 r = -EFAULT;
3372 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3373 goto out;
3374 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3375 cpuid_arg->entries);
3376 break;
3377 }
3378 case KVM_GET_CPUID2: {
3379 struct kvm_cpuid2 __user *cpuid_arg = argp;
3380 struct kvm_cpuid2 cpuid;
3381
3382 r = -EFAULT;
3383 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3384 goto out;
3385 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3386 cpuid_arg->entries);
3387 if (r)
3388 goto out;
3389 r = -EFAULT;
3390 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3391 goto out;
3392 r = 0;
3393 break;
3394 }
3395 case KVM_GET_MSRS:
3396 r = msr_io(vcpu, argp, do_get_msr, 1);
3397 break;
3398 case KVM_SET_MSRS:
3399 r = msr_io(vcpu, argp, do_set_msr, 0);
3400 break;
3401 case KVM_TPR_ACCESS_REPORTING: {
3402 struct kvm_tpr_access_ctl tac;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&tac, argp, sizeof tac))
3406 goto out;
3407 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3408 if (r)
3409 goto out;
3410 r = -EFAULT;
3411 if (copy_to_user(argp, &tac, sizeof tac))
3412 goto out;
3413 r = 0;
3414 break;
3415 };
3416 case KVM_SET_VAPIC_ADDR: {
3417 struct kvm_vapic_addr va;
3418
3419 r = -EINVAL;
3420 if (!lapic_in_kernel(vcpu))
3421 goto out;
3422 r = -EFAULT;
3423 if (copy_from_user(&va, argp, sizeof va))
3424 goto out;
3425 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3426 break;
3427 }
3428 case KVM_X86_SETUP_MCE: {
3429 u64 mcg_cap;
3430
3431 r = -EFAULT;
3432 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3433 goto out;
3434 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3435 break;
3436 }
3437 case KVM_X86_SET_MCE: {
3438 struct kvm_x86_mce mce;
3439
3440 r = -EFAULT;
3441 if (copy_from_user(&mce, argp, sizeof mce))
3442 goto out;
3443 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3444 break;
3445 }
3446 case KVM_GET_VCPU_EVENTS: {
3447 struct kvm_vcpu_events events;
3448
3449 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3450
3451 r = -EFAULT;
3452 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3453 break;
3454 r = 0;
3455 break;
3456 }
3457 case KVM_SET_VCPU_EVENTS: {
3458 struct kvm_vcpu_events events;
3459
3460 r = -EFAULT;
3461 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3462 break;
3463
3464 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3465 break;
3466 }
3467 case KVM_GET_DEBUGREGS: {
3468 struct kvm_debugregs dbgregs;
3469
3470 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3471
3472 r = -EFAULT;
3473 if (copy_to_user(argp, &dbgregs,
3474 sizeof(struct kvm_debugregs)))
3475 break;
3476 r = 0;
3477 break;
3478 }
3479 case KVM_SET_DEBUGREGS: {
3480 struct kvm_debugregs dbgregs;
3481
3482 r = -EFAULT;
3483 if (copy_from_user(&dbgregs, argp,
3484 sizeof(struct kvm_debugregs)))
3485 break;
3486
3487 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3488 break;
3489 }
3490 case KVM_GET_XSAVE: {
3491 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3492 r = -ENOMEM;
3493 if (!u.xsave)
3494 break;
3495
3496 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3497
3498 r = -EFAULT;
3499 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3500 break;
3501 r = 0;
3502 break;
3503 }
3504 case KVM_SET_XSAVE: {
3505 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3506 if (IS_ERR(u.xsave))
3507 return PTR_ERR(u.xsave);
3508
3509 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3510 break;
3511 }
3512 case KVM_GET_XCRS: {
3513 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3514 r = -ENOMEM;
3515 if (!u.xcrs)
3516 break;
3517
3518 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3519
3520 r = -EFAULT;
3521 if (copy_to_user(argp, u.xcrs,
3522 sizeof(struct kvm_xcrs)))
3523 break;
3524 r = 0;
3525 break;
3526 }
3527 case KVM_SET_XCRS: {
3528 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3529 if (IS_ERR(u.xcrs))
3530 return PTR_ERR(u.xcrs);
3531
3532 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3533 break;
3534 }
3535 case KVM_SET_TSC_KHZ: {
3536 u32 user_tsc_khz;
3537
3538 r = -EINVAL;
3539 user_tsc_khz = (u32)arg;
3540
3541 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3542 goto out;
3543
3544 if (user_tsc_khz == 0)
3545 user_tsc_khz = tsc_khz;
3546
3547 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3548 r = 0;
3549
3550 goto out;
3551 }
3552 case KVM_GET_TSC_KHZ: {
3553 r = vcpu->arch.virtual_tsc_khz;
3554 goto out;
3555 }
3556 case KVM_KVMCLOCK_CTRL: {
3557 r = kvm_set_guest_paused(vcpu);
3558 goto out;
3559 }
3560 case KVM_ENABLE_CAP: {
3561 struct kvm_enable_cap cap;
3562
3563 r = -EFAULT;
3564 if (copy_from_user(&cap, argp, sizeof(cap)))
3565 goto out;
3566 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3567 break;
3568 }
3569 default:
3570 r = -EINVAL;
3571 }
3572 out:
3573 kfree(u.buffer);
3574 return r;
3575 }
3576
3577 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3578 {
3579 return VM_FAULT_SIGBUS;
3580 }
3581
3582 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3583 {
3584 int ret;
3585
3586 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3587 return -EINVAL;
3588 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3589 return ret;
3590 }
3591
3592 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3593 u64 ident_addr)
3594 {
3595 kvm->arch.ept_identity_map_addr = ident_addr;
3596 return 0;
3597 }
3598
3599 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3600 u32 kvm_nr_mmu_pages)
3601 {
3602 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3603 return -EINVAL;
3604
3605 mutex_lock(&kvm->slots_lock);
3606
3607 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3608 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3609
3610 mutex_unlock(&kvm->slots_lock);
3611 return 0;
3612 }
3613
3614 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3615 {
3616 return kvm->arch.n_max_mmu_pages;
3617 }
3618
3619 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3620 {
3621 int r;
3622
3623 r = 0;
3624 switch (chip->chip_id) {
3625 case KVM_IRQCHIP_PIC_MASTER:
3626 memcpy(&chip->chip.pic,
3627 &pic_irqchip(kvm)->pics[0],
3628 sizeof(struct kvm_pic_state));
3629 break;
3630 case KVM_IRQCHIP_PIC_SLAVE:
3631 memcpy(&chip->chip.pic,
3632 &pic_irqchip(kvm)->pics[1],
3633 sizeof(struct kvm_pic_state));
3634 break;
3635 case KVM_IRQCHIP_IOAPIC:
3636 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3637 break;
3638 default:
3639 r = -EINVAL;
3640 break;
3641 }
3642 return r;
3643 }
3644
3645 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3646 {
3647 int r;
3648
3649 r = 0;
3650 switch (chip->chip_id) {
3651 case KVM_IRQCHIP_PIC_MASTER:
3652 spin_lock(&pic_irqchip(kvm)->lock);
3653 memcpy(&pic_irqchip(kvm)->pics[0],
3654 &chip->chip.pic,
3655 sizeof(struct kvm_pic_state));
3656 spin_unlock(&pic_irqchip(kvm)->lock);
3657 break;
3658 case KVM_IRQCHIP_PIC_SLAVE:
3659 spin_lock(&pic_irqchip(kvm)->lock);
3660 memcpy(&pic_irqchip(kvm)->pics[1],
3661 &chip->chip.pic,
3662 sizeof(struct kvm_pic_state));
3663 spin_unlock(&pic_irqchip(kvm)->lock);
3664 break;
3665 case KVM_IRQCHIP_IOAPIC:
3666 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3667 break;
3668 default:
3669 r = -EINVAL;
3670 break;
3671 }
3672 kvm_pic_update_irq(pic_irqchip(kvm));
3673 return r;
3674 }
3675
3676 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3677 {
3678 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3679
3680 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3681
3682 mutex_lock(&kps->lock);
3683 memcpy(ps, &kps->channels, sizeof(*ps));
3684 mutex_unlock(&kps->lock);
3685 return 0;
3686 }
3687
3688 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3689 {
3690 int i;
3691 struct kvm_pit *pit = kvm->arch.vpit;
3692
3693 mutex_lock(&pit->pit_state.lock);
3694 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3695 for (i = 0; i < 3; i++)
3696 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3697 mutex_unlock(&pit->pit_state.lock);
3698 return 0;
3699 }
3700
3701 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3702 {
3703 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3704 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3705 sizeof(ps->channels));
3706 ps->flags = kvm->arch.vpit->pit_state.flags;
3707 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3708 memset(&ps->reserved, 0, sizeof(ps->reserved));
3709 return 0;
3710 }
3711
3712 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3713 {
3714 int start = 0;
3715 int i;
3716 u32 prev_legacy, cur_legacy;
3717 struct kvm_pit *pit = kvm->arch.vpit;
3718
3719 mutex_lock(&pit->pit_state.lock);
3720 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3721 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3722 if (!prev_legacy && cur_legacy)
3723 start = 1;
3724 memcpy(&pit->pit_state.channels, &ps->channels,
3725 sizeof(pit->pit_state.channels));
3726 pit->pit_state.flags = ps->flags;
3727 for (i = 0; i < 3; i++)
3728 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3729 start && i == 0);
3730 mutex_unlock(&pit->pit_state.lock);
3731 return 0;
3732 }
3733
3734 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3735 struct kvm_reinject_control *control)
3736 {
3737 struct kvm_pit *pit = kvm->arch.vpit;
3738
3739 if (!pit)
3740 return -ENXIO;
3741
3742 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3743 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3744 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3745 */
3746 mutex_lock(&pit->pit_state.lock);
3747 kvm_pit_set_reinject(pit, control->pit_reinject);
3748 mutex_unlock(&pit->pit_state.lock);
3749
3750 return 0;
3751 }
3752
3753 /**
3754 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3755 * @kvm: kvm instance
3756 * @log: slot id and address to which we copy the log
3757 *
3758 * Steps 1-4 below provide general overview of dirty page logging. See
3759 * kvm_get_dirty_log_protect() function description for additional details.
3760 *
3761 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3762 * always flush the TLB (step 4) even if previous step failed and the dirty
3763 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3764 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3765 * writes will be marked dirty for next log read.
3766 *
3767 * 1. Take a snapshot of the bit and clear it if needed.
3768 * 2. Write protect the corresponding page.
3769 * 3. Copy the snapshot to the userspace.
3770 * 4. Flush TLB's if needed.
3771 */
3772 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3773 {
3774 bool is_dirty = false;
3775 int r;
3776
3777 mutex_lock(&kvm->slots_lock);
3778
3779 /*
3780 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3781 */
3782 if (kvm_x86_ops->flush_log_dirty)
3783 kvm_x86_ops->flush_log_dirty(kvm);
3784
3785 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3786
3787 /*
3788 * All the TLBs can be flushed out of mmu lock, see the comments in
3789 * kvm_mmu_slot_remove_write_access().
3790 */
3791 lockdep_assert_held(&kvm->slots_lock);
3792 if (is_dirty)
3793 kvm_flush_remote_tlbs(kvm);
3794
3795 mutex_unlock(&kvm->slots_lock);
3796 return r;
3797 }
3798
3799 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3800 bool line_status)
3801 {
3802 if (!irqchip_in_kernel(kvm))
3803 return -ENXIO;
3804
3805 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3806 irq_event->irq, irq_event->level,
3807 line_status);
3808 return 0;
3809 }
3810
3811 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3812 struct kvm_enable_cap *cap)
3813 {
3814 int r;
3815
3816 if (cap->flags)
3817 return -EINVAL;
3818
3819 switch (cap->cap) {
3820 case KVM_CAP_DISABLE_QUIRKS:
3821 kvm->arch.disabled_quirks = cap->args[0];
3822 r = 0;
3823 break;
3824 case KVM_CAP_SPLIT_IRQCHIP: {
3825 mutex_lock(&kvm->lock);
3826 r = -EINVAL;
3827 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3828 goto split_irqchip_unlock;
3829 r = -EEXIST;
3830 if (irqchip_in_kernel(kvm))
3831 goto split_irqchip_unlock;
3832 if (kvm->created_vcpus)
3833 goto split_irqchip_unlock;
3834 r = kvm_setup_empty_irq_routing(kvm);
3835 if (r)
3836 goto split_irqchip_unlock;
3837 /* Pairs with irqchip_in_kernel. */
3838 smp_wmb();
3839 kvm->arch.irqchip_split = true;
3840 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3841 r = 0;
3842 split_irqchip_unlock:
3843 mutex_unlock(&kvm->lock);
3844 break;
3845 }
3846 case KVM_CAP_X2APIC_API:
3847 r = -EINVAL;
3848 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3849 break;
3850
3851 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3852 kvm->arch.x2apic_format = true;
3853 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3854 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3855
3856 r = 0;
3857 break;
3858 default:
3859 r = -EINVAL;
3860 break;
3861 }
3862 return r;
3863 }
3864
3865 long kvm_arch_vm_ioctl(struct file *filp,
3866 unsigned int ioctl, unsigned long arg)
3867 {
3868 struct kvm *kvm = filp->private_data;
3869 void __user *argp = (void __user *)arg;
3870 int r = -ENOTTY;
3871 /*
3872 * This union makes it completely explicit to gcc-3.x
3873 * that these two variables' stack usage should be
3874 * combined, not added together.
3875 */
3876 union {
3877 struct kvm_pit_state ps;
3878 struct kvm_pit_state2 ps2;
3879 struct kvm_pit_config pit_config;
3880 } u;
3881
3882 switch (ioctl) {
3883 case KVM_SET_TSS_ADDR:
3884 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3885 break;
3886 case KVM_SET_IDENTITY_MAP_ADDR: {
3887 u64 ident_addr;
3888
3889 r = -EFAULT;
3890 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3891 goto out;
3892 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3893 break;
3894 }
3895 case KVM_SET_NR_MMU_PAGES:
3896 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3897 break;
3898 case KVM_GET_NR_MMU_PAGES:
3899 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3900 break;
3901 case KVM_CREATE_IRQCHIP: {
3902 struct kvm_pic *vpic;
3903
3904 mutex_lock(&kvm->lock);
3905 r = -EEXIST;
3906 if (kvm->arch.vpic)
3907 goto create_irqchip_unlock;
3908 r = -EINVAL;
3909 if (kvm->created_vcpus)
3910 goto create_irqchip_unlock;
3911 r = -ENOMEM;
3912 vpic = kvm_create_pic(kvm);
3913 if (vpic) {
3914 r = kvm_ioapic_init(kvm);
3915 if (r) {
3916 mutex_lock(&kvm->slots_lock);
3917 kvm_destroy_pic(vpic);
3918 mutex_unlock(&kvm->slots_lock);
3919 goto create_irqchip_unlock;
3920 }
3921 } else
3922 goto create_irqchip_unlock;
3923 r = kvm_setup_default_irq_routing(kvm);
3924 if (r) {
3925 mutex_lock(&kvm->slots_lock);
3926 mutex_lock(&kvm->irq_lock);
3927 kvm_ioapic_destroy(kvm);
3928 kvm_destroy_pic(vpic);
3929 mutex_unlock(&kvm->irq_lock);
3930 mutex_unlock(&kvm->slots_lock);
3931 goto create_irqchip_unlock;
3932 }
3933 /* Write kvm->irq_routing before kvm->arch.vpic. */
3934 smp_wmb();
3935 kvm->arch.vpic = vpic;
3936 create_irqchip_unlock:
3937 mutex_unlock(&kvm->lock);
3938 break;
3939 }
3940 case KVM_CREATE_PIT:
3941 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3942 goto create_pit;
3943 case KVM_CREATE_PIT2:
3944 r = -EFAULT;
3945 if (copy_from_user(&u.pit_config, argp,
3946 sizeof(struct kvm_pit_config)))
3947 goto out;
3948 create_pit:
3949 mutex_lock(&kvm->lock);
3950 r = -EEXIST;
3951 if (kvm->arch.vpit)
3952 goto create_pit_unlock;
3953 r = -ENOMEM;
3954 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3955 if (kvm->arch.vpit)
3956 r = 0;
3957 create_pit_unlock:
3958 mutex_unlock(&kvm->lock);
3959 break;
3960 case KVM_GET_IRQCHIP: {
3961 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3962 struct kvm_irqchip *chip;
3963
3964 chip = memdup_user(argp, sizeof(*chip));
3965 if (IS_ERR(chip)) {
3966 r = PTR_ERR(chip);
3967 goto out;
3968 }
3969
3970 r = -ENXIO;
3971 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3972 goto get_irqchip_out;
3973 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3974 if (r)
3975 goto get_irqchip_out;
3976 r = -EFAULT;
3977 if (copy_to_user(argp, chip, sizeof *chip))
3978 goto get_irqchip_out;
3979 r = 0;
3980 get_irqchip_out:
3981 kfree(chip);
3982 break;
3983 }
3984 case KVM_SET_IRQCHIP: {
3985 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3986 struct kvm_irqchip *chip;
3987
3988 chip = memdup_user(argp, sizeof(*chip));
3989 if (IS_ERR(chip)) {
3990 r = PTR_ERR(chip);
3991 goto out;
3992 }
3993
3994 r = -ENXIO;
3995 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3996 goto set_irqchip_out;
3997 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3998 if (r)
3999 goto set_irqchip_out;
4000 r = 0;
4001 set_irqchip_out:
4002 kfree(chip);
4003 break;
4004 }
4005 case KVM_GET_PIT: {
4006 r = -EFAULT;
4007 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4008 goto out;
4009 r = -ENXIO;
4010 if (!kvm->arch.vpit)
4011 goto out;
4012 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4013 if (r)
4014 goto out;
4015 r = -EFAULT;
4016 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4017 goto out;
4018 r = 0;
4019 break;
4020 }
4021 case KVM_SET_PIT: {
4022 r = -EFAULT;
4023 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4024 goto out;
4025 r = -ENXIO;
4026 if (!kvm->arch.vpit)
4027 goto out;
4028 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4029 break;
4030 }
4031 case KVM_GET_PIT2: {
4032 r = -ENXIO;
4033 if (!kvm->arch.vpit)
4034 goto out;
4035 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4036 if (r)
4037 goto out;
4038 r = -EFAULT;
4039 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4040 goto out;
4041 r = 0;
4042 break;
4043 }
4044 case KVM_SET_PIT2: {
4045 r = -EFAULT;
4046 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4047 goto out;
4048 r = -ENXIO;
4049 if (!kvm->arch.vpit)
4050 goto out;
4051 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4052 break;
4053 }
4054 case KVM_REINJECT_CONTROL: {
4055 struct kvm_reinject_control control;
4056 r = -EFAULT;
4057 if (copy_from_user(&control, argp, sizeof(control)))
4058 goto out;
4059 r = kvm_vm_ioctl_reinject(kvm, &control);
4060 break;
4061 }
4062 case KVM_SET_BOOT_CPU_ID:
4063 r = 0;
4064 mutex_lock(&kvm->lock);
4065 if (kvm->created_vcpus)
4066 r = -EBUSY;
4067 else
4068 kvm->arch.bsp_vcpu_id = arg;
4069 mutex_unlock(&kvm->lock);
4070 break;
4071 case KVM_XEN_HVM_CONFIG: {
4072 r = -EFAULT;
4073 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4074 sizeof(struct kvm_xen_hvm_config)))
4075 goto out;
4076 r = -EINVAL;
4077 if (kvm->arch.xen_hvm_config.flags)
4078 goto out;
4079 r = 0;
4080 break;
4081 }
4082 case KVM_SET_CLOCK: {
4083 struct kvm_clock_data user_ns;
4084 u64 now_ns;
4085
4086 r = -EFAULT;
4087 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4088 goto out;
4089
4090 r = -EINVAL;
4091 if (user_ns.flags)
4092 goto out;
4093
4094 r = 0;
4095 local_irq_disable();
4096 now_ns = __get_kvmclock_ns(kvm);
4097 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4098 local_irq_enable();
4099 kvm_gen_update_masterclock(kvm);
4100 break;
4101 }
4102 case KVM_GET_CLOCK: {
4103 struct kvm_clock_data user_ns;
4104 u64 now_ns;
4105
4106 now_ns = get_kvmclock_ns(kvm);
4107 user_ns.clock = now_ns;
4108 user_ns.flags = 0;
4109 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4110
4111 r = -EFAULT;
4112 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4113 goto out;
4114 r = 0;
4115 break;
4116 }
4117 case KVM_ENABLE_CAP: {
4118 struct kvm_enable_cap cap;
4119
4120 r = -EFAULT;
4121 if (copy_from_user(&cap, argp, sizeof(cap)))
4122 goto out;
4123 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4124 break;
4125 }
4126 default:
4127 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4128 }
4129 out:
4130 return r;
4131 }
4132
4133 static void kvm_init_msr_list(void)
4134 {
4135 u32 dummy[2];
4136 unsigned i, j;
4137
4138 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4139 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4140 continue;
4141
4142 /*
4143 * Even MSRs that are valid in the host may not be exposed
4144 * to the guests in some cases.
4145 */
4146 switch (msrs_to_save[i]) {
4147 case MSR_IA32_BNDCFGS:
4148 if (!kvm_x86_ops->mpx_supported())
4149 continue;
4150 break;
4151 case MSR_TSC_AUX:
4152 if (!kvm_x86_ops->rdtscp_supported())
4153 continue;
4154 break;
4155 default:
4156 break;
4157 }
4158
4159 if (j < i)
4160 msrs_to_save[j] = msrs_to_save[i];
4161 j++;
4162 }
4163 num_msrs_to_save = j;
4164
4165 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4166 switch (emulated_msrs[i]) {
4167 case MSR_IA32_SMBASE:
4168 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4169 continue;
4170 break;
4171 default:
4172 break;
4173 }
4174
4175 if (j < i)
4176 emulated_msrs[j] = emulated_msrs[i];
4177 j++;
4178 }
4179 num_emulated_msrs = j;
4180 }
4181
4182 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4183 const void *v)
4184 {
4185 int handled = 0;
4186 int n;
4187
4188 do {
4189 n = min(len, 8);
4190 if (!(lapic_in_kernel(vcpu) &&
4191 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4192 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4193 break;
4194 handled += n;
4195 addr += n;
4196 len -= n;
4197 v += n;
4198 } while (len);
4199
4200 return handled;
4201 }
4202
4203 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4204 {
4205 int handled = 0;
4206 int n;
4207
4208 do {
4209 n = min(len, 8);
4210 if (!(lapic_in_kernel(vcpu) &&
4211 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4212 addr, n, v))
4213 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4214 break;
4215 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4216 handled += n;
4217 addr += n;
4218 len -= n;
4219 v += n;
4220 } while (len);
4221
4222 return handled;
4223 }
4224
4225 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4226 struct kvm_segment *var, int seg)
4227 {
4228 kvm_x86_ops->set_segment(vcpu, var, seg);
4229 }
4230
4231 void kvm_get_segment(struct kvm_vcpu *vcpu,
4232 struct kvm_segment *var, int seg)
4233 {
4234 kvm_x86_ops->get_segment(vcpu, var, seg);
4235 }
4236
4237 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4238 struct x86_exception *exception)
4239 {
4240 gpa_t t_gpa;
4241
4242 BUG_ON(!mmu_is_nested(vcpu));
4243
4244 /* NPT walks are always user-walks */
4245 access |= PFERR_USER_MASK;
4246 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4247
4248 return t_gpa;
4249 }
4250
4251 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4252 struct x86_exception *exception)
4253 {
4254 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4255 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4256 }
4257
4258 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4259 struct x86_exception *exception)
4260 {
4261 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4262 access |= PFERR_FETCH_MASK;
4263 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4264 }
4265
4266 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4267 struct x86_exception *exception)
4268 {
4269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4270 access |= PFERR_WRITE_MASK;
4271 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4272 }
4273
4274 /* uses this to access any guest's mapped memory without checking CPL */
4275 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4276 struct x86_exception *exception)
4277 {
4278 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4279 }
4280
4281 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4282 struct kvm_vcpu *vcpu, u32 access,
4283 struct x86_exception *exception)
4284 {
4285 void *data = val;
4286 int r = X86EMUL_CONTINUE;
4287
4288 while (bytes) {
4289 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4290 exception);
4291 unsigned offset = addr & (PAGE_SIZE-1);
4292 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4293 int ret;
4294
4295 if (gpa == UNMAPPED_GVA)
4296 return X86EMUL_PROPAGATE_FAULT;
4297 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4298 offset, toread);
4299 if (ret < 0) {
4300 r = X86EMUL_IO_NEEDED;
4301 goto out;
4302 }
4303
4304 bytes -= toread;
4305 data += toread;
4306 addr += toread;
4307 }
4308 out:
4309 return r;
4310 }
4311
4312 /* used for instruction fetching */
4313 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4314 gva_t addr, void *val, unsigned int bytes,
4315 struct x86_exception *exception)
4316 {
4317 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4318 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4319 unsigned offset;
4320 int ret;
4321
4322 /* Inline kvm_read_guest_virt_helper for speed. */
4323 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4324 exception);
4325 if (unlikely(gpa == UNMAPPED_GVA))
4326 return X86EMUL_PROPAGATE_FAULT;
4327
4328 offset = addr & (PAGE_SIZE-1);
4329 if (WARN_ON(offset + bytes > PAGE_SIZE))
4330 bytes = (unsigned)PAGE_SIZE - offset;
4331 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4332 offset, bytes);
4333 if (unlikely(ret < 0))
4334 return X86EMUL_IO_NEEDED;
4335
4336 return X86EMUL_CONTINUE;
4337 }
4338
4339 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4340 gva_t addr, void *val, unsigned int bytes,
4341 struct x86_exception *exception)
4342 {
4343 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4345
4346 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4347 exception);
4348 }
4349 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4350
4351 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4352 gva_t addr, void *val, unsigned int bytes,
4353 struct x86_exception *exception)
4354 {
4355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4356 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4357 }
4358
4359 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4360 unsigned long addr, void *val, unsigned int bytes)
4361 {
4362 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4363 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4364
4365 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4366 }
4367
4368 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4369 gva_t addr, void *val,
4370 unsigned int bytes,
4371 struct x86_exception *exception)
4372 {
4373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4374 void *data = val;
4375 int r = X86EMUL_CONTINUE;
4376
4377 while (bytes) {
4378 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4379 PFERR_WRITE_MASK,
4380 exception);
4381 unsigned offset = addr & (PAGE_SIZE-1);
4382 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4383 int ret;
4384
4385 if (gpa == UNMAPPED_GVA)
4386 return X86EMUL_PROPAGATE_FAULT;
4387 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4388 if (ret < 0) {
4389 r = X86EMUL_IO_NEEDED;
4390 goto out;
4391 }
4392
4393 bytes -= towrite;
4394 data += towrite;
4395 addr += towrite;
4396 }
4397 out:
4398 return r;
4399 }
4400 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4401
4402 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4403 gpa_t *gpa, struct x86_exception *exception,
4404 bool write)
4405 {
4406 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4407 | (write ? PFERR_WRITE_MASK : 0);
4408
4409 /*
4410 * currently PKRU is only applied to ept enabled guest so
4411 * there is no pkey in EPT page table for L1 guest or EPT
4412 * shadow page table for L2 guest.
4413 */
4414 if (vcpu_match_mmio_gva(vcpu, gva)
4415 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4416 vcpu->arch.access, 0, access)) {
4417 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4418 (gva & (PAGE_SIZE - 1));
4419 trace_vcpu_match_mmio(gva, *gpa, write, false);
4420 return 1;
4421 }
4422
4423 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4424
4425 if (*gpa == UNMAPPED_GVA)
4426 return -1;
4427
4428 /* For APIC access vmexit */
4429 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4430 return 1;
4431
4432 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4433 trace_vcpu_match_mmio(gva, *gpa, write, true);
4434 return 1;
4435 }
4436
4437 return 0;
4438 }
4439
4440 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4441 const void *val, int bytes)
4442 {
4443 int ret;
4444
4445 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4446 if (ret < 0)
4447 return 0;
4448 kvm_page_track_write(vcpu, gpa, val, bytes);
4449 return 1;
4450 }
4451
4452 struct read_write_emulator_ops {
4453 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4454 int bytes);
4455 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4456 void *val, int bytes);
4457 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4458 int bytes, void *val);
4459 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4460 void *val, int bytes);
4461 bool write;
4462 };
4463
4464 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4465 {
4466 if (vcpu->mmio_read_completed) {
4467 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4468 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4469 vcpu->mmio_read_completed = 0;
4470 return 1;
4471 }
4472
4473 return 0;
4474 }
4475
4476 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4477 void *val, int bytes)
4478 {
4479 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4480 }
4481
4482 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4483 void *val, int bytes)
4484 {
4485 return emulator_write_phys(vcpu, gpa, val, bytes);
4486 }
4487
4488 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4489 {
4490 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4491 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4492 }
4493
4494 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4495 void *val, int bytes)
4496 {
4497 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4498 return X86EMUL_IO_NEEDED;
4499 }
4500
4501 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4502 void *val, int bytes)
4503 {
4504 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4505
4506 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4507 return X86EMUL_CONTINUE;
4508 }
4509
4510 static const struct read_write_emulator_ops read_emultor = {
4511 .read_write_prepare = read_prepare,
4512 .read_write_emulate = read_emulate,
4513 .read_write_mmio = vcpu_mmio_read,
4514 .read_write_exit_mmio = read_exit_mmio,
4515 };
4516
4517 static const struct read_write_emulator_ops write_emultor = {
4518 .read_write_emulate = write_emulate,
4519 .read_write_mmio = write_mmio,
4520 .read_write_exit_mmio = write_exit_mmio,
4521 .write = true,
4522 };
4523
4524 static int emulator_read_write_onepage(unsigned long addr, void *val,
4525 unsigned int bytes,
4526 struct x86_exception *exception,
4527 struct kvm_vcpu *vcpu,
4528 const struct read_write_emulator_ops *ops)
4529 {
4530 gpa_t gpa;
4531 int handled, ret;
4532 bool write = ops->write;
4533 struct kvm_mmio_fragment *frag;
4534
4535 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4536
4537 if (ret < 0)
4538 return X86EMUL_PROPAGATE_FAULT;
4539
4540 /* For APIC access vmexit */
4541 if (ret)
4542 goto mmio;
4543
4544 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4545 return X86EMUL_CONTINUE;
4546
4547 mmio:
4548 /*
4549 * Is this MMIO handled locally?
4550 */
4551 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4552 if (handled == bytes)
4553 return X86EMUL_CONTINUE;
4554
4555 gpa += handled;
4556 bytes -= handled;
4557 val += handled;
4558
4559 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4560 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4561 frag->gpa = gpa;
4562 frag->data = val;
4563 frag->len = bytes;
4564 return X86EMUL_CONTINUE;
4565 }
4566
4567 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4568 unsigned long addr,
4569 void *val, unsigned int bytes,
4570 struct x86_exception *exception,
4571 const struct read_write_emulator_ops *ops)
4572 {
4573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4574 gpa_t gpa;
4575 int rc;
4576
4577 if (ops->read_write_prepare &&
4578 ops->read_write_prepare(vcpu, val, bytes))
4579 return X86EMUL_CONTINUE;
4580
4581 vcpu->mmio_nr_fragments = 0;
4582
4583 /* Crossing a page boundary? */
4584 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4585 int now;
4586
4587 now = -addr & ~PAGE_MASK;
4588 rc = emulator_read_write_onepage(addr, val, now, exception,
4589 vcpu, ops);
4590
4591 if (rc != X86EMUL_CONTINUE)
4592 return rc;
4593 addr += now;
4594 if (ctxt->mode != X86EMUL_MODE_PROT64)
4595 addr = (u32)addr;
4596 val += now;
4597 bytes -= now;
4598 }
4599
4600 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4601 vcpu, ops);
4602 if (rc != X86EMUL_CONTINUE)
4603 return rc;
4604
4605 if (!vcpu->mmio_nr_fragments)
4606 return rc;
4607
4608 gpa = vcpu->mmio_fragments[0].gpa;
4609
4610 vcpu->mmio_needed = 1;
4611 vcpu->mmio_cur_fragment = 0;
4612
4613 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4614 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4615 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4616 vcpu->run->mmio.phys_addr = gpa;
4617
4618 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4619 }
4620
4621 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4622 unsigned long addr,
4623 void *val,
4624 unsigned int bytes,
4625 struct x86_exception *exception)
4626 {
4627 return emulator_read_write(ctxt, addr, val, bytes,
4628 exception, &read_emultor);
4629 }
4630
4631 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4632 unsigned long addr,
4633 const void *val,
4634 unsigned int bytes,
4635 struct x86_exception *exception)
4636 {
4637 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4638 exception, &write_emultor);
4639 }
4640
4641 #define CMPXCHG_TYPE(t, ptr, old, new) \
4642 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4643
4644 #ifdef CONFIG_X86_64
4645 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4646 #else
4647 # define CMPXCHG64(ptr, old, new) \
4648 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4649 #endif
4650
4651 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4652 unsigned long addr,
4653 const void *old,
4654 const void *new,
4655 unsigned int bytes,
4656 struct x86_exception *exception)
4657 {
4658 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4659 gpa_t gpa;
4660 struct page *page;
4661 char *kaddr;
4662 bool exchanged;
4663
4664 /* guests cmpxchg8b have to be emulated atomically */
4665 if (bytes > 8 || (bytes & (bytes - 1)))
4666 goto emul_write;
4667
4668 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4669
4670 if (gpa == UNMAPPED_GVA ||
4671 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4672 goto emul_write;
4673
4674 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4675 goto emul_write;
4676
4677 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4678 if (is_error_page(page))
4679 goto emul_write;
4680
4681 kaddr = kmap_atomic(page);
4682 kaddr += offset_in_page(gpa);
4683 switch (bytes) {
4684 case 1:
4685 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4686 break;
4687 case 2:
4688 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4689 break;
4690 case 4:
4691 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4692 break;
4693 case 8:
4694 exchanged = CMPXCHG64(kaddr, old, new);
4695 break;
4696 default:
4697 BUG();
4698 }
4699 kunmap_atomic(kaddr);
4700 kvm_release_page_dirty(page);
4701
4702 if (!exchanged)
4703 return X86EMUL_CMPXCHG_FAILED;
4704
4705 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4706 kvm_page_track_write(vcpu, gpa, new, bytes);
4707
4708 return X86EMUL_CONTINUE;
4709
4710 emul_write:
4711 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4712
4713 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4714 }
4715
4716 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4717 {
4718 /* TODO: String I/O for in kernel device */
4719 int r;
4720
4721 if (vcpu->arch.pio.in)
4722 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4723 vcpu->arch.pio.size, pd);
4724 else
4725 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4726 vcpu->arch.pio.port, vcpu->arch.pio.size,
4727 pd);
4728 return r;
4729 }
4730
4731 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4732 unsigned short port, void *val,
4733 unsigned int count, bool in)
4734 {
4735 vcpu->arch.pio.port = port;
4736 vcpu->arch.pio.in = in;
4737 vcpu->arch.pio.count = count;
4738 vcpu->arch.pio.size = size;
4739
4740 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4741 vcpu->arch.pio.count = 0;
4742 return 1;
4743 }
4744
4745 vcpu->run->exit_reason = KVM_EXIT_IO;
4746 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4747 vcpu->run->io.size = size;
4748 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4749 vcpu->run->io.count = count;
4750 vcpu->run->io.port = port;
4751
4752 return 0;
4753 }
4754
4755 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4756 int size, unsigned short port, void *val,
4757 unsigned int count)
4758 {
4759 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4760 int ret;
4761
4762 if (vcpu->arch.pio.count)
4763 goto data_avail;
4764
4765 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4766 if (ret) {
4767 data_avail:
4768 memcpy(val, vcpu->arch.pio_data, size * count);
4769 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4770 vcpu->arch.pio.count = 0;
4771 return 1;
4772 }
4773
4774 return 0;
4775 }
4776
4777 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4778 int size, unsigned short port,
4779 const void *val, unsigned int count)
4780 {
4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782
4783 memcpy(vcpu->arch.pio_data, val, size * count);
4784 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4785 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4786 }
4787
4788 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4789 {
4790 return kvm_x86_ops->get_segment_base(vcpu, seg);
4791 }
4792
4793 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4794 {
4795 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4796 }
4797
4798 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4799 {
4800 if (!need_emulate_wbinvd(vcpu))
4801 return X86EMUL_CONTINUE;
4802
4803 if (kvm_x86_ops->has_wbinvd_exit()) {
4804 int cpu = get_cpu();
4805
4806 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4807 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4808 wbinvd_ipi, NULL, 1);
4809 put_cpu();
4810 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4811 } else
4812 wbinvd();
4813 return X86EMUL_CONTINUE;
4814 }
4815
4816 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4817 {
4818 kvm_x86_ops->skip_emulated_instruction(vcpu);
4819 return kvm_emulate_wbinvd_noskip(vcpu);
4820 }
4821 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4822
4823
4824
4825 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4826 {
4827 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4828 }
4829
4830 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4831 unsigned long *dest)
4832 {
4833 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4834 }
4835
4836 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4837 unsigned long value)
4838 {
4839
4840 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4841 }
4842
4843 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4844 {
4845 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4846 }
4847
4848 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4849 {
4850 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4851 unsigned long value;
4852
4853 switch (cr) {
4854 case 0:
4855 value = kvm_read_cr0(vcpu);
4856 break;
4857 case 2:
4858 value = vcpu->arch.cr2;
4859 break;
4860 case 3:
4861 value = kvm_read_cr3(vcpu);
4862 break;
4863 case 4:
4864 value = kvm_read_cr4(vcpu);
4865 break;
4866 case 8:
4867 value = kvm_get_cr8(vcpu);
4868 break;
4869 default:
4870 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4871 return 0;
4872 }
4873
4874 return value;
4875 }
4876
4877 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4878 {
4879 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4880 int res = 0;
4881
4882 switch (cr) {
4883 case 0:
4884 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4885 break;
4886 case 2:
4887 vcpu->arch.cr2 = val;
4888 break;
4889 case 3:
4890 res = kvm_set_cr3(vcpu, val);
4891 break;
4892 case 4:
4893 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4894 break;
4895 case 8:
4896 res = kvm_set_cr8(vcpu, val);
4897 break;
4898 default:
4899 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4900 res = -1;
4901 }
4902
4903 return res;
4904 }
4905
4906 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4907 {
4908 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4909 }
4910
4911 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4912 {
4913 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4914 }
4915
4916 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4917 {
4918 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4919 }
4920
4921 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4922 {
4923 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4924 }
4925
4926 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4927 {
4928 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4929 }
4930
4931 static unsigned long emulator_get_cached_segment_base(
4932 struct x86_emulate_ctxt *ctxt, int seg)
4933 {
4934 return get_segment_base(emul_to_vcpu(ctxt), seg);
4935 }
4936
4937 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4938 struct desc_struct *desc, u32 *base3,
4939 int seg)
4940 {
4941 struct kvm_segment var;
4942
4943 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4944 *selector = var.selector;
4945
4946 if (var.unusable) {
4947 memset(desc, 0, sizeof(*desc));
4948 return false;
4949 }
4950
4951 if (var.g)
4952 var.limit >>= 12;
4953 set_desc_limit(desc, var.limit);
4954 set_desc_base(desc, (unsigned long)var.base);
4955 #ifdef CONFIG_X86_64
4956 if (base3)
4957 *base3 = var.base >> 32;
4958 #endif
4959 desc->type = var.type;
4960 desc->s = var.s;
4961 desc->dpl = var.dpl;
4962 desc->p = var.present;
4963 desc->avl = var.avl;
4964 desc->l = var.l;
4965 desc->d = var.db;
4966 desc->g = var.g;
4967
4968 return true;
4969 }
4970
4971 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4972 struct desc_struct *desc, u32 base3,
4973 int seg)
4974 {
4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4976 struct kvm_segment var;
4977
4978 var.selector = selector;
4979 var.base = get_desc_base(desc);
4980 #ifdef CONFIG_X86_64
4981 var.base |= ((u64)base3) << 32;
4982 #endif
4983 var.limit = get_desc_limit(desc);
4984 if (desc->g)
4985 var.limit = (var.limit << 12) | 0xfff;
4986 var.type = desc->type;
4987 var.dpl = desc->dpl;
4988 var.db = desc->d;
4989 var.s = desc->s;
4990 var.l = desc->l;
4991 var.g = desc->g;
4992 var.avl = desc->avl;
4993 var.present = desc->p;
4994 var.unusable = !var.present;
4995 var.padding = 0;
4996
4997 kvm_set_segment(vcpu, &var, seg);
4998 return;
4999 }
5000
5001 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5002 u32 msr_index, u64 *pdata)
5003 {
5004 struct msr_data msr;
5005 int r;
5006
5007 msr.index = msr_index;
5008 msr.host_initiated = false;
5009 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5010 if (r)
5011 return r;
5012
5013 *pdata = msr.data;
5014 return 0;
5015 }
5016
5017 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5018 u32 msr_index, u64 data)
5019 {
5020 struct msr_data msr;
5021
5022 msr.data = data;
5023 msr.index = msr_index;
5024 msr.host_initiated = false;
5025 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5026 }
5027
5028 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5029 {
5030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5031
5032 return vcpu->arch.smbase;
5033 }
5034
5035 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5036 {
5037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5038
5039 vcpu->arch.smbase = smbase;
5040 }
5041
5042 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5043 u32 pmc)
5044 {
5045 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5046 }
5047
5048 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5049 u32 pmc, u64 *pdata)
5050 {
5051 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5052 }
5053
5054 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5055 {
5056 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5057 }
5058
5059 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5060 {
5061 preempt_disable();
5062 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5063 /*
5064 * CR0.TS may reference the host fpu state, not the guest fpu state,
5065 * so it may be clear at this point.
5066 */
5067 clts();
5068 }
5069
5070 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5071 {
5072 preempt_enable();
5073 }
5074
5075 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5076 struct x86_instruction_info *info,
5077 enum x86_intercept_stage stage)
5078 {
5079 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5080 }
5081
5082 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5083 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5084 {
5085 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5086 }
5087
5088 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5089 {
5090 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5091 }
5092
5093 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5094 {
5095 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5096 }
5097
5098 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5099 {
5100 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5101 }
5102
5103 static const struct x86_emulate_ops emulate_ops = {
5104 .read_gpr = emulator_read_gpr,
5105 .write_gpr = emulator_write_gpr,
5106 .read_std = kvm_read_guest_virt_system,
5107 .write_std = kvm_write_guest_virt_system,
5108 .read_phys = kvm_read_guest_phys_system,
5109 .fetch = kvm_fetch_guest_virt,
5110 .read_emulated = emulator_read_emulated,
5111 .write_emulated = emulator_write_emulated,
5112 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5113 .invlpg = emulator_invlpg,
5114 .pio_in_emulated = emulator_pio_in_emulated,
5115 .pio_out_emulated = emulator_pio_out_emulated,
5116 .get_segment = emulator_get_segment,
5117 .set_segment = emulator_set_segment,
5118 .get_cached_segment_base = emulator_get_cached_segment_base,
5119 .get_gdt = emulator_get_gdt,
5120 .get_idt = emulator_get_idt,
5121 .set_gdt = emulator_set_gdt,
5122 .set_idt = emulator_set_idt,
5123 .get_cr = emulator_get_cr,
5124 .set_cr = emulator_set_cr,
5125 .cpl = emulator_get_cpl,
5126 .get_dr = emulator_get_dr,
5127 .set_dr = emulator_set_dr,
5128 .get_smbase = emulator_get_smbase,
5129 .set_smbase = emulator_set_smbase,
5130 .set_msr = emulator_set_msr,
5131 .get_msr = emulator_get_msr,
5132 .check_pmc = emulator_check_pmc,
5133 .read_pmc = emulator_read_pmc,
5134 .halt = emulator_halt,
5135 .wbinvd = emulator_wbinvd,
5136 .fix_hypercall = emulator_fix_hypercall,
5137 .get_fpu = emulator_get_fpu,
5138 .put_fpu = emulator_put_fpu,
5139 .intercept = emulator_intercept,
5140 .get_cpuid = emulator_get_cpuid,
5141 .set_nmi_mask = emulator_set_nmi_mask,
5142 };
5143
5144 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5145 {
5146 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5147 /*
5148 * an sti; sti; sequence only disable interrupts for the first
5149 * instruction. So, if the last instruction, be it emulated or
5150 * not, left the system with the INT_STI flag enabled, it
5151 * means that the last instruction is an sti. We should not
5152 * leave the flag on in this case. The same goes for mov ss
5153 */
5154 if (int_shadow & mask)
5155 mask = 0;
5156 if (unlikely(int_shadow || mask)) {
5157 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5158 if (!mask)
5159 kvm_make_request(KVM_REQ_EVENT, vcpu);
5160 }
5161 }
5162
5163 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5164 {
5165 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5166 if (ctxt->exception.vector == PF_VECTOR)
5167 return kvm_propagate_fault(vcpu, &ctxt->exception);
5168
5169 if (ctxt->exception.error_code_valid)
5170 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5171 ctxt->exception.error_code);
5172 else
5173 kvm_queue_exception(vcpu, ctxt->exception.vector);
5174 return false;
5175 }
5176
5177 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5178 {
5179 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5180 int cs_db, cs_l;
5181
5182 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5183
5184 ctxt->eflags = kvm_get_rflags(vcpu);
5185 ctxt->eip = kvm_rip_read(vcpu);
5186 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5187 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5188 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5189 cs_db ? X86EMUL_MODE_PROT32 :
5190 X86EMUL_MODE_PROT16;
5191 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5192 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5193 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5194 ctxt->emul_flags = vcpu->arch.hflags;
5195
5196 init_decode_cache(ctxt);
5197 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5198 }
5199
5200 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5201 {
5202 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5203 int ret;
5204
5205 init_emulate_ctxt(vcpu);
5206
5207 ctxt->op_bytes = 2;
5208 ctxt->ad_bytes = 2;
5209 ctxt->_eip = ctxt->eip + inc_eip;
5210 ret = emulate_int_real(ctxt, irq);
5211
5212 if (ret != X86EMUL_CONTINUE)
5213 return EMULATE_FAIL;
5214
5215 ctxt->eip = ctxt->_eip;
5216 kvm_rip_write(vcpu, ctxt->eip);
5217 kvm_set_rflags(vcpu, ctxt->eflags);
5218
5219 if (irq == NMI_VECTOR)
5220 vcpu->arch.nmi_pending = 0;
5221 else
5222 vcpu->arch.interrupt.pending = false;
5223
5224 return EMULATE_DONE;
5225 }
5226 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5227
5228 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5229 {
5230 int r = EMULATE_DONE;
5231
5232 ++vcpu->stat.insn_emulation_fail;
5233 trace_kvm_emulate_insn_failed(vcpu);
5234 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5235 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5236 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5237 vcpu->run->internal.ndata = 0;
5238 r = EMULATE_FAIL;
5239 }
5240 kvm_queue_exception(vcpu, UD_VECTOR);
5241
5242 return r;
5243 }
5244
5245 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5246 bool write_fault_to_shadow_pgtable,
5247 int emulation_type)
5248 {
5249 gpa_t gpa = cr2;
5250 kvm_pfn_t pfn;
5251
5252 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5253 return false;
5254
5255 if (!vcpu->arch.mmu.direct_map) {
5256 /*
5257 * Write permission should be allowed since only
5258 * write access need to be emulated.
5259 */
5260 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5261
5262 /*
5263 * If the mapping is invalid in guest, let cpu retry
5264 * it to generate fault.
5265 */
5266 if (gpa == UNMAPPED_GVA)
5267 return true;
5268 }
5269
5270 /*
5271 * Do not retry the unhandleable instruction if it faults on the
5272 * readonly host memory, otherwise it will goto a infinite loop:
5273 * retry instruction -> write #PF -> emulation fail -> retry
5274 * instruction -> ...
5275 */
5276 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5277
5278 /*
5279 * If the instruction failed on the error pfn, it can not be fixed,
5280 * report the error to userspace.
5281 */
5282 if (is_error_noslot_pfn(pfn))
5283 return false;
5284
5285 kvm_release_pfn_clean(pfn);
5286
5287 /* The instructions are well-emulated on direct mmu. */
5288 if (vcpu->arch.mmu.direct_map) {
5289 unsigned int indirect_shadow_pages;
5290
5291 spin_lock(&vcpu->kvm->mmu_lock);
5292 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5293 spin_unlock(&vcpu->kvm->mmu_lock);
5294
5295 if (indirect_shadow_pages)
5296 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5297
5298 return true;
5299 }
5300
5301 /*
5302 * if emulation was due to access to shadowed page table
5303 * and it failed try to unshadow page and re-enter the
5304 * guest to let CPU execute the instruction.
5305 */
5306 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5307
5308 /*
5309 * If the access faults on its page table, it can not
5310 * be fixed by unprotecting shadow page and it should
5311 * be reported to userspace.
5312 */
5313 return !write_fault_to_shadow_pgtable;
5314 }
5315
5316 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5317 unsigned long cr2, int emulation_type)
5318 {
5319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5320 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5321
5322 last_retry_eip = vcpu->arch.last_retry_eip;
5323 last_retry_addr = vcpu->arch.last_retry_addr;
5324
5325 /*
5326 * If the emulation is caused by #PF and it is non-page_table
5327 * writing instruction, it means the VM-EXIT is caused by shadow
5328 * page protected, we can zap the shadow page and retry this
5329 * instruction directly.
5330 *
5331 * Note: if the guest uses a non-page-table modifying instruction
5332 * on the PDE that points to the instruction, then we will unmap
5333 * the instruction and go to an infinite loop. So, we cache the
5334 * last retried eip and the last fault address, if we meet the eip
5335 * and the address again, we can break out of the potential infinite
5336 * loop.
5337 */
5338 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5339
5340 if (!(emulation_type & EMULTYPE_RETRY))
5341 return false;
5342
5343 if (x86_page_table_writing_insn(ctxt))
5344 return false;
5345
5346 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5347 return false;
5348
5349 vcpu->arch.last_retry_eip = ctxt->eip;
5350 vcpu->arch.last_retry_addr = cr2;
5351
5352 if (!vcpu->arch.mmu.direct_map)
5353 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5354
5355 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5356
5357 return true;
5358 }
5359
5360 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5361 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5362
5363 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5364 {
5365 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5366 /* This is a good place to trace that we are exiting SMM. */
5367 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5368
5369 /* Process a latched INIT or SMI, if any. */
5370 kvm_make_request(KVM_REQ_EVENT, vcpu);
5371 }
5372
5373 kvm_mmu_reset_context(vcpu);
5374 }
5375
5376 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5377 {
5378 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5379
5380 vcpu->arch.hflags = emul_flags;
5381
5382 if (changed & HF_SMM_MASK)
5383 kvm_smm_changed(vcpu);
5384 }
5385
5386 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5387 unsigned long *db)
5388 {
5389 u32 dr6 = 0;
5390 int i;
5391 u32 enable, rwlen;
5392
5393 enable = dr7;
5394 rwlen = dr7 >> 16;
5395 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5396 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5397 dr6 |= (1 << i);
5398 return dr6;
5399 }
5400
5401 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5402 {
5403 struct kvm_run *kvm_run = vcpu->run;
5404
5405 /*
5406 * rflags is the old, "raw" value of the flags. The new value has
5407 * not been saved yet.
5408 *
5409 * This is correct even for TF set by the guest, because "the
5410 * processor will not generate this exception after the instruction
5411 * that sets the TF flag".
5412 */
5413 if (unlikely(rflags & X86_EFLAGS_TF)) {
5414 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5415 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5416 DR6_RTM;
5417 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5418 kvm_run->debug.arch.exception = DB_VECTOR;
5419 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5420 *r = EMULATE_USER_EXIT;
5421 } else {
5422 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5423 /*
5424 * "Certain debug exceptions may clear bit 0-3. The
5425 * remaining contents of the DR6 register are never
5426 * cleared by the processor".
5427 */
5428 vcpu->arch.dr6 &= ~15;
5429 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5430 kvm_queue_exception(vcpu, DB_VECTOR);
5431 }
5432 }
5433 }
5434
5435 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5436 {
5437 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5438 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5439 struct kvm_run *kvm_run = vcpu->run;
5440 unsigned long eip = kvm_get_linear_rip(vcpu);
5441 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5442 vcpu->arch.guest_debug_dr7,
5443 vcpu->arch.eff_db);
5444
5445 if (dr6 != 0) {
5446 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5447 kvm_run->debug.arch.pc = eip;
5448 kvm_run->debug.arch.exception = DB_VECTOR;
5449 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5450 *r = EMULATE_USER_EXIT;
5451 return true;
5452 }
5453 }
5454
5455 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5456 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5457 unsigned long eip = kvm_get_linear_rip(vcpu);
5458 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5459 vcpu->arch.dr7,
5460 vcpu->arch.db);
5461
5462 if (dr6 != 0) {
5463 vcpu->arch.dr6 &= ~15;
5464 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5465 kvm_queue_exception(vcpu, DB_VECTOR);
5466 *r = EMULATE_DONE;
5467 return true;
5468 }
5469 }
5470
5471 return false;
5472 }
5473
5474 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5475 unsigned long cr2,
5476 int emulation_type,
5477 void *insn,
5478 int insn_len)
5479 {
5480 int r;
5481 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5482 bool writeback = true;
5483 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5484
5485 /*
5486 * Clear write_fault_to_shadow_pgtable here to ensure it is
5487 * never reused.
5488 */
5489 vcpu->arch.write_fault_to_shadow_pgtable = false;
5490 kvm_clear_exception_queue(vcpu);
5491
5492 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5493 init_emulate_ctxt(vcpu);
5494
5495 /*
5496 * We will reenter on the same instruction since
5497 * we do not set complete_userspace_io. This does not
5498 * handle watchpoints yet, those would be handled in
5499 * the emulate_ops.
5500 */
5501 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5502 return r;
5503
5504 ctxt->interruptibility = 0;
5505 ctxt->have_exception = false;
5506 ctxt->exception.vector = -1;
5507 ctxt->perm_ok = false;
5508
5509 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5510
5511 r = x86_decode_insn(ctxt, insn, insn_len);
5512
5513 trace_kvm_emulate_insn_start(vcpu);
5514 ++vcpu->stat.insn_emulation;
5515 if (r != EMULATION_OK) {
5516 if (emulation_type & EMULTYPE_TRAP_UD)
5517 return EMULATE_FAIL;
5518 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5519 emulation_type))
5520 return EMULATE_DONE;
5521 if (emulation_type & EMULTYPE_SKIP)
5522 return EMULATE_FAIL;
5523 return handle_emulation_failure(vcpu);
5524 }
5525 }
5526
5527 if (emulation_type & EMULTYPE_SKIP) {
5528 kvm_rip_write(vcpu, ctxt->_eip);
5529 if (ctxt->eflags & X86_EFLAGS_RF)
5530 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5531 return EMULATE_DONE;
5532 }
5533
5534 if (retry_instruction(ctxt, cr2, emulation_type))
5535 return EMULATE_DONE;
5536
5537 /* this is needed for vmware backdoor interface to work since it
5538 changes registers values during IO operation */
5539 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5540 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5541 emulator_invalidate_register_cache(ctxt);
5542 }
5543
5544 restart:
5545 r = x86_emulate_insn(ctxt);
5546
5547 if (r == EMULATION_INTERCEPTED)
5548 return EMULATE_DONE;
5549
5550 if (r == EMULATION_FAILED) {
5551 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5552 emulation_type))
5553 return EMULATE_DONE;
5554
5555 return handle_emulation_failure(vcpu);
5556 }
5557
5558 if (ctxt->have_exception) {
5559 r = EMULATE_DONE;
5560 if (inject_emulated_exception(vcpu))
5561 return r;
5562 } else if (vcpu->arch.pio.count) {
5563 if (!vcpu->arch.pio.in) {
5564 /* FIXME: return into emulator if single-stepping. */
5565 vcpu->arch.pio.count = 0;
5566 } else {
5567 writeback = false;
5568 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5569 }
5570 r = EMULATE_USER_EXIT;
5571 } else if (vcpu->mmio_needed) {
5572 if (!vcpu->mmio_is_write)
5573 writeback = false;
5574 r = EMULATE_USER_EXIT;
5575 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5576 } else if (r == EMULATION_RESTART)
5577 goto restart;
5578 else
5579 r = EMULATE_DONE;
5580
5581 if (writeback) {
5582 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5583 toggle_interruptibility(vcpu, ctxt->interruptibility);
5584 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5585 if (vcpu->arch.hflags != ctxt->emul_flags)
5586 kvm_set_hflags(vcpu, ctxt->emul_flags);
5587 kvm_rip_write(vcpu, ctxt->eip);
5588 if (r == EMULATE_DONE)
5589 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5590 if (!ctxt->have_exception ||
5591 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5592 __kvm_set_rflags(vcpu, ctxt->eflags);
5593
5594 /*
5595 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5596 * do nothing, and it will be requested again as soon as
5597 * the shadow expires. But we still need to check here,
5598 * because POPF has no interrupt shadow.
5599 */
5600 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5601 kvm_make_request(KVM_REQ_EVENT, vcpu);
5602 } else
5603 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5604
5605 return r;
5606 }
5607 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5608
5609 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5610 {
5611 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5612 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5613 size, port, &val, 1);
5614 /* do not return to emulator after return from userspace */
5615 vcpu->arch.pio.count = 0;
5616 return ret;
5617 }
5618 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5619
5620 static int kvmclock_cpu_down_prep(unsigned int cpu)
5621 {
5622 __this_cpu_write(cpu_tsc_khz, 0);
5623 return 0;
5624 }
5625
5626 static void tsc_khz_changed(void *data)
5627 {
5628 struct cpufreq_freqs *freq = data;
5629 unsigned long khz = 0;
5630
5631 if (data)
5632 khz = freq->new;
5633 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5634 khz = cpufreq_quick_get(raw_smp_processor_id());
5635 if (!khz)
5636 khz = tsc_khz;
5637 __this_cpu_write(cpu_tsc_khz, khz);
5638 }
5639
5640 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5641 void *data)
5642 {
5643 struct cpufreq_freqs *freq = data;
5644 struct kvm *kvm;
5645 struct kvm_vcpu *vcpu;
5646 int i, send_ipi = 0;
5647
5648 /*
5649 * We allow guests to temporarily run on slowing clocks,
5650 * provided we notify them after, or to run on accelerating
5651 * clocks, provided we notify them before. Thus time never
5652 * goes backwards.
5653 *
5654 * However, we have a problem. We can't atomically update
5655 * the frequency of a given CPU from this function; it is
5656 * merely a notifier, which can be called from any CPU.
5657 * Changing the TSC frequency at arbitrary points in time
5658 * requires a recomputation of local variables related to
5659 * the TSC for each VCPU. We must flag these local variables
5660 * to be updated and be sure the update takes place with the
5661 * new frequency before any guests proceed.
5662 *
5663 * Unfortunately, the combination of hotplug CPU and frequency
5664 * change creates an intractable locking scenario; the order
5665 * of when these callouts happen is undefined with respect to
5666 * CPU hotplug, and they can race with each other. As such,
5667 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5668 * undefined; you can actually have a CPU frequency change take
5669 * place in between the computation of X and the setting of the
5670 * variable. To protect against this problem, all updates of
5671 * the per_cpu tsc_khz variable are done in an interrupt
5672 * protected IPI, and all callers wishing to update the value
5673 * must wait for a synchronous IPI to complete (which is trivial
5674 * if the caller is on the CPU already). This establishes the
5675 * necessary total order on variable updates.
5676 *
5677 * Note that because a guest time update may take place
5678 * anytime after the setting of the VCPU's request bit, the
5679 * correct TSC value must be set before the request. However,
5680 * to ensure the update actually makes it to any guest which
5681 * starts running in hardware virtualization between the set
5682 * and the acquisition of the spinlock, we must also ping the
5683 * CPU after setting the request bit.
5684 *
5685 */
5686
5687 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5688 return 0;
5689 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5690 return 0;
5691
5692 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5693
5694 spin_lock(&kvm_lock);
5695 list_for_each_entry(kvm, &vm_list, vm_list) {
5696 kvm_for_each_vcpu(i, vcpu, kvm) {
5697 if (vcpu->cpu != freq->cpu)
5698 continue;
5699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5700 if (vcpu->cpu != smp_processor_id())
5701 send_ipi = 1;
5702 }
5703 }
5704 spin_unlock(&kvm_lock);
5705
5706 if (freq->old < freq->new && send_ipi) {
5707 /*
5708 * We upscale the frequency. Must make the guest
5709 * doesn't see old kvmclock values while running with
5710 * the new frequency, otherwise we risk the guest sees
5711 * time go backwards.
5712 *
5713 * In case we update the frequency for another cpu
5714 * (which might be in guest context) send an interrupt
5715 * to kick the cpu out of guest context. Next time
5716 * guest context is entered kvmclock will be updated,
5717 * so the guest will not see stale values.
5718 */
5719 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5720 }
5721 return 0;
5722 }
5723
5724 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5725 .notifier_call = kvmclock_cpufreq_notifier
5726 };
5727
5728 static int kvmclock_cpu_online(unsigned int cpu)
5729 {
5730 tsc_khz_changed(NULL);
5731 return 0;
5732 }
5733
5734 static void kvm_timer_init(void)
5735 {
5736 int cpu;
5737
5738 max_tsc_khz = tsc_khz;
5739
5740 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5741 #ifdef CONFIG_CPU_FREQ
5742 struct cpufreq_policy policy;
5743 memset(&policy, 0, sizeof(policy));
5744 cpu = get_cpu();
5745 cpufreq_get_policy(&policy, cpu);
5746 if (policy.cpuinfo.max_freq)
5747 max_tsc_khz = policy.cpuinfo.max_freq;
5748 put_cpu();
5749 #endif
5750 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5751 CPUFREQ_TRANSITION_NOTIFIER);
5752 }
5753 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5754
5755 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5756 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5757 }
5758
5759 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5760
5761 int kvm_is_in_guest(void)
5762 {
5763 return __this_cpu_read(current_vcpu) != NULL;
5764 }
5765
5766 static int kvm_is_user_mode(void)
5767 {
5768 int user_mode = 3;
5769
5770 if (__this_cpu_read(current_vcpu))
5771 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5772
5773 return user_mode != 0;
5774 }
5775
5776 static unsigned long kvm_get_guest_ip(void)
5777 {
5778 unsigned long ip = 0;
5779
5780 if (__this_cpu_read(current_vcpu))
5781 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5782
5783 return ip;
5784 }
5785
5786 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5787 .is_in_guest = kvm_is_in_guest,
5788 .is_user_mode = kvm_is_user_mode,
5789 .get_guest_ip = kvm_get_guest_ip,
5790 };
5791
5792 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5793 {
5794 __this_cpu_write(current_vcpu, vcpu);
5795 }
5796 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5797
5798 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5799 {
5800 __this_cpu_write(current_vcpu, NULL);
5801 }
5802 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5803
5804 static void kvm_set_mmio_spte_mask(void)
5805 {
5806 u64 mask;
5807 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5808
5809 /*
5810 * Set the reserved bits and the present bit of an paging-structure
5811 * entry to generate page fault with PFER.RSV = 1.
5812 */
5813 /* Mask the reserved physical address bits. */
5814 mask = rsvd_bits(maxphyaddr, 51);
5815
5816 /* Bit 62 is always reserved for 32bit host. */
5817 mask |= 0x3ull << 62;
5818
5819 /* Set the present bit. */
5820 mask |= 1ull;
5821
5822 #ifdef CONFIG_X86_64
5823 /*
5824 * If reserved bit is not supported, clear the present bit to disable
5825 * mmio page fault.
5826 */
5827 if (maxphyaddr == 52)
5828 mask &= ~1ull;
5829 #endif
5830
5831 kvm_mmu_set_mmio_spte_mask(mask);
5832 }
5833
5834 #ifdef CONFIG_X86_64
5835 static void pvclock_gtod_update_fn(struct work_struct *work)
5836 {
5837 struct kvm *kvm;
5838
5839 struct kvm_vcpu *vcpu;
5840 int i;
5841
5842 spin_lock(&kvm_lock);
5843 list_for_each_entry(kvm, &vm_list, vm_list)
5844 kvm_for_each_vcpu(i, vcpu, kvm)
5845 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5846 atomic_set(&kvm_guest_has_master_clock, 0);
5847 spin_unlock(&kvm_lock);
5848 }
5849
5850 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5851
5852 /*
5853 * Notification about pvclock gtod data update.
5854 */
5855 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5856 void *priv)
5857 {
5858 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5859 struct timekeeper *tk = priv;
5860
5861 update_pvclock_gtod(tk);
5862
5863 /* disable master clock if host does not trust, or does not
5864 * use, TSC clocksource
5865 */
5866 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5867 atomic_read(&kvm_guest_has_master_clock) != 0)
5868 queue_work(system_long_wq, &pvclock_gtod_work);
5869
5870 return 0;
5871 }
5872
5873 static struct notifier_block pvclock_gtod_notifier = {
5874 .notifier_call = pvclock_gtod_notify,
5875 };
5876 #endif
5877
5878 int kvm_arch_init(void *opaque)
5879 {
5880 int r;
5881 struct kvm_x86_ops *ops = opaque;
5882
5883 if (kvm_x86_ops) {
5884 printk(KERN_ERR "kvm: already loaded the other module\n");
5885 r = -EEXIST;
5886 goto out;
5887 }
5888
5889 if (!ops->cpu_has_kvm_support()) {
5890 printk(KERN_ERR "kvm: no hardware support\n");
5891 r = -EOPNOTSUPP;
5892 goto out;
5893 }
5894 if (ops->disabled_by_bios()) {
5895 printk(KERN_ERR "kvm: disabled by bios\n");
5896 r = -EOPNOTSUPP;
5897 goto out;
5898 }
5899
5900 r = -ENOMEM;
5901 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5902 if (!shared_msrs) {
5903 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5904 goto out;
5905 }
5906
5907 r = kvm_mmu_module_init();
5908 if (r)
5909 goto out_free_percpu;
5910
5911 kvm_set_mmio_spte_mask();
5912
5913 kvm_x86_ops = ops;
5914
5915 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5916 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5917 PT_PRESENT_MASK);
5918 kvm_timer_init();
5919
5920 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5921
5922 if (boot_cpu_has(X86_FEATURE_XSAVE))
5923 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5924
5925 kvm_lapic_init();
5926 #ifdef CONFIG_X86_64
5927 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5928 #endif
5929
5930 return 0;
5931
5932 out_free_percpu:
5933 free_percpu(shared_msrs);
5934 out:
5935 return r;
5936 }
5937
5938 void kvm_arch_exit(void)
5939 {
5940 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5941
5942 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5943 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5944 CPUFREQ_TRANSITION_NOTIFIER);
5945 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
5946 #ifdef CONFIG_X86_64
5947 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5948 #endif
5949 kvm_x86_ops = NULL;
5950 kvm_mmu_module_exit();
5951 free_percpu(shared_msrs);
5952 }
5953
5954 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5955 {
5956 ++vcpu->stat.halt_exits;
5957 if (lapic_in_kernel(vcpu)) {
5958 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5959 return 1;
5960 } else {
5961 vcpu->run->exit_reason = KVM_EXIT_HLT;
5962 return 0;
5963 }
5964 }
5965 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5966
5967 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5968 {
5969 kvm_x86_ops->skip_emulated_instruction(vcpu);
5970 return kvm_vcpu_halt(vcpu);
5971 }
5972 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5973
5974 /*
5975 * kvm_pv_kick_cpu_op: Kick a vcpu.
5976 *
5977 * @apicid - apicid of vcpu to be kicked.
5978 */
5979 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5980 {
5981 struct kvm_lapic_irq lapic_irq;
5982
5983 lapic_irq.shorthand = 0;
5984 lapic_irq.dest_mode = 0;
5985 lapic_irq.dest_id = apicid;
5986 lapic_irq.msi_redir_hint = false;
5987
5988 lapic_irq.delivery_mode = APIC_DM_REMRD;
5989 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5990 }
5991
5992 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5993 {
5994 vcpu->arch.apicv_active = false;
5995 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5996 }
5997
5998 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5999 {
6000 unsigned long nr, a0, a1, a2, a3, ret;
6001 int op_64_bit, r = 1;
6002
6003 kvm_x86_ops->skip_emulated_instruction(vcpu);
6004
6005 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6006 return kvm_hv_hypercall(vcpu);
6007
6008 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6009 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6010 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6011 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6012 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6013
6014 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6015
6016 op_64_bit = is_64_bit_mode(vcpu);
6017 if (!op_64_bit) {
6018 nr &= 0xFFFFFFFF;
6019 a0 &= 0xFFFFFFFF;
6020 a1 &= 0xFFFFFFFF;
6021 a2 &= 0xFFFFFFFF;
6022 a3 &= 0xFFFFFFFF;
6023 }
6024
6025 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6026 ret = -KVM_EPERM;
6027 goto out;
6028 }
6029
6030 switch (nr) {
6031 case KVM_HC_VAPIC_POLL_IRQ:
6032 ret = 0;
6033 break;
6034 case KVM_HC_KICK_CPU:
6035 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6036 ret = 0;
6037 break;
6038 default:
6039 ret = -KVM_ENOSYS;
6040 break;
6041 }
6042 out:
6043 if (!op_64_bit)
6044 ret = (u32)ret;
6045 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6046 ++vcpu->stat.hypercalls;
6047 return r;
6048 }
6049 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6050
6051 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6052 {
6053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6054 char instruction[3];
6055 unsigned long rip = kvm_rip_read(vcpu);
6056
6057 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6058
6059 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6060 }
6061
6062 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6063 {
6064 return vcpu->run->request_interrupt_window &&
6065 likely(!pic_in_kernel(vcpu->kvm));
6066 }
6067
6068 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6069 {
6070 struct kvm_run *kvm_run = vcpu->run;
6071
6072 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6073 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6074 kvm_run->cr8 = kvm_get_cr8(vcpu);
6075 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6076 kvm_run->ready_for_interrupt_injection =
6077 pic_in_kernel(vcpu->kvm) ||
6078 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6079 }
6080
6081 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6082 {
6083 int max_irr, tpr;
6084
6085 if (!kvm_x86_ops->update_cr8_intercept)
6086 return;
6087
6088 if (!lapic_in_kernel(vcpu))
6089 return;
6090
6091 if (vcpu->arch.apicv_active)
6092 return;
6093
6094 if (!vcpu->arch.apic->vapic_addr)
6095 max_irr = kvm_lapic_find_highest_irr(vcpu);
6096 else
6097 max_irr = -1;
6098
6099 if (max_irr != -1)
6100 max_irr >>= 4;
6101
6102 tpr = kvm_lapic_get_cr8(vcpu);
6103
6104 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6105 }
6106
6107 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6108 {
6109 int r;
6110
6111 /* try to reinject previous events if any */
6112 if (vcpu->arch.exception.pending) {
6113 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6114 vcpu->arch.exception.has_error_code,
6115 vcpu->arch.exception.error_code);
6116
6117 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6118 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6119 X86_EFLAGS_RF);
6120
6121 if (vcpu->arch.exception.nr == DB_VECTOR &&
6122 (vcpu->arch.dr7 & DR7_GD)) {
6123 vcpu->arch.dr7 &= ~DR7_GD;
6124 kvm_update_dr7(vcpu);
6125 }
6126
6127 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6128 vcpu->arch.exception.has_error_code,
6129 vcpu->arch.exception.error_code,
6130 vcpu->arch.exception.reinject);
6131 return 0;
6132 }
6133
6134 if (vcpu->arch.nmi_injected) {
6135 kvm_x86_ops->set_nmi(vcpu);
6136 return 0;
6137 }
6138
6139 if (vcpu->arch.interrupt.pending) {
6140 kvm_x86_ops->set_irq(vcpu);
6141 return 0;
6142 }
6143
6144 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6145 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6146 if (r != 0)
6147 return r;
6148 }
6149
6150 /* try to inject new event if pending */
6151 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6152 vcpu->arch.smi_pending = false;
6153 enter_smm(vcpu);
6154 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6155 --vcpu->arch.nmi_pending;
6156 vcpu->arch.nmi_injected = true;
6157 kvm_x86_ops->set_nmi(vcpu);
6158 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6159 /*
6160 * Because interrupts can be injected asynchronously, we are
6161 * calling check_nested_events again here to avoid a race condition.
6162 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6163 * proposal and current concerns. Perhaps we should be setting
6164 * KVM_REQ_EVENT only on certain events and not unconditionally?
6165 */
6166 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6167 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6168 if (r != 0)
6169 return r;
6170 }
6171 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6172 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6173 false);
6174 kvm_x86_ops->set_irq(vcpu);
6175 }
6176 }
6177
6178 return 0;
6179 }
6180
6181 static void process_nmi(struct kvm_vcpu *vcpu)
6182 {
6183 unsigned limit = 2;
6184
6185 /*
6186 * x86 is limited to one NMI running, and one NMI pending after it.
6187 * If an NMI is already in progress, limit further NMIs to just one.
6188 * Otherwise, allow two (and we'll inject the first one immediately).
6189 */
6190 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6191 limit = 1;
6192
6193 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6194 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6195 kvm_make_request(KVM_REQ_EVENT, vcpu);
6196 }
6197
6198 #define put_smstate(type, buf, offset, val) \
6199 *(type *)((buf) + (offset) - 0x7e00) = val
6200
6201 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6202 {
6203 u32 flags = 0;
6204 flags |= seg->g << 23;
6205 flags |= seg->db << 22;
6206 flags |= seg->l << 21;
6207 flags |= seg->avl << 20;
6208 flags |= seg->present << 15;
6209 flags |= seg->dpl << 13;
6210 flags |= seg->s << 12;
6211 flags |= seg->type << 8;
6212 return flags;
6213 }
6214
6215 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6216 {
6217 struct kvm_segment seg;
6218 int offset;
6219
6220 kvm_get_segment(vcpu, &seg, n);
6221 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6222
6223 if (n < 3)
6224 offset = 0x7f84 + n * 12;
6225 else
6226 offset = 0x7f2c + (n - 3) * 12;
6227
6228 put_smstate(u32, buf, offset + 8, seg.base);
6229 put_smstate(u32, buf, offset + 4, seg.limit);
6230 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6231 }
6232
6233 #ifdef CONFIG_X86_64
6234 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6235 {
6236 struct kvm_segment seg;
6237 int offset;
6238 u16 flags;
6239
6240 kvm_get_segment(vcpu, &seg, n);
6241 offset = 0x7e00 + n * 16;
6242
6243 flags = enter_smm_get_segment_flags(&seg) >> 8;
6244 put_smstate(u16, buf, offset, seg.selector);
6245 put_smstate(u16, buf, offset + 2, flags);
6246 put_smstate(u32, buf, offset + 4, seg.limit);
6247 put_smstate(u64, buf, offset + 8, seg.base);
6248 }
6249 #endif
6250
6251 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6252 {
6253 struct desc_ptr dt;
6254 struct kvm_segment seg;
6255 unsigned long val;
6256 int i;
6257
6258 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6259 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6260 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6261 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6262
6263 for (i = 0; i < 8; i++)
6264 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6265
6266 kvm_get_dr(vcpu, 6, &val);
6267 put_smstate(u32, buf, 0x7fcc, (u32)val);
6268 kvm_get_dr(vcpu, 7, &val);
6269 put_smstate(u32, buf, 0x7fc8, (u32)val);
6270
6271 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6272 put_smstate(u32, buf, 0x7fc4, seg.selector);
6273 put_smstate(u32, buf, 0x7f64, seg.base);
6274 put_smstate(u32, buf, 0x7f60, seg.limit);
6275 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6276
6277 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6278 put_smstate(u32, buf, 0x7fc0, seg.selector);
6279 put_smstate(u32, buf, 0x7f80, seg.base);
6280 put_smstate(u32, buf, 0x7f7c, seg.limit);
6281 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6282
6283 kvm_x86_ops->get_gdt(vcpu, &dt);
6284 put_smstate(u32, buf, 0x7f74, dt.address);
6285 put_smstate(u32, buf, 0x7f70, dt.size);
6286
6287 kvm_x86_ops->get_idt(vcpu, &dt);
6288 put_smstate(u32, buf, 0x7f58, dt.address);
6289 put_smstate(u32, buf, 0x7f54, dt.size);
6290
6291 for (i = 0; i < 6; i++)
6292 enter_smm_save_seg_32(vcpu, buf, i);
6293
6294 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6295
6296 /* revision id */
6297 put_smstate(u32, buf, 0x7efc, 0x00020000);
6298 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6299 }
6300
6301 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6302 {
6303 #ifdef CONFIG_X86_64
6304 struct desc_ptr dt;
6305 struct kvm_segment seg;
6306 unsigned long val;
6307 int i;
6308
6309 for (i = 0; i < 16; i++)
6310 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6311
6312 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6313 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6314
6315 kvm_get_dr(vcpu, 6, &val);
6316 put_smstate(u64, buf, 0x7f68, val);
6317 kvm_get_dr(vcpu, 7, &val);
6318 put_smstate(u64, buf, 0x7f60, val);
6319
6320 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6321 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6322 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6323
6324 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6325
6326 /* revision id */
6327 put_smstate(u32, buf, 0x7efc, 0x00020064);
6328
6329 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6330
6331 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6332 put_smstate(u16, buf, 0x7e90, seg.selector);
6333 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6334 put_smstate(u32, buf, 0x7e94, seg.limit);
6335 put_smstate(u64, buf, 0x7e98, seg.base);
6336
6337 kvm_x86_ops->get_idt(vcpu, &dt);
6338 put_smstate(u32, buf, 0x7e84, dt.size);
6339 put_smstate(u64, buf, 0x7e88, dt.address);
6340
6341 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6342 put_smstate(u16, buf, 0x7e70, seg.selector);
6343 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6344 put_smstate(u32, buf, 0x7e74, seg.limit);
6345 put_smstate(u64, buf, 0x7e78, seg.base);
6346
6347 kvm_x86_ops->get_gdt(vcpu, &dt);
6348 put_smstate(u32, buf, 0x7e64, dt.size);
6349 put_smstate(u64, buf, 0x7e68, dt.address);
6350
6351 for (i = 0; i < 6; i++)
6352 enter_smm_save_seg_64(vcpu, buf, i);
6353 #else
6354 WARN_ON_ONCE(1);
6355 #endif
6356 }
6357
6358 static void enter_smm(struct kvm_vcpu *vcpu)
6359 {
6360 struct kvm_segment cs, ds;
6361 struct desc_ptr dt;
6362 char buf[512];
6363 u32 cr0;
6364
6365 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6366 vcpu->arch.hflags |= HF_SMM_MASK;
6367 memset(buf, 0, 512);
6368 if (guest_cpuid_has_longmode(vcpu))
6369 enter_smm_save_state_64(vcpu, buf);
6370 else
6371 enter_smm_save_state_32(vcpu, buf);
6372
6373 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6374
6375 if (kvm_x86_ops->get_nmi_mask(vcpu))
6376 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6377 else
6378 kvm_x86_ops->set_nmi_mask(vcpu, true);
6379
6380 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6381 kvm_rip_write(vcpu, 0x8000);
6382
6383 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6384 kvm_x86_ops->set_cr0(vcpu, cr0);
6385 vcpu->arch.cr0 = cr0;
6386
6387 kvm_x86_ops->set_cr4(vcpu, 0);
6388
6389 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6390 dt.address = dt.size = 0;
6391 kvm_x86_ops->set_idt(vcpu, &dt);
6392
6393 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6394
6395 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6396 cs.base = vcpu->arch.smbase;
6397
6398 ds.selector = 0;
6399 ds.base = 0;
6400
6401 cs.limit = ds.limit = 0xffffffff;
6402 cs.type = ds.type = 0x3;
6403 cs.dpl = ds.dpl = 0;
6404 cs.db = ds.db = 0;
6405 cs.s = ds.s = 1;
6406 cs.l = ds.l = 0;
6407 cs.g = ds.g = 1;
6408 cs.avl = ds.avl = 0;
6409 cs.present = ds.present = 1;
6410 cs.unusable = ds.unusable = 0;
6411 cs.padding = ds.padding = 0;
6412
6413 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6414 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6415 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6416 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6417 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6418 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6419
6420 if (guest_cpuid_has_longmode(vcpu))
6421 kvm_x86_ops->set_efer(vcpu, 0);
6422
6423 kvm_update_cpuid(vcpu);
6424 kvm_mmu_reset_context(vcpu);
6425 }
6426
6427 static void process_smi(struct kvm_vcpu *vcpu)
6428 {
6429 vcpu->arch.smi_pending = true;
6430 kvm_make_request(KVM_REQ_EVENT, vcpu);
6431 }
6432
6433 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6434 {
6435 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6436 }
6437
6438 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6439 {
6440 u64 eoi_exit_bitmap[4];
6441
6442 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6443 return;
6444
6445 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6446
6447 if (irqchip_split(vcpu->kvm))
6448 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6449 else {
6450 if (vcpu->arch.apicv_active)
6451 kvm_x86_ops->sync_pir_to_irr(vcpu);
6452 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6453 }
6454 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6455 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6456 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6457 }
6458
6459 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6460 {
6461 ++vcpu->stat.tlb_flush;
6462 kvm_x86_ops->tlb_flush(vcpu);
6463 }
6464
6465 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6466 {
6467 struct page *page = NULL;
6468
6469 if (!lapic_in_kernel(vcpu))
6470 return;
6471
6472 if (!kvm_x86_ops->set_apic_access_page_addr)
6473 return;
6474
6475 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6476 if (is_error_page(page))
6477 return;
6478 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6479
6480 /*
6481 * Do not pin apic access page in memory, the MMU notifier
6482 * will call us again if it is migrated or swapped out.
6483 */
6484 put_page(page);
6485 }
6486 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6487
6488 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6489 unsigned long address)
6490 {
6491 /*
6492 * The physical address of apic access page is stored in the VMCS.
6493 * Update it when it becomes invalid.
6494 */
6495 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6496 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6497 }
6498
6499 /*
6500 * Returns 1 to let vcpu_run() continue the guest execution loop without
6501 * exiting to the userspace. Otherwise, the value will be returned to the
6502 * userspace.
6503 */
6504 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6505 {
6506 int r;
6507 bool req_int_win =
6508 dm_request_for_irq_injection(vcpu) &&
6509 kvm_cpu_accept_dm_intr(vcpu);
6510
6511 bool req_immediate_exit = false;
6512
6513 if (vcpu->requests) {
6514 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6515 kvm_mmu_unload(vcpu);
6516 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6517 __kvm_migrate_timers(vcpu);
6518 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6519 kvm_gen_update_masterclock(vcpu->kvm);
6520 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6521 kvm_gen_kvmclock_update(vcpu);
6522 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6523 r = kvm_guest_time_update(vcpu);
6524 if (unlikely(r))
6525 goto out;
6526 }
6527 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6528 kvm_mmu_sync_roots(vcpu);
6529 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6530 kvm_vcpu_flush_tlb(vcpu);
6531 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6532 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6533 r = 0;
6534 goto out;
6535 }
6536 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6537 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6538 r = 0;
6539 goto out;
6540 }
6541 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6542 vcpu->fpu_active = 0;
6543 kvm_x86_ops->fpu_deactivate(vcpu);
6544 }
6545 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6546 /* Page is swapped out. Do synthetic halt */
6547 vcpu->arch.apf.halted = true;
6548 r = 1;
6549 goto out;
6550 }
6551 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6552 record_steal_time(vcpu);
6553 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6554 process_smi(vcpu);
6555 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6556 process_nmi(vcpu);
6557 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6558 kvm_pmu_handle_event(vcpu);
6559 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6560 kvm_pmu_deliver_pmi(vcpu);
6561 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6562 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6563 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6564 vcpu->arch.ioapic_handled_vectors)) {
6565 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6566 vcpu->run->eoi.vector =
6567 vcpu->arch.pending_ioapic_eoi;
6568 r = 0;
6569 goto out;
6570 }
6571 }
6572 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6573 vcpu_scan_ioapic(vcpu);
6574 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6575 kvm_vcpu_reload_apic_access_page(vcpu);
6576 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6577 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6578 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6579 r = 0;
6580 goto out;
6581 }
6582 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6583 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6584 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6585 r = 0;
6586 goto out;
6587 }
6588 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6589 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6590 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6591 r = 0;
6592 goto out;
6593 }
6594
6595 /*
6596 * KVM_REQ_HV_STIMER has to be processed after
6597 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6598 * depend on the guest clock being up-to-date
6599 */
6600 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6601 kvm_hv_process_stimers(vcpu);
6602 }
6603
6604 /*
6605 * KVM_REQ_EVENT is not set when posted interrupts are set by
6606 * VT-d hardware, so we have to update RVI unconditionally.
6607 */
6608 if (kvm_lapic_enabled(vcpu)) {
6609 /*
6610 * Update architecture specific hints for APIC
6611 * virtual interrupt delivery.
6612 */
6613 if (vcpu->arch.apicv_active)
6614 kvm_x86_ops->hwapic_irr_update(vcpu,
6615 kvm_lapic_find_highest_irr(vcpu));
6616 }
6617
6618 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6619 kvm_apic_accept_events(vcpu);
6620 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6621 r = 1;
6622 goto out;
6623 }
6624
6625 if (inject_pending_event(vcpu, req_int_win) != 0)
6626 req_immediate_exit = true;
6627 else {
6628 /* Enable NMI/IRQ window open exits if needed.
6629 *
6630 * SMIs have two cases: 1) they can be nested, and
6631 * then there is nothing to do here because RSM will
6632 * cause a vmexit anyway; 2) or the SMI can be pending
6633 * because inject_pending_event has completed the
6634 * injection of an IRQ or NMI from the previous vmexit,
6635 * and then we request an immediate exit to inject the SMI.
6636 */
6637 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6638 req_immediate_exit = true;
6639 if (vcpu->arch.nmi_pending)
6640 kvm_x86_ops->enable_nmi_window(vcpu);
6641 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6642 kvm_x86_ops->enable_irq_window(vcpu);
6643 }
6644
6645 if (kvm_lapic_enabled(vcpu)) {
6646 update_cr8_intercept(vcpu);
6647 kvm_lapic_sync_to_vapic(vcpu);
6648 }
6649 }
6650
6651 r = kvm_mmu_reload(vcpu);
6652 if (unlikely(r)) {
6653 goto cancel_injection;
6654 }
6655
6656 preempt_disable();
6657
6658 kvm_x86_ops->prepare_guest_switch(vcpu);
6659 if (vcpu->fpu_active)
6660 kvm_load_guest_fpu(vcpu);
6661 vcpu->mode = IN_GUEST_MODE;
6662
6663 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6664
6665 /*
6666 * We should set ->mode before check ->requests,
6667 * Please see the comment in kvm_make_all_cpus_request.
6668 * This also orders the write to mode from any reads
6669 * to the page tables done while the VCPU is running.
6670 * Please see the comment in kvm_flush_remote_tlbs.
6671 */
6672 smp_mb__after_srcu_read_unlock();
6673
6674 local_irq_disable();
6675
6676 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6677 || need_resched() || signal_pending(current)) {
6678 vcpu->mode = OUTSIDE_GUEST_MODE;
6679 smp_wmb();
6680 local_irq_enable();
6681 preempt_enable();
6682 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6683 r = 1;
6684 goto cancel_injection;
6685 }
6686
6687 kvm_load_guest_xcr0(vcpu);
6688
6689 if (req_immediate_exit) {
6690 kvm_make_request(KVM_REQ_EVENT, vcpu);
6691 smp_send_reschedule(vcpu->cpu);
6692 }
6693
6694 trace_kvm_entry(vcpu->vcpu_id);
6695 wait_lapic_expire(vcpu);
6696 guest_enter_irqoff();
6697
6698 if (unlikely(vcpu->arch.switch_db_regs)) {
6699 set_debugreg(0, 7);
6700 set_debugreg(vcpu->arch.eff_db[0], 0);
6701 set_debugreg(vcpu->arch.eff_db[1], 1);
6702 set_debugreg(vcpu->arch.eff_db[2], 2);
6703 set_debugreg(vcpu->arch.eff_db[3], 3);
6704 set_debugreg(vcpu->arch.dr6, 6);
6705 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6706 }
6707
6708 kvm_x86_ops->run(vcpu);
6709
6710 /*
6711 * Do this here before restoring debug registers on the host. And
6712 * since we do this before handling the vmexit, a DR access vmexit
6713 * can (a) read the correct value of the debug registers, (b) set
6714 * KVM_DEBUGREG_WONT_EXIT again.
6715 */
6716 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6717 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6718 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6719 kvm_update_dr0123(vcpu);
6720 kvm_update_dr6(vcpu);
6721 kvm_update_dr7(vcpu);
6722 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6723 }
6724
6725 /*
6726 * If the guest has used debug registers, at least dr7
6727 * will be disabled while returning to the host.
6728 * If we don't have active breakpoints in the host, we don't
6729 * care about the messed up debug address registers. But if
6730 * we have some of them active, restore the old state.
6731 */
6732 if (hw_breakpoint_active())
6733 hw_breakpoint_restore();
6734
6735 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6736
6737 vcpu->mode = OUTSIDE_GUEST_MODE;
6738 smp_wmb();
6739
6740 kvm_put_guest_xcr0(vcpu);
6741
6742 kvm_x86_ops->handle_external_intr(vcpu);
6743
6744 ++vcpu->stat.exits;
6745
6746 guest_exit_irqoff();
6747
6748 local_irq_enable();
6749 preempt_enable();
6750
6751 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6752
6753 /*
6754 * Profile KVM exit RIPs:
6755 */
6756 if (unlikely(prof_on == KVM_PROFILING)) {
6757 unsigned long rip = kvm_rip_read(vcpu);
6758 profile_hit(KVM_PROFILING, (void *)rip);
6759 }
6760
6761 if (unlikely(vcpu->arch.tsc_always_catchup))
6762 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6763
6764 if (vcpu->arch.apic_attention)
6765 kvm_lapic_sync_from_vapic(vcpu);
6766
6767 r = kvm_x86_ops->handle_exit(vcpu);
6768 return r;
6769
6770 cancel_injection:
6771 kvm_x86_ops->cancel_injection(vcpu);
6772 if (unlikely(vcpu->arch.apic_attention))
6773 kvm_lapic_sync_from_vapic(vcpu);
6774 out:
6775 return r;
6776 }
6777
6778 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6779 {
6780 if (!kvm_arch_vcpu_runnable(vcpu) &&
6781 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6782 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6783 kvm_vcpu_block(vcpu);
6784 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6785
6786 if (kvm_x86_ops->post_block)
6787 kvm_x86_ops->post_block(vcpu);
6788
6789 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6790 return 1;
6791 }
6792
6793 kvm_apic_accept_events(vcpu);
6794 switch(vcpu->arch.mp_state) {
6795 case KVM_MP_STATE_HALTED:
6796 vcpu->arch.pv.pv_unhalted = false;
6797 vcpu->arch.mp_state =
6798 KVM_MP_STATE_RUNNABLE;
6799 case KVM_MP_STATE_RUNNABLE:
6800 vcpu->arch.apf.halted = false;
6801 break;
6802 case KVM_MP_STATE_INIT_RECEIVED:
6803 break;
6804 default:
6805 return -EINTR;
6806 break;
6807 }
6808 return 1;
6809 }
6810
6811 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6812 {
6813 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6814 !vcpu->arch.apf.halted);
6815 }
6816
6817 static int vcpu_run(struct kvm_vcpu *vcpu)
6818 {
6819 int r;
6820 struct kvm *kvm = vcpu->kvm;
6821
6822 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6823
6824 for (;;) {
6825 if (kvm_vcpu_running(vcpu)) {
6826 r = vcpu_enter_guest(vcpu);
6827 } else {
6828 r = vcpu_block(kvm, vcpu);
6829 }
6830
6831 if (r <= 0)
6832 break;
6833
6834 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6835 if (kvm_cpu_has_pending_timer(vcpu))
6836 kvm_inject_pending_timer_irqs(vcpu);
6837
6838 if (dm_request_for_irq_injection(vcpu) &&
6839 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6840 r = 0;
6841 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6842 ++vcpu->stat.request_irq_exits;
6843 break;
6844 }
6845
6846 kvm_check_async_pf_completion(vcpu);
6847
6848 if (signal_pending(current)) {
6849 r = -EINTR;
6850 vcpu->run->exit_reason = KVM_EXIT_INTR;
6851 ++vcpu->stat.signal_exits;
6852 break;
6853 }
6854 if (need_resched()) {
6855 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6856 cond_resched();
6857 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6858 }
6859 }
6860
6861 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6862
6863 return r;
6864 }
6865
6866 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6867 {
6868 int r;
6869 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6870 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6871 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6872 if (r != EMULATE_DONE)
6873 return 0;
6874 return 1;
6875 }
6876
6877 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6878 {
6879 BUG_ON(!vcpu->arch.pio.count);
6880
6881 return complete_emulated_io(vcpu);
6882 }
6883
6884 /*
6885 * Implements the following, as a state machine:
6886 *
6887 * read:
6888 * for each fragment
6889 * for each mmio piece in the fragment
6890 * write gpa, len
6891 * exit
6892 * copy data
6893 * execute insn
6894 *
6895 * write:
6896 * for each fragment
6897 * for each mmio piece in the fragment
6898 * write gpa, len
6899 * copy data
6900 * exit
6901 */
6902 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6903 {
6904 struct kvm_run *run = vcpu->run;
6905 struct kvm_mmio_fragment *frag;
6906 unsigned len;
6907
6908 BUG_ON(!vcpu->mmio_needed);
6909
6910 /* Complete previous fragment */
6911 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6912 len = min(8u, frag->len);
6913 if (!vcpu->mmio_is_write)
6914 memcpy(frag->data, run->mmio.data, len);
6915
6916 if (frag->len <= 8) {
6917 /* Switch to the next fragment. */
6918 frag++;
6919 vcpu->mmio_cur_fragment++;
6920 } else {
6921 /* Go forward to the next mmio piece. */
6922 frag->data += len;
6923 frag->gpa += len;
6924 frag->len -= len;
6925 }
6926
6927 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6928 vcpu->mmio_needed = 0;
6929
6930 /* FIXME: return into emulator if single-stepping. */
6931 if (vcpu->mmio_is_write)
6932 return 1;
6933 vcpu->mmio_read_completed = 1;
6934 return complete_emulated_io(vcpu);
6935 }
6936
6937 run->exit_reason = KVM_EXIT_MMIO;
6938 run->mmio.phys_addr = frag->gpa;
6939 if (vcpu->mmio_is_write)
6940 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6941 run->mmio.len = min(8u, frag->len);
6942 run->mmio.is_write = vcpu->mmio_is_write;
6943 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6944 return 0;
6945 }
6946
6947
6948 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6949 {
6950 struct fpu *fpu = &current->thread.fpu;
6951 int r;
6952 sigset_t sigsaved;
6953
6954 fpu__activate_curr(fpu);
6955
6956 if (vcpu->sigset_active)
6957 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6958
6959 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6960 kvm_vcpu_block(vcpu);
6961 kvm_apic_accept_events(vcpu);
6962 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6963 r = -EAGAIN;
6964 goto out;
6965 }
6966
6967 /* re-sync apic's tpr */
6968 if (!lapic_in_kernel(vcpu)) {
6969 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6970 r = -EINVAL;
6971 goto out;
6972 }
6973 }
6974
6975 if (unlikely(vcpu->arch.complete_userspace_io)) {
6976 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6977 vcpu->arch.complete_userspace_io = NULL;
6978 r = cui(vcpu);
6979 if (r <= 0)
6980 goto out;
6981 } else
6982 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6983
6984 r = vcpu_run(vcpu);
6985
6986 out:
6987 post_kvm_run_save(vcpu);
6988 if (vcpu->sigset_active)
6989 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6990
6991 return r;
6992 }
6993
6994 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6995 {
6996 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6997 /*
6998 * We are here if userspace calls get_regs() in the middle of
6999 * instruction emulation. Registers state needs to be copied
7000 * back from emulation context to vcpu. Userspace shouldn't do
7001 * that usually, but some bad designed PV devices (vmware
7002 * backdoor interface) need this to work
7003 */
7004 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7005 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7006 }
7007 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7008 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7009 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7010 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7011 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7012 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7013 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7014 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7015 #ifdef CONFIG_X86_64
7016 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7017 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7018 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7019 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7020 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7021 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7022 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7023 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7024 #endif
7025
7026 regs->rip = kvm_rip_read(vcpu);
7027 regs->rflags = kvm_get_rflags(vcpu);
7028
7029 return 0;
7030 }
7031
7032 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7033 {
7034 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7035 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7036
7037 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7038 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7039 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7040 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7041 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7042 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7043 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7044 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7045 #ifdef CONFIG_X86_64
7046 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7047 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7048 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7049 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7050 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7051 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7052 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7053 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7054 #endif
7055
7056 kvm_rip_write(vcpu, regs->rip);
7057 kvm_set_rflags(vcpu, regs->rflags);
7058
7059 vcpu->arch.exception.pending = false;
7060
7061 kvm_make_request(KVM_REQ_EVENT, vcpu);
7062
7063 return 0;
7064 }
7065
7066 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7067 {
7068 struct kvm_segment cs;
7069
7070 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7071 *db = cs.db;
7072 *l = cs.l;
7073 }
7074 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7075
7076 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7077 struct kvm_sregs *sregs)
7078 {
7079 struct desc_ptr dt;
7080
7081 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7082 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7083 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7084 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7085 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7086 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7087
7088 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7089 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7090
7091 kvm_x86_ops->get_idt(vcpu, &dt);
7092 sregs->idt.limit = dt.size;
7093 sregs->idt.base = dt.address;
7094 kvm_x86_ops->get_gdt(vcpu, &dt);
7095 sregs->gdt.limit = dt.size;
7096 sregs->gdt.base = dt.address;
7097
7098 sregs->cr0 = kvm_read_cr0(vcpu);
7099 sregs->cr2 = vcpu->arch.cr2;
7100 sregs->cr3 = kvm_read_cr3(vcpu);
7101 sregs->cr4 = kvm_read_cr4(vcpu);
7102 sregs->cr8 = kvm_get_cr8(vcpu);
7103 sregs->efer = vcpu->arch.efer;
7104 sregs->apic_base = kvm_get_apic_base(vcpu);
7105
7106 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7107
7108 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7109 set_bit(vcpu->arch.interrupt.nr,
7110 (unsigned long *)sregs->interrupt_bitmap);
7111
7112 return 0;
7113 }
7114
7115 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7116 struct kvm_mp_state *mp_state)
7117 {
7118 kvm_apic_accept_events(vcpu);
7119 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7120 vcpu->arch.pv.pv_unhalted)
7121 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7122 else
7123 mp_state->mp_state = vcpu->arch.mp_state;
7124
7125 return 0;
7126 }
7127
7128 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7129 struct kvm_mp_state *mp_state)
7130 {
7131 if (!lapic_in_kernel(vcpu) &&
7132 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7133 return -EINVAL;
7134
7135 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7136 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7137 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7138 } else
7139 vcpu->arch.mp_state = mp_state->mp_state;
7140 kvm_make_request(KVM_REQ_EVENT, vcpu);
7141 return 0;
7142 }
7143
7144 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7145 int reason, bool has_error_code, u32 error_code)
7146 {
7147 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7148 int ret;
7149
7150 init_emulate_ctxt(vcpu);
7151
7152 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7153 has_error_code, error_code);
7154
7155 if (ret)
7156 return EMULATE_FAIL;
7157
7158 kvm_rip_write(vcpu, ctxt->eip);
7159 kvm_set_rflags(vcpu, ctxt->eflags);
7160 kvm_make_request(KVM_REQ_EVENT, vcpu);
7161 return EMULATE_DONE;
7162 }
7163 EXPORT_SYMBOL_GPL(kvm_task_switch);
7164
7165 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7166 struct kvm_sregs *sregs)
7167 {
7168 struct msr_data apic_base_msr;
7169 int mmu_reset_needed = 0;
7170 int pending_vec, max_bits, idx;
7171 struct desc_ptr dt;
7172
7173 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7174 return -EINVAL;
7175
7176 dt.size = sregs->idt.limit;
7177 dt.address = sregs->idt.base;
7178 kvm_x86_ops->set_idt(vcpu, &dt);
7179 dt.size = sregs->gdt.limit;
7180 dt.address = sregs->gdt.base;
7181 kvm_x86_ops->set_gdt(vcpu, &dt);
7182
7183 vcpu->arch.cr2 = sregs->cr2;
7184 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7185 vcpu->arch.cr3 = sregs->cr3;
7186 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7187
7188 kvm_set_cr8(vcpu, sregs->cr8);
7189
7190 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7191 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7192 apic_base_msr.data = sregs->apic_base;
7193 apic_base_msr.host_initiated = true;
7194 kvm_set_apic_base(vcpu, &apic_base_msr);
7195
7196 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7197 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7198 vcpu->arch.cr0 = sregs->cr0;
7199
7200 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7201 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7202 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7203 kvm_update_cpuid(vcpu);
7204
7205 idx = srcu_read_lock(&vcpu->kvm->srcu);
7206 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7207 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7208 mmu_reset_needed = 1;
7209 }
7210 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7211
7212 if (mmu_reset_needed)
7213 kvm_mmu_reset_context(vcpu);
7214
7215 max_bits = KVM_NR_INTERRUPTS;
7216 pending_vec = find_first_bit(
7217 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7218 if (pending_vec < max_bits) {
7219 kvm_queue_interrupt(vcpu, pending_vec, false);
7220 pr_debug("Set back pending irq %d\n", pending_vec);
7221 }
7222
7223 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7224 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7225 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7226 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7227 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7228 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7229
7230 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7231 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7232
7233 update_cr8_intercept(vcpu);
7234
7235 /* Older userspace won't unhalt the vcpu on reset. */
7236 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7237 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7238 !is_protmode(vcpu))
7239 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7240
7241 kvm_make_request(KVM_REQ_EVENT, vcpu);
7242
7243 return 0;
7244 }
7245
7246 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7247 struct kvm_guest_debug *dbg)
7248 {
7249 unsigned long rflags;
7250 int i, r;
7251
7252 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7253 r = -EBUSY;
7254 if (vcpu->arch.exception.pending)
7255 goto out;
7256 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7257 kvm_queue_exception(vcpu, DB_VECTOR);
7258 else
7259 kvm_queue_exception(vcpu, BP_VECTOR);
7260 }
7261
7262 /*
7263 * Read rflags as long as potentially injected trace flags are still
7264 * filtered out.
7265 */
7266 rflags = kvm_get_rflags(vcpu);
7267
7268 vcpu->guest_debug = dbg->control;
7269 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7270 vcpu->guest_debug = 0;
7271
7272 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7273 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7274 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7275 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7276 } else {
7277 for (i = 0; i < KVM_NR_DB_REGS; i++)
7278 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7279 }
7280 kvm_update_dr7(vcpu);
7281
7282 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7283 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7284 get_segment_base(vcpu, VCPU_SREG_CS);
7285
7286 /*
7287 * Trigger an rflags update that will inject or remove the trace
7288 * flags.
7289 */
7290 kvm_set_rflags(vcpu, rflags);
7291
7292 kvm_x86_ops->update_bp_intercept(vcpu);
7293
7294 r = 0;
7295
7296 out:
7297
7298 return r;
7299 }
7300
7301 /*
7302 * Translate a guest virtual address to a guest physical address.
7303 */
7304 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7305 struct kvm_translation *tr)
7306 {
7307 unsigned long vaddr = tr->linear_address;
7308 gpa_t gpa;
7309 int idx;
7310
7311 idx = srcu_read_lock(&vcpu->kvm->srcu);
7312 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7313 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7314 tr->physical_address = gpa;
7315 tr->valid = gpa != UNMAPPED_GVA;
7316 tr->writeable = 1;
7317 tr->usermode = 0;
7318
7319 return 0;
7320 }
7321
7322 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7323 {
7324 struct fxregs_state *fxsave =
7325 &vcpu->arch.guest_fpu.state.fxsave;
7326
7327 memcpy(fpu->fpr, fxsave->st_space, 128);
7328 fpu->fcw = fxsave->cwd;
7329 fpu->fsw = fxsave->swd;
7330 fpu->ftwx = fxsave->twd;
7331 fpu->last_opcode = fxsave->fop;
7332 fpu->last_ip = fxsave->rip;
7333 fpu->last_dp = fxsave->rdp;
7334 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7335
7336 return 0;
7337 }
7338
7339 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7340 {
7341 struct fxregs_state *fxsave =
7342 &vcpu->arch.guest_fpu.state.fxsave;
7343
7344 memcpy(fxsave->st_space, fpu->fpr, 128);
7345 fxsave->cwd = fpu->fcw;
7346 fxsave->swd = fpu->fsw;
7347 fxsave->twd = fpu->ftwx;
7348 fxsave->fop = fpu->last_opcode;
7349 fxsave->rip = fpu->last_ip;
7350 fxsave->rdp = fpu->last_dp;
7351 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7352
7353 return 0;
7354 }
7355
7356 static void fx_init(struct kvm_vcpu *vcpu)
7357 {
7358 fpstate_init(&vcpu->arch.guest_fpu.state);
7359 if (boot_cpu_has(X86_FEATURE_XSAVES))
7360 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7361 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7362
7363 /*
7364 * Ensure guest xcr0 is valid for loading
7365 */
7366 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7367
7368 vcpu->arch.cr0 |= X86_CR0_ET;
7369 }
7370
7371 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7372 {
7373 if (vcpu->guest_fpu_loaded)
7374 return;
7375
7376 /*
7377 * Restore all possible states in the guest,
7378 * and assume host would use all available bits.
7379 * Guest xcr0 would be loaded later.
7380 */
7381 vcpu->guest_fpu_loaded = 1;
7382 __kernel_fpu_begin();
7383 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7384 trace_kvm_fpu(1);
7385 }
7386
7387 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7388 {
7389 if (!vcpu->guest_fpu_loaded)
7390 return;
7391
7392 vcpu->guest_fpu_loaded = 0;
7393 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7394 __kernel_fpu_end();
7395 ++vcpu->stat.fpu_reload;
7396 trace_kvm_fpu(0);
7397 }
7398
7399 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7400 {
7401 kvmclock_reset(vcpu);
7402
7403 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7404 kvm_x86_ops->vcpu_free(vcpu);
7405 }
7406
7407 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7408 unsigned int id)
7409 {
7410 struct kvm_vcpu *vcpu;
7411
7412 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7413 printk_once(KERN_WARNING
7414 "kvm: SMP vm created on host with unstable TSC; "
7415 "guest TSC will not be reliable\n");
7416
7417 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7418
7419 return vcpu;
7420 }
7421
7422 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7423 {
7424 int r;
7425
7426 kvm_vcpu_mtrr_init(vcpu);
7427 r = vcpu_load(vcpu);
7428 if (r)
7429 return r;
7430 kvm_vcpu_reset(vcpu, false);
7431 kvm_mmu_setup(vcpu);
7432 vcpu_put(vcpu);
7433 return r;
7434 }
7435
7436 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7437 {
7438 struct msr_data msr;
7439 struct kvm *kvm = vcpu->kvm;
7440
7441 if (vcpu_load(vcpu))
7442 return;
7443 msr.data = 0x0;
7444 msr.index = MSR_IA32_TSC;
7445 msr.host_initiated = true;
7446 kvm_write_tsc(vcpu, &msr);
7447 vcpu_put(vcpu);
7448
7449 if (!kvmclock_periodic_sync)
7450 return;
7451
7452 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7453 KVMCLOCK_SYNC_PERIOD);
7454 }
7455
7456 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7457 {
7458 int r;
7459 vcpu->arch.apf.msr_val = 0;
7460
7461 r = vcpu_load(vcpu);
7462 BUG_ON(r);
7463 kvm_mmu_unload(vcpu);
7464 vcpu_put(vcpu);
7465
7466 kvm_x86_ops->vcpu_free(vcpu);
7467 }
7468
7469 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7470 {
7471 vcpu->arch.hflags = 0;
7472
7473 vcpu->arch.smi_pending = 0;
7474 atomic_set(&vcpu->arch.nmi_queued, 0);
7475 vcpu->arch.nmi_pending = 0;
7476 vcpu->arch.nmi_injected = false;
7477 kvm_clear_interrupt_queue(vcpu);
7478 kvm_clear_exception_queue(vcpu);
7479
7480 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7481 kvm_update_dr0123(vcpu);
7482 vcpu->arch.dr6 = DR6_INIT;
7483 kvm_update_dr6(vcpu);
7484 vcpu->arch.dr7 = DR7_FIXED_1;
7485 kvm_update_dr7(vcpu);
7486
7487 vcpu->arch.cr2 = 0;
7488
7489 kvm_make_request(KVM_REQ_EVENT, vcpu);
7490 vcpu->arch.apf.msr_val = 0;
7491 vcpu->arch.st.msr_val = 0;
7492
7493 kvmclock_reset(vcpu);
7494
7495 kvm_clear_async_pf_completion_queue(vcpu);
7496 kvm_async_pf_hash_reset(vcpu);
7497 vcpu->arch.apf.halted = false;
7498
7499 if (!init_event) {
7500 kvm_pmu_reset(vcpu);
7501 vcpu->arch.smbase = 0x30000;
7502 }
7503
7504 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7505 vcpu->arch.regs_avail = ~0;
7506 vcpu->arch.regs_dirty = ~0;
7507
7508 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7509 }
7510
7511 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7512 {
7513 struct kvm_segment cs;
7514
7515 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7516 cs.selector = vector << 8;
7517 cs.base = vector << 12;
7518 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7519 kvm_rip_write(vcpu, 0);
7520 }
7521
7522 int kvm_arch_hardware_enable(void)
7523 {
7524 struct kvm *kvm;
7525 struct kvm_vcpu *vcpu;
7526 int i;
7527 int ret;
7528 u64 local_tsc;
7529 u64 max_tsc = 0;
7530 bool stable, backwards_tsc = false;
7531
7532 kvm_shared_msr_cpu_online();
7533 ret = kvm_x86_ops->hardware_enable();
7534 if (ret != 0)
7535 return ret;
7536
7537 local_tsc = rdtsc();
7538 stable = !check_tsc_unstable();
7539 list_for_each_entry(kvm, &vm_list, vm_list) {
7540 kvm_for_each_vcpu(i, vcpu, kvm) {
7541 if (!stable && vcpu->cpu == smp_processor_id())
7542 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7543 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7544 backwards_tsc = true;
7545 if (vcpu->arch.last_host_tsc > max_tsc)
7546 max_tsc = vcpu->arch.last_host_tsc;
7547 }
7548 }
7549 }
7550
7551 /*
7552 * Sometimes, even reliable TSCs go backwards. This happens on
7553 * platforms that reset TSC during suspend or hibernate actions, but
7554 * maintain synchronization. We must compensate. Fortunately, we can
7555 * detect that condition here, which happens early in CPU bringup,
7556 * before any KVM threads can be running. Unfortunately, we can't
7557 * bring the TSCs fully up to date with real time, as we aren't yet far
7558 * enough into CPU bringup that we know how much real time has actually
7559 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7560 * variables that haven't been updated yet.
7561 *
7562 * So we simply find the maximum observed TSC above, then record the
7563 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7564 * the adjustment will be applied. Note that we accumulate
7565 * adjustments, in case multiple suspend cycles happen before some VCPU
7566 * gets a chance to run again. In the event that no KVM threads get a
7567 * chance to run, we will miss the entire elapsed period, as we'll have
7568 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7569 * loose cycle time. This isn't too big a deal, since the loss will be
7570 * uniform across all VCPUs (not to mention the scenario is extremely
7571 * unlikely). It is possible that a second hibernate recovery happens
7572 * much faster than a first, causing the observed TSC here to be
7573 * smaller; this would require additional padding adjustment, which is
7574 * why we set last_host_tsc to the local tsc observed here.
7575 *
7576 * N.B. - this code below runs only on platforms with reliable TSC,
7577 * as that is the only way backwards_tsc is set above. Also note
7578 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7579 * have the same delta_cyc adjustment applied if backwards_tsc
7580 * is detected. Note further, this adjustment is only done once,
7581 * as we reset last_host_tsc on all VCPUs to stop this from being
7582 * called multiple times (one for each physical CPU bringup).
7583 *
7584 * Platforms with unreliable TSCs don't have to deal with this, they
7585 * will be compensated by the logic in vcpu_load, which sets the TSC to
7586 * catchup mode. This will catchup all VCPUs to real time, but cannot
7587 * guarantee that they stay in perfect synchronization.
7588 */
7589 if (backwards_tsc) {
7590 u64 delta_cyc = max_tsc - local_tsc;
7591 backwards_tsc_observed = true;
7592 list_for_each_entry(kvm, &vm_list, vm_list) {
7593 kvm_for_each_vcpu(i, vcpu, kvm) {
7594 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7595 vcpu->arch.last_host_tsc = local_tsc;
7596 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7597 }
7598
7599 /*
7600 * We have to disable TSC offset matching.. if you were
7601 * booting a VM while issuing an S4 host suspend....
7602 * you may have some problem. Solving this issue is
7603 * left as an exercise to the reader.
7604 */
7605 kvm->arch.last_tsc_nsec = 0;
7606 kvm->arch.last_tsc_write = 0;
7607 }
7608
7609 }
7610 return 0;
7611 }
7612
7613 void kvm_arch_hardware_disable(void)
7614 {
7615 kvm_x86_ops->hardware_disable();
7616 drop_user_return_notifiers();
7617 }
7618
7619 int kvm_arch_hardware_setup(void)
7620 {
7621 int r;
7622
7623 r = kvm_x86_ops->hardware_setup();
7624 if (r != 0)
7625 return r;
7626
7627 if (kvm_has_tsc_control) {
7628 /*
7629 * Make sure the user can only configure tsc_khz values that
7630 * fit into a signed integer.
7631 * A min value is not calculated needed because it will always
7632 * be 1 on all machines.
7633 */
7634 u64 max = min(0x7fffffffULL,
7635 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7636 kvm_max_guest_tsc_khz = max;
7637
7638 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7639 }
7640
7641 kvm_init_msr_list();
7642 return 0;
7643 }
7644
7645 void kvm_arch_hardware_unsetup(void)
7646 {
7647 kvm_x86_ops->hardware_unsetup();
7648 }
7649
7650 void kvm_arch_check_processor_compat(void *rtn)
7651 {
7652 kvm_x86_ops->check_processor_compatibility(rtn);
7653 }
7654
7655 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7656 {
7657 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7658 }
7659 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7660
7661 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7662 {
7663 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7664 }
7665
7666 struct static_key kvm_no_apic_vcpu __read_mostly;
7667 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7668
7669 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7670 {
7671 struct page *page;
7672 struct kvm *kvm;
7673 int r;
7674
7675 BUG_ON(vcpu->kvm == NULL);
7676 kvm = vcpu->kvm;
7677
7678 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7679 vcpu->arch.pv.pv_unhalted = false;
7680 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7681 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7682 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7683 else
7684 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7685
7686 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7687 if (!page) {
7688 r = -ENOMEM;
7689 goto fail;
7690 }
7691 vcpu->arch.pio_data = page_address(page);
7692
7693 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7694
7695 r = kvm_mmu_create(vcpu);
7696 if (r < 0)
7697 goto fail_free_pio_data;
7698
7699 if (irqchip_in_kernel(kvm)) {
7700 r = kvm_create_lapic(vcpu);
7701 if (r < 0)
7702 goto fail_mmu_destroy;
7703 } else
7704 static_key_slow_inc(&kvm_no_apic_vcpu);
7705
7706 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7707 GFP_KERNEL);
7708 if (!vcpu->arch.mce_banks) {
7709 r = -ENOMEM;
7710 goto fail_free_lapic;
7711 }
7712 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7713
7714 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7715 r = -ENOMEM;
7716 goto fail_free_mce_banks;
7717 }
7718
7719 fx_init(vcpu);
7720
7721 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7722 vcpu->arch.pv_time_enabled = false;
7723
7724 vcpu->arch.guest_supported_xcr0 = 0;
7725 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7726
7727 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7728
7729 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7730
7731 kvm_async_pf_hash_reset(vcpu);
7732 kvm_pmu_init(vcpu);
7733
7734 vcpu->arch.pending_external_vector = -1;
7735
7736 kvm_hv_vcpu_init(vcpu);
7737
7738 return 0;
7739
7740 fail_free_mce_banks:
7741 kfree(vcpu->arch.mce_banks);
7742 fail_free_lapic:
7743 kvm_free_lapic(vcpu);
7744 fail_mmu_destroy:
7745 kvm_mmu_destroy(vcpu);
7746 fail_free_pio_data:
7747 free_page((unsigned long)vcpu->arch.pio_data);
7748 fail:
7749 return r;
7750 }
7751
7752 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7753 {
7754 int idx;
7755
7756 kvm_hv_vcpu_uninit(vcpu);
7757 kvm_pmu_destroy(vcpu);
7758 kfree(vcpu->arch.mce_banks);
7759 kvm_free_lapic(vcpu);
7760 idx = srcu_read_lock(&vcpu->kvm->srcu);
7761 kvm_mmu_destroy(vcpu);
7762 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7763 free_page((unsigned long)vcpu->arch.pio_data);
7764 if (!lapic_in_kernel(vcpu))
7765 static_key_slow_dec(&kvm_no_apic_vcpu);
7766 }
7767
7768 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7769 {
7770 kvm_x86_ops->sched_in(vcpu, cpu);
7771 }
7772
7773 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7774 {
7775 if (type)
7776 return -EINVAL;
7777
7778 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7779 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7780 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7781 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7782 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7783
7784 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7785 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7786 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7787 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7788 &kvm->arch.irq_sources_bitmap);
7789
7790 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7791 mutex_init(&kvm->arch.apic_map_lock);
7792 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7793
7794 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
7795 pvclock_update_vm_gtod_copy(kvm);
7796
7797 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7798 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7799
7800 kvm_page_track_init(kvm);
7801 kvm_mmu_init_vm(kvm);
7802
7803 if (kvm_x86_ops->vm_init)
7804 return kvm_x86_ops->vm_init(kvm);
7805
7806 return 0;
7807 }
7808
7809 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7810 {
7811 int r;
7812 r = vcpu_load(vcpu);
7813 BUG_ON(r);
7814 kvm_mmu_unload(vcpu);
7815 vcpu_put(vcpu);
7816 }
7817
7818 static void kvm_free_vcpus(struct kvm *kvm)
7819 {
7820 unsigned int i;
7821 struct kvm_vcpu *vcpu;
7822
7823 /*
7824 * Unpin any mmu pages first.
7825 */
7826 kvm_for_each_vcpu(i, vcpu, kvm) {
7827 kvm_clear_async_pf_completion_queue(vcpu);
7828 kvm_unload_vcpu_mmu(vcpu);
7829 }
7830 kvm_for_each_vcpu(i, vcpu, kvm)
7831 kvm_arch_vcpu_free(vcpu);
7832
7833 mutex_lock(&kvm->lock);
7834 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7835 kvm->vcpus[i] = NULL;
7836
7837 atomic_set(&kvm->online_vcpus, 0);
7838 mutex_unlock(&kvm->lock);
7839 }
7840
7841 void kvm_arch_sync_events(struct kvm *kvm)
7842 {
7843 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7844 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7845 kvm_free_all_assigned_devices(kvm);
7846 kvm_free_pit(kvm);
7847 }
7848
7849 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7850 {
7851 int i, r;
7852 unsigned long hva;
7853 struct kvm_memslots *slots = kvm_memslots(kvm);
7854 struct kvm_memory_slot *slot, old;
7855
7856 /* Called with kvm->slots_lock held. */
7857 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7858 return -EINVAL;
7859
7860 slot = id_to_memslot(slots, id);
7861 if (size) {
7862 if (slot->npages)
7863 return -EEXIST;
7864
7865 /*
7866 * MAP_SHARED to prevent internal slot pages from being moved
7867 * by fork()/COW.
7868 */
7869 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7870 MAP_SHARED | MAP_ANONYMOUS, 0);
7871 if (IS_ERR((void *)hva))
7872 return PTR_ERR((void *)hva);
7873 } else {
7874 if (!slot->npages)
7875 return 0;
7876
7877 hva = 0;
7878 }
7879
7880 old = *slot;
7881 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7882 struct kvm_userspace_memory_region m;
7883
7884 m.slot = id | (i << 16);
7885 m.flags = 0;
7886 m.guest_phys_addr = gpa;
7887 m.userspace_addr = hva;
7888 m.memory_size = size;
7889 r = __kvm_set_memory_region(kvm, &m);
7890 if (r < 0)
7891 return r;
7892 }
7893
7894 if (!size) {
7895 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7896 WARN_ON(r < 0);
7897 }
7898
7899 return 0;
7900 }
7901 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7902
7903 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7904 {
7905 int r;
7906
7907 mutex_lock(&kvm->slots_lock);
7908 r = __x86_set_memory_region(kvm, id, gpa, size);
7909 mutex_unlock(&kvm->slots_lock);
7910
7911 return r;
7912 }
7913 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7914
7915 void kvm_arch_destroy_vm(struct kvm *kvm)
7916 {
7917 if (current->mm == kvm->mm) {
7918 /*
7919 * Free memory regions allocated on behalf of userspace,
7920 * unless the the memory map has changed due to process exit
7921 * or fd copying.
7922 */
7923 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7924 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7925 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7926 }
7927 if (kvm_x86_ops->vm_destroy)
7928 kvm_x86_ops->vm_destroy(kvm);
7929 kvm_iommu_unmap_guest(kvm);
7930 kfree(kvm->arch.vpic);
7931 kfree(kvm->arch.vioapic);
7932 kvm_free_vcpus(kvm);
7933 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7934 kvm_mmu_uninit_vm(kvm);
7935 }
7936
7937 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7938 struct kvm_memory_slot *dont)
7939 {
7940 int i;
7941
7942 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7943 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7944 kvfree(free->arch.rmap[i]);
7945 free->arch.rmap[i] = NULL;
7946 }
7947 if (i == 0)
7948 continue;
7949
7950 if (!dont || free->arch.lpage_info[i - 1] !=
7951 dont->arch.lpage_info[i - 1]) {
7952 kvfree(free->arch.lpage_info[i - 1]);
7953 free->arch.lpage_info[i - 1] = NULL;
7954 }
7955 }
7956
7957 kvm_page_track_free_memslot(free, dont);
7958 }
7959
7960 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7961 unsigned long npages)
7962 {
7963 int i;
7964
7965 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7966 struct kvm_lpage_info *linfo;
7967 unsigned long ugfn;
7968 int lpages;
7969 int level = i + 1;
7970
7971 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7972 slot->base_gfn, level) + 1;
7973
7974 slot->arch.rmap[i] =
7975 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7976 if (!slot->arch.rmap[i])
7977 goto out_free;
7978 if (i == 0)
7979 continue;
7980
7981 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7982 if (!linfo)
7983 goto out_free;
7984
7985 slot->arch.lpage_info[i - 1] = linfo;
7986
7987 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7988 linfo[0].disallow_lpage = 1;
7989 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7990 linfo[lpages - 1].disallow_lpage = 1;
7991 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7992 /*
7993 * If the gfn and userspace address are not aligned wrt each
7994 * other, or if explicitly asked to, disable large page
7995 * support for this slot
7996 */
7997 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7998 !kvm_largepages_enabled()) {
7999 unsigned long j;
8000
8001 for (j = 0; j < lpages; ++j)
8002 linfo[j].disallow_lpage = 1;
8003 }
8004 }
8005
8006 if (kvm_page_track_create_memslot(slot, npages))
8007 goto out_free;
8008
8009 return 0;
8010
8011 out_free:
8012 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8013 kvfree(slot->arch.rmap[i]);
8014 slot->arch.rmap[i] = NULL;
8015 if (i == 0)
8016 continue;
8017
8018 kvfree(slot->arch.lpage_info[i - 1]);
8019 slot->arch.lpage_info[i - 1] = NULL;
8020 }
8021 return -ENOMEM;
8022 }
8023
8024 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8025 {
8026 /*
8027 * memslots->generation has been incremented.
8028 * mmio generation may have reached its maximum value.
8029 */
8030 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8031 }
8032
8033 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8034 struct kvm_memory_slot *memslot,
8035 const struct kvm_userspace_memory_region *mem,
8036 enum kvm_mr_change change)
8037 {
8038 return 0;
8039 }
8040
8041 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8042 struct kvm_memory_slot *new)
8043 {
8044 /* Still write protect RO slot */
8045 if (new->flags & KVM_MEM_READONLY) {
8046 kvm_mmu_slot_remove_write_access(kvm, new);
8047 return;
8048 }
8049
8050 /*
8051 * Call kvm_x86_ops dirty logging hooks when they are valid.
8052 *
8053 * kvm_x86_ops->slot_disable_log_dirty is called when:
8054 *
8055 * - KVM_MR_CREATE with dirty logging is disabled
8056 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8057 *
8058 * The reason is, in case of PML, we need to set D-bit for any slots
8059 * with dirty logging disabled in order to eliminate unnecessary GPA
8060 * logging in PML buffer (and potential PML buffer full VMEXT). This
8061 * guarantees leaving PML enabled during guest's lifetime won't have
8062 * any additonal overhead from PML when guest is running with dirty
8063 * logging disabled for memory slots.
8064 *
8065 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8066 * to dirty logging mode.
8067 *
8068 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8069 *
8070 * In case of write protect:
8071 *
8072 * Write protect all pages for dirty logging.
8073 *
8074 * All the sptes including the large sptes which point to this
8075 * slot are set to readonly. We can not create any new large
8076 * spte on this slot until the end of the logging.
8077 *
8078 * See the comments in fast_page_fault().
8079 */
8080 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8081 if (kvm_x86_ops->slot_enable_log_dirty)
8082 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8083 else
8084 kvm_mmu_slot_remove_write_access(kvm, new);
8085 } else {
8086 if (kvm_x86_ops->slot_disable_log_dirty)
8087 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8088 }
8089 }
8090
8091 void kvm_arch_commit_memory_region(struct kvm *kvm,
8092 const struct kvm_userspace_memory_region *mem,
8093 const struct kvm_memory_slot *old,
8094 const struct kvm_memory_slot *new,
8095 enum kvm_mr_change change)
8096 {
8097 int nr_mmu_pages = 0;
8098
8099 if (!kvm->arch.n_requested_mmu_pages)
8100 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8101
8102 if (nr_mmu_pages)
8103 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8104
8105 /*
8106 * Dirty logging tracks sptes in 4k granularity, meaning that large
8107 * sptes have to be split. If live migration is successful, the guest
8108 * in the source machine will be destroyed and large sptes will be
8109 * created in the destination. However, if the guest continues to run
8110 * in the source machine (for example if live migration fails), small
8111 * sptes will remain around and cause bad performance.
8112 *
8113 * Scan sptes if dirty logging has been stopped, dropping those
8114 * which can be collapsed into a single large-page spte. Later
8115 * page faults will create the large-page sptes.
8116 */
8117 if ((change != KVM_MR_DELETE) &&
8118 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8119 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8120 kvm_mmu_zap_collapsible_sptes(kvm, new);
8121
8122 /*
8123 * Set up write protection and/or dirty logging for the new slot.
8124 *
8125 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8126 * been zapped so no dirty logging staff is needed for old slot. For
8127 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8128 * new and it's also covered when dealing with the new slot.
8129 *
8130 * FIXME: const-ify all uses of struct kvm_memory_slot.
8131 */
8132 if (change != KVM_MR_DELETE)
8133 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8134 }
8135
8136 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8137 {
8138 kvm_mmu_invalidate_zap_all_pages(kvm);
8139 }
8140
8141 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8142 struct kvm_memory_slot *slot)
8143 {
8144 kvm_mmu_invalidate_zap_all_pages(kvm);
8145 }
8146
8147 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8148 {
8149 if (!list_empty_careful(&vcpu->async_pf.done))
8150 return true;
8151
8152 if (kvm_apic_has_events(vcpu))
8153 return true;
8154
8155 if (vcpu->arch.pv.pv_unhalted)
8156 return true;
8157
8158 if (atomic_read(&vcpu->arch.nmi_queued))
8159 return true;
8160
8161 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8162 return true;
8163
8164 if (kvm_arch_interrupt_allowed(vcpu) &&
8165 kvm_cpu_has_interrupt(vcpu))
8166 return true;
8167
8168 if (kvm_hv_has_stimer_pending(vcpu))
8169 return true;
8170
8171 return false;
8172 }
8173
8174 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8175 {
8176 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8177 kvm_x86_ops->check_nested_events(vcpu, false);
8178
8179 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8180 }
8181
8182 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8183 {
8184 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8185 }
8186
8187 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8188 {
8189 return kvm_x86_ops->interrupt_allowed(vcpu);
8190 }
8191
8192 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8193 {
8194 if (is_64_bit_mode(vcpu))
8195 return kvm_rip_read(vcpu);
8196 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8197 kvm_rip_read(vcpu));
8198 }
8199 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8200
8201 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8202 {
8203 return kvm_get_linear_rip(vcpu) == linear_rip;
8204 }
8205 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8206
8207 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8208 {
8209 unsigned long rflags;
8210
8211 rflags = kvm_x86_ops->get_rflags(vcpu);
8212 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8213 rflags &= ~X86_EFLAGS_TF;
8214 return rflags;
8215 }
8216 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8217
8218 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8219 {
8220 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8221 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8222 rflags |= X86_EFLAGS_TF;
8223 kvm_x86_ops->set_rflags(vcpu, rflags);
8224 }
8225
8226 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8227 {
8228 __kvm_set_rflags(vcpu, rflags);
8229 kvm_make_request(KVM_REQ_EVENT, vcpu);
8230 }
8231 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8232
8233 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8234 {
8235 int r;
8236
8237 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8238 work->wakeup_all)
8239 return;
8240
8241 r = kvm_mmu_reload(vcpu);
8242 if (unlikely(r))
8243 return;
8244
8245 if (!vcpu->arch.mmu.direct_map &&
8246 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8247 return;
8248
8249 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8250 }
8251
8252 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8253 {
8254 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8255 }
8256
8257 static inline u32 kvm_async_pf_next_probe(u32 key)
8258 {
8259 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8260 }
8261
8262 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8263 {
8264 u32 key = kvm_async_pf_hash_fn(gfn);
8265
8266 while (vcpu->arch.apf.gfns[key] != ~0)
8267 key = kvm_async_pf_next_probe(key);
8268
8269 vcpu->arch.apf.gfns[key] = gfn;
8270 }
8271
8272 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8273 {
8274 int i;
8275 u32 key = kvm_async_pf_hash_fn(gfn);
8276
8277 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8278 (vcpu->arch.apf.gfns[key] != gfn &&
8279 vcpu->arch.apf.gfns[key] != ~0); i++)
8280 key = kvm_async_pf_next_probe(key);
8281
8282 return key;
8283 }
8284
8285 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8286 {
8287 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8288 }
8289
8290 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8291 {
8292 u32 i, j, k;
8293
8294 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8295 while (true) {
8296 vcpu->arch.apf.gfns[i] = ~0;
8297 do {
8298 j = kvm_async_pf_next_probe(j);
8299 if (vcpu->arch.apf.gfns[j] == ~0)
8300 return;
8301 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8302 /*
8303 * k lies cyclically in ]i,j]
8304 * | i.k.j |
8305 * |....j i.k.| or |.k..j i...|
8306 */
8307 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8308 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8309 i = j;
8310 }
8311 }
8312
8313 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8314 {
8315
8316 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8317 sizeof(val));
8318 }
8319
8320 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8321 struct kvm_async_pf *work)
8322 {
8323 struct x86_exception fault;
8324
8325 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8326 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8327
8328 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8329 (vcpu->arch.apf.send_user_only &&
8330 kvm_x86_ops->get_cpl(vcpu) == 0))
8331 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8332 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8333 fault.vector = PF_VECTOR;
8334 fault.error_code_valid = true;
8335 fault.error_code = 0;
8336 fault.nested_page_fault = false;
8337 fault.address = work->arch.token;
8338 kvm_inject_page_fault(vcpu, &fault);
8339 }
8340 }
8341
8342 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8343 struct kvm_async_pf *work)
8344 {
8345 struct x86_exception fault;
8346
8347 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8348 if (work->wakeup_all)
8349 work->arch.token = ~0; /* broadcast wakeup */
8350 else
8351 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8352
8353 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8354 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8355 fault.vector = PF_VECTOR;
8356 fault.error_code_valid = true;
8357 fault.error_code = 0;
8358 fault.nested_page_fault = false;
8359 fault.address = work->arch.token;
8360 kvm_inject_page_fault(vcpu, &fault);
8361 }
8362 vcpu->arch.apf.halted = false;
8363 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8364 }
8365
8366 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8367 {
8368 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8369 return true;
8370 else
8371 return !kvm_event_needs_reinjection(vcpu) &&
8372 kvm_x86_ops->interrupt_allowed(vcpu);
8373 }
8374
8375 void kvm_arch_start_assignment(struct kvm *kvm)
8376 {
8377 atomic_inc(&kvm->arch.assigned_device_count);
8378 }
8379 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8380
8381 void kvm_arch_end_assignment(struct kvm *kvm)
8382 {
8383 atomic_dec(&kvm->arch.assigned_device_count);
8384 }
8385 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8386
8387 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8388 {
8389 return atomic_read(&kvm->arch.assigned_device_count);
8390 }
8391 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8392
8393 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8394 {
8395 atomic_inc(&kvm->arch.noncoherent_dma_count);
8396 }
8397 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8398
8399 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8400 {
8401 atomic_dec(&kvm->arch.noncoherent_dma_count);
8402 }
8403 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8404
8405 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8406 {
8407 return atomic_read(&kvm->arch.noncoherent_dma_count);
8408 }
8409 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8410
8411 bool kvm_arch_has_irq_bypass(void)
8412 {
8413 return kvm_x86_ops->update_pi_irte != NULL;
8414 }
8415
8416 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8417 struct irq_bypass_producer *prod)
8418 {
8419 struct kvm_kernel_irqfd *irqfd =
8420 container_of(cons, struct kvm_kernel_irqfd, consumer);
8421
8422 irqfd->producer = prod;
8423
8424 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8425 prod->irq, irqfd->gsi, 1);
8426 }
8427
8428 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8429 struct irq_bypass_producer *prod)
8430 {
8431 int ret;
8432 struct kvm_kernel_irqfd *irqfd =
8433 container_of(cons, struct kvm_kernel_irqfd, consumer);
8434
8435 WARN_ON(irqfd->producer != prod);
8436 irqfd->producer = NULL;
8437
8438 /*
8439 * When producer of consumer is unregistered, we change back to
8440 * remapped mode, so we can re-use the current implementation
8441 * when the irq is masked/disabled or the consumer side (KVM
8442 * int this case doesn't want to receive the interrupts.
8443 */
8444 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8445 if (ret)
8446 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8447 " fails: %d\n", irqfd->consumer.token, ret);
8448 }
8449
8450 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8451 uint32_t guest_irq, bool set)
8452 {
8453 if (!kvm_x86_ops->update_pi_irte)
8454 return -EINVAL;
8455
8456 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8457 }
8458
8459 bool kvm_vector_hashing_enabled(void)
8460 {
8461 return vector_hashing;
8462 }
8463 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8464
8465 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8466 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8467 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8468 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8469 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8470 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8471 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8472 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8473 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8474 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8475 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8476 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8477 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8478 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8479 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8480 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8481 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8482 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8483 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
A mirror of Linus' kernel repository