arch/xtensa/include/asm/addrspace.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2008-2013 Tensilica Inc.
   4  * Copyright (C) 2016 Cadence Design Systems Inc.
   5  */
   6
   7 #ifndef _XTENSA_ADDRSPACE_H
   8 #define _XTENSA_ADDRSPACE_H
   9
  10 #include <asm/arch/core.h>
  11
  12 /*
  13  * MMU Memory Map
  14  *
  15  * noMMU and v3 MMU have identity mapped address space on reset.
  16  * V2 MMU:
  17  *   IO (uncached)      f0000000..ffffffff      -> f000000
  18  *   IO (cached)        e0000000..efffffff      -> f000000
  19  *   MEM (uncached)     d8000000..dfffffff      -> 0000000
  20  *   MEM (cached)       d0000000..d7ffffff      -> 0000000
  21  *
  22  * The actual location of memory and IO is the board property.
  23  */
  24
  25 #define IOADDR(x)               (CONFIG_SYS_IO_BASE + (x))
  26 #define MEMADDR(x)              (CONFIG_SYS_MEMORY_BASE + (x))
  27 #define PHYSADDR(x)             ((x) - XCHAL_VECBASE_RESET_VADDR + \
  28                                  XCHAL_VECBASE_RESET_PADDR)
  29
  30 #endif  /* _XTENSA_ADDRSPACE_H */