1 /* BFD back-end for Renesas Super-H COFF binaries.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7 This file is part of BFD, the Binary File Descriptor library.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
30 #include "coff/internal.h"
32 #undef bfd_pe_print_pdata
37 #ifndef COFF_IMAGE_WITH_PE
38 static bfd_boolean sh_align_load_span
39 (bfd
*, asection
*, bfd_byte
*,
40 bfd_boolean (*) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
41 void *, bfd_vma
**, bfd_vma
*, bfd_vma
, bfd_vma
, bfd_boolean
*);
43 #define _bfd_sh_align_load_span sh_align_load_span
46 #define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
50 #define bfd_pe_print_pdata NULL
52 #endif /* COFF_WITH_PE. */
56 /* Internal functions. */
59 /* Can't build import tables with 2**4 alignment. */
60 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
62 /* Default section alignment to 2**4. */
63 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
66 #ifdef COFF_IMAGE_WITH_PE
67 /* Align PE executables. */
68 #define COFF_PAGE_SIZE 0x1000
71 /* Generate long file names. */
72 #define COFF_LONG_FILENAMES
75 /* Return TRUE if this relocation should
76 appear in the output .reloc section. */
79 in_reloc_p (bfd
* abfd ATTRIBUTE_UNUSED
,
80 reloc_howto_type
* howto
)
82 return ! howto
->pc_relative
&& howto
->type
!= R_SH_IMAGEBASE
;
86 static bfd_reloc_status_type
87 sh_reloc (bfd
*, arelent
*, asymbol
*, void *, asection
*, bfd
*, char **);
89 sh_relocate_section (bfd
*, struct bfd_link_info
*, bfd
*, asection
*,
90 bfd_byte
*, struct internal_reloc
*,
91 struct internal_syment
*, asection
**);
93 sh_align_loads (bfd
*, asection
*, struct internal_reloc
*,
94 bfd_byte
*, bfd_boolean
*);
96 /* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98 static reloc_howto_type sh_coff_howtos
[] =
104 HOWTO (R_SH_IMM32CE
, /* type */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
108 FALSE
, /* pc_relative */
110 complain_overflow_bitfield
, /* complain_on_overflow */
111 sh_reloc
, /* special_function */
112 "r_imm32ce", /* name */
113 TRUE
, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 FALSE
), /* pcrel_offset */
120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
128 HOWTO (R_SH_PCDISP8BY2
, /* type */
130 1, /* size (0 = byte, 1 = short, 2 = long) */
132 TRUE
, /* pc_relative */
134 complain_overflow_signed
, /* complain_on_overflow */
135 sh_reloc
, /* special_function */
136 "r_pcdisp8by2", /* name */
137 TRUE
, /* partial_inplace */
140 TRUE
), /* pcrel_offset */
142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
144 HOWTO (R_SH_PCDISP
, /* type */
146 1, /* size (0 = byte, 1 = short, 2 = long) */
148 TRUE
, /* pc_relative */
150 complain_overflow_signed
, /* complain_on_overflow */
151 sh_reloc
, /* special_function */
152 "r_pcdisp12by2", /* name */
153 TRUE
, /* partial_inplace */
154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
156 TRUE
), /* pcrel_offset */
160 HOWTO (R_SH_IMM32
, /* type */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
164 FALSE
, /* pc_relative */
166 complain_overflow_bitfield
, /* complain_on_overflow */
167 sh_reloc
, /* special_function */
168 "r_imm32", /* name */
169 TRUE
, /* partial_inplace */
170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
172 FALSE
), /* pcrel_offset */
176 HOWTO (R_SH_IMAGEBASE
, /* type */
178 2, /* size (0 = byte, 1 = short, 2 = long) */
180 FALSE
, /* pc_relative */
182 complain_overflow_bitfield
, /* complain_on_overflow */
183 sh_reloc
, /* special_function */
185 TRUE
, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 FALSE
), /* pcrel_offset */
190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
198 HOWTO (R_SH_PCRELIMM8BY2
, /* type */
200 1, /* size (0 = byte, 1 = short, 2 = long) */
202 TRUE
, /* pc_relative */
204 complain_overflow_unsigned
, /* complain_on_overflow */
205 sh_reloc
, /* special_function */
206 "r_pcrelimm8by2", /* name */
207 TRUE
, /* partial_inplace */
210 TRUE
), /* pcrel_offset */
212 HOWTO (R_SH_PCRELIMM8BY4
, /* type */
214 1, /* size (0 = byte, 1 = short, 2 = long) */
216 TRUE
, /* pc_relative */
218 complain_overflow_unsigned
, /* complain_on_overflow */
219 sh_reloc
, /* special_function */
220 "r_pcrelimm8by4", /* name */
221 TRUE
, /* partial_inplace */
224 TRUE
), /* pcrel_offset */
226 HOWTO (R_SH_IMM16
, /* type */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
230 FALSE
, /* pc_relative */
232 complain_overflow_bitfield
, /* complain_on_overflow */
233 sh_reloc
, /* special_function */
234 "r_imm16", /* name */
235 TRUE
, /* partial_inplace */
236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
238 FALSE
), /* pcrel_offset */
240 HOWTO (R_SH_SWITCH16
, /* type */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
244 FALSE
, /* pc_relative */
246 complain_overflow_bitfield
, /* complain_on_overflow */
247 sh_reloc
, /* special_function */
248 "r_switch16", /* name */
249 TRUE
, /* partial_inplace */
250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
252 FALSE
), /* pcrel_offset */
254 HOWTO (R_SH_SWITCH32
, /* type */
256 2, /* size (0 = byte, 1 = short, 2 = long) */
258 FALSE
, /* pc_relative */
260 complain_overflow_bitfield
, /* complain_on_overflow */
261 sh_reloc
, /* special_function */
262 "r_switch32", /* name */
263 TRUE
, /* partial_inplace */
264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE
), /* pcrel_offset */
268 HOWTO (R_SH_USES
, /* type */
270 1, /* size (0 = byte, 1 = short, 2 = long) */
272 FALSE
, /* pc_relative */
274 complain_overflow_bitfield
, /* complain_on_overflow */
275 sh_reloc
, /* special_function */
277 TRUE
, /* partial_inplace */
278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
280 FALSE
), /* pcrel_offset */
282 HOWTO (R_SH_COUNT
, /* type */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
286 FALSE
, /* pc_relative */
288 complain_overflow_bitfield
, /* complain_on_overflow */
289 sh_reloc
, /* special_function */
290 "r_count", /* name */
291 TRUE
, /* partial_inplace */
292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
294 FALSE
), /* pcrel_offset */
296 HOWTO (R_SH_ALIGN
, /* type */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
300 FALSE
, /* pc_relative */
302 complain_overflow_bitfield
, /* complain_on_overflow */
303 sh_reloc
, /* special_function */
304 "r_align", /* name */
305 TRUE
, /* partial_inplace */
306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
308 FALSE
), /* pcrel_offset */
310 HOWTO (R_SH_CODE
, /* type */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
314 FALSE
, /* pc_relative */
316 complain_overflow_bitfield
, /* complain_on_overflow */
317 sh_reloc
, /* special_function */
319 TRUE
, /* partial_inplace */
320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
322 FALSE
), /* pcrel_offset */
324 HOWTO (R_SH_DATA
, /* type */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
328 FALSE
, /* pc_relative */
330 complain_overflow_bitfield
, /* complain_on_overflow */
331 sh_reloc
, /* special_function */
333 TRUE
, /* partial_inplace */
334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
336 FALSE
), /* pcrel_offset */
338 HOWTO (R_SH_LABEL
, /* type */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
342 FALSE
, /* pc_relative */
344 complain_overflow_bitfield
, /* complain_on_overflow */
345 sh_reloc
, /* special_function */
346 "r_label", /* name */
347 TRUE
, /* partial_inplace */
348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
350 FALSE
), /* pcrel_offset */
352 HOWTO (R_SH_SWITCH8
, /* type */
354 0, /* size (0 = byte, 1 = short, 2 = long) */
356 FALSE
, /* pc_relative */
358 complain_overflow_bitfield
, /* complain_on_overflow */
359 sh_reloc
, /* special_function */
360 "r_switch8", /* name */
361 TRUE
, /* partial_inplace */
364 FALSE
) /* pcrel_offset */
367 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
369 /* Check for a bad magic number. */
370 #define BADMAG(x) SHBADMAG(x)
372 /* Customize coffcode.h (this is not currently used). */
375 /* FIXME: This should not be set here. */
376 #define __A_MAGIC_SET__
379 /* Swap the r_offset field in and out. */
380 #define SWAP_IN_RELOC_OFFSET H_GET_32
381 #define SWAP_OUT_RELOC_OFFSET H_PUT_32
383 /* Swap out extra information in the reloc structure. */
384 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
393 /* Get the value of a symbol, when performing a relocation. */
396 get_symbol_value (asymbol
*symbol
)
400 if (bfd_is_com_section (symbol
->section
))
403 relocation
= (symbol
->value
+
404 symbol
->section
->output_section
->vma
+
405 symbol
->section
->output_offset
);
411 /* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413 #define coff_rtype_to_howto coff_sh_rtype_to_howto
416 static reloc_howto_type
*
417 coff_sh_rtype_to_howto (bfd
* abfd ATTRIBUTE_UNUSED
,
419 struct internal_reloc
* rel
,
420 struct coff_link_hash_entry
* h
,
421 struct internal_syment
* sym
,
424 reloc_howto_type
* howto
;
426 howto
= sh_coff_howtos
+ rel
->r_type
;
430 if (howto
->pc_relative
)
431 *addendp
+= sec
->vma
;
433 if (sym
!= NULL
&& sym
->n_scnum
== 0 && sym
->n_value
!= 0)
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
440 BFD_ASSERT (h
!= NULL
);
443 if (howto
->pc_relative
)
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
454 *addendp
-= sym
->n_value
;
457 if (rel
->r_type
== R_SH_IMAGEBASE
)
458 *addendp
-= pe_data (sec
->output_section
->owner
)->pe_opthdr
.ImageBase
;
463 #endif /* COFF_WITH_PE */
465 /* This structure is used to map BFD reloc codes to SH PE relocs. */
466 struct shcoff_reloc_map
468 bfd_reloc_code_real_type bfd_reloc_val
;
469 unsigned char shcoff_reloc_val
;
473 /* An array mapping BFD reloc codes to SH PE relocs. */
474 static const struct shcoff_reloc_map sh_reloc_map
[] =
476 { BFD_RELOC_32
, R_SH_IMM32CE
},
477 { BFD_RELOC_RVA
, R_SH_IMAGEBASE
},
478 { BFD_RELOC_CTOR
, R_SH_IMM32CE
},
481 /* An array mapping BFD reloc codes to SH PE relocs. */
482 static const struct shcoff_reloc_map sh_reloc_map
[] =
484 { BFD_RELOC_32
, R_SH_IMM32
},
485 { BFD_RELOC_CTOR
, R_SH_IMM32
},
489 /* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
492 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
494 static reloc_howto_type
*
495 sh_coff_reloc_type_lookup (bfd
* abfd ATTRIBUTE_UNUSED
,
496 bfd_reloc_code_real_type code
)
500 for (i
= ARRAY_SIZE (sh_reloc_map
); i
--;)
501 if (sh_reloc_map
[i
].bfd_reloc_val
== code
)
502 return &sh_coff_howtos
[(int) sh_reloc_map
[i
].shcoff_reloc_val
];
504 _bfd_error_handler (_("SH Error: unknown reloc type %d"), code
);
508 static reloc_howto_type
*
509 sh_coff_reloc_name_lookup (bfd
*abfd ATTRIBUTE_UNUSED
,
514 for (i
= 0; i
< sizeof (sh_coff_howtos
) / sizeof (sh_coff_howtos
[0]); i
++)
515 if (sh_coff_howtos
[i
].name
!= NULL
516 && strcasecmp (sh_coff_howtos
[i
].name
, r_name
) == 0)
517 return &sh_coff_howtos
[i
];
522 /* This macro is used in coffcode.h to get the howto corresponding to
523 an internal reloc. */
525 #define RTYPE2HOWTO(relent, internal) \
527 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
528 ? &sh_coff_howtos[(internal)->r_type] \
529 : (reloc_howto_type *) NULL))
531 /* This is the same as the macro in coffcode.h, except that it copies
532 r_offset into reloc_entry->addend for some relocs. */
533 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
535 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
536 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
537 coffsym = (obj_symbols (abfd) \
538 + (cache_ptr->sym_ptr_ptr - symbols)); \
540 coffsym = coff_symbol_from (ptr); \
541 if (coffsym != (coff_symbol_type *) NULL \
542 && coffsym->native->u.syment.n_scnum == 0) \
543 cache_ptr->addend = 0; \
544 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
545 && ptr->section != (asection *) NULL) \
546 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
548 cache_ptr->addend = 0; \
549 if ((reloc).r_type == R_SH_SWITCH8 \
550 || (reloc).r_type == R_SH_SWITCH16 \
551 || (reloc).r_type == R_SH_SWITCH32 \
552 || (reloc).r_type == R_SH_USES \
553 || (reloc).r_type == R_SH_COUNT \
554 || (reloc).r_type == R_SH_ALIGN) \
555 cache_ptr->addend = (reloc).r_offset; \
558 /* This is the howto function for the SH relocations. */
560 static bfd_reloc_status_type
561 sh_reloc (bfd
* abfd
,
562 arelent
* reloc_entry
,
565 asection
* input_section
,
567 char ** error_message ATTRIBUTE_UNUSED
)
571 unsigned short r_type
;
572 bfd_vma addr
= reloc_entry
->address
;
573 bfd_byte
*hit_data
= addr
+ (bfd_byte
*) data
;
575 r_type
= reloc_entry
->howto
->type
;
577 if (output_bfd
!= NULL
)
579 /* Partial linking--do nothing. */
580 reloc_entry
->address
+= input_section
->output_offset
;
584 /* Almost all relocs have to do with relaxing. If any work must be
585 done for them, it has been done in sh_relax_section. */
586 if (r_type
!= R_SH_IMM32
588 && r_type
!= R_SH_IMM32CE
589 && r_type
!= R_SH_IMAGEBASE
591 && (r_type
!= R_SH_PCDISP
592 || (symbol_in
->flags
& BSF_LOCAL
) != 0))
595 if (symbol_in
!= NULL
596 && bfd_is_und_section (symbol_in
->section
))
597 return bfd_reloc_undefined
;
599 if (addr
> input_section
->size
)
600 return bfd_reloc_outofrange
;
602 sym_value
= get_symbol_value (symbol_in
);
610 insn
= bfd_get_32 (abfd
, hit_data
);
611 insn
+= sym_value
+ reloc_entry
->addend
;
612 bfd_put_32 (abfd
, (bfd_vma
) insn
, hit_data
);
616 insn
= bfd_get_32 (abfd
, hit_data
);
617 insn
+= sym_value
+ reloc_entry
->addend
;
618 insn
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
619 bfd_put_32 (abfd
, (bfd_vma
) insn
, hit_data
);
623 insn
= bfd_get_16 (abfd
, hit_data
);
624 sym_value
+= reloc_entry
->addend
;
625 sym_value
-= (input_section
->output_section
->vma
626 + input_section
->output_offset
629 sym_value
+= (insn
& 0xfff) << 1;
632 insn
= (insn
& 0xf000) | (sym_value
& 0xfff);
633 bfd_put_16 (abfd
, (bfd_vma
) insn
, hit_data
);
634 if (sym_value
< (bfd_vma
) -0x1000 || sym_value
>= 0x1000)
635 return bfd_reloc_overflow
;
645 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
647 /* We can do relaxing. */
648 #define coff_bfd_relax_section sh_relax_section
650 /* We use the special COFF backend linker. */
651 #define coff_relocate_section sh_relocate_section
653 /* When relaxing, we need to use special code to get the relocated
655 #define coff_bfd_get_relocated_section_contents \
656 sh_coff_get_relocated_section_contents
658 #include "coffcode.h"
661 sh_relax_delete_bytes (bfd
*, asection
*, bfd_vma
, int);
663 /* This function handles relaxing on the SH.
665 Function calls on the SH look like this:
674 The compiler and assembler will cooperate to create R_SH_USES
675 relocs on the jsr instructions. The r_offset field of the
676 R_SH_USES reloc is the PC relative offset to the instruction which
677 loads the register (the r_offset field is computed as though it
678 were a jump instruction, so the offset value is actually from four
679 bytes past the instruction). The linker can use this reloc to
680 determine just which function is being called, and thus decide
681 whether it is possible to replace the jsr with a bsr.
683 If multiple function calls are all based on a single register load
684 (i.e., the same function is called multiple times), the compiler
685 guarantees that each function call will have an R_SH_USES reloc.
686 Therefore, if the linker is able to convert each R_SH_USES reloc
687 which refers to that address, it can safely eliminate the register
690 When the assembler creates an R_SH_USES reloc, it examines it to
691 determine which address is being loaded (L1 in the above example).
692 It then counts the number of references to that address, and
693 creates an R_SH_COUNT reloc at that address. The r_offset field of
694 the R_SH_COUNT reloc will be the number of references. If the
695 linker is able to eliminate a register load, it can use the
696 R_SH_COUNT reloc to see whether it can also eliminate the function
699 SH relaxing also handles another, unrelated, matter. On the SH, if
700 a load or store instruction is not aligned on a four byte boundary,
701 the memory cycle interferes with the 32 bit instruction fetch,
702 causing a one cycle bubble in the pipeline. Therefore, we try to
703 align load and store instructions on four byte boundaries if we
704 can, by swapping them with one of the adjacent instructions. */
707 sh_relax_section (bfd
*abfd
,
709 struct bfd_link_info
*link_info
,
712 struct internal_reloc
*internal_relocs
;
713 bfd_boolean have_code
;
714 struct internal_reloc
*irel
, *irelend
;
715 bfd_byte
*contents
= NULL
;
719 if (bfd_link_relocatable (link_info
)
720 || (sec
->flags
& SEC_RELOC
) == 0
721 || sec
->reloc_count
== 0)
724 if (coff_section_data (abfd
, sec
) == NULL
)
726 bfd_size_type amt
= sizeof (struct coff_section_tdata
);
727 sec
->used_by_bfd
= bfd_zalloc (abfd
, amt
);
728 if (sec
->used_by_bfd
== NULL
)
732 internal_relocs
= (_bfd_coff_read_internal_relocs
733 (abfd
, sec
, link_info
->keep_memory
,
734 (bfd_byte
*) NULL
, FALSE
,
735 (struct internal_reloc
*) NULL
));
736 if (internal_relocs
== NULL
)
741 irelend
= internal_relocs
+ sec
->reloc_count
;
742 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
744 bfd_vma laddr
, paddr
, symval
;
746 struct internal_reloc
*irelfn
, *irelscan
, *irelcount
;
747 struct internal_syment sym
;
750 if (irel
->r_type
== R_SH_CODE
)
753 if (irel
->r_type
!= R_SH_USES
)
756 /* Get the section contents. */
757 if (contents
== NULL
)
759 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
760 contents
= coff_section_data (abfd
, sec
)->contents
;
763 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
768 /* The r_offset field of the R_SH_USES reloc will point us to
769 the register load. The 4 is because the r_offset field is
770 computed as though it were a jump offset, which are based
771 from 4 bytes after the jump instruction. */
772 laddr
= irel
->r_vaddr
- sec
->vma
+ 4;
773 /* Careful to sign extend the 32-bit offset. */
774 laddr
+= ((irel
->r_offset
& 0xffffffff) ^ 0x80000000) - 0x80000000;
775 if (laddr
>= sec
->size
)
777 /* xgettext: c-format */
779 (_("%pB: %#" PRIx64
": warning: bad R_SH_USES offset"),
780 abfd
, (uint64_t) irel
->r_vaddr
);
783 insn
= bfd_get_16 (abfd
, contents
+ laddr
);
785 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
786 if ((insn
& 0xf000) != 0xd000)
789 /* xgettext: c-format */
790 (_("%pB: %#" PRIx64
": warning: R_SH_USES points to unrecognized insn %#x"),
791 abfd
, (uint64_t) irel
->r_vaddr
, insn
);
795 /* Get the address from which the register is being loaded. The
796 displacement in the mov.l instruction is quadrupled. It is a
797 displacement from four bytes after the movl instruction, but,
798 before adding in the PC address, two least significant bits
799 of the PC are cleared. We assume that the section is aligned
800 on a four byte boundary. */
803 paddr
+= (laddr
+ 4) &~ (bfd_vma
) 3;
804 if (paddr
>= sec
->size
)
807 /* xgettext: c-format */
808 (_("%pB: %#" PRIx64
": warning: bad R_SH_USES load offset"),
809 abfd
, (uint64_t) irel
->r_vaddr
);
813 /* Get the reloc for the address from which the register is
814 being loaded. This reloc will tell us which function is
815 actually being called. */
817 for (irelfn
= internal_relocs
; irelfn
< irelend
; irelfn
++)
818 if (irelfn
->r_vaddr
== paddr
820 && (irelfn
->r_type
== R_SH_IMM32
821 || irelfn
->r_type
== R_SH_IMM32CE
822 || irelfn
->r_type
== R_SH_IMAGEBASE
)
825 && irelfn
->r_type
== R_SH_IMM32
829 if (irelfn
>= irelend
)
832 /* xgettext: c-format */
833 (_("%pB: %#" PRIx64
": warning: could not find expected reloc"),
834 abfd
, (uint64_t) paddr
);
838 /* Get the value of the symbol referred to by the reloc. */
839 if (! _bfd_coff_get_external_symbols (abfd
))
841 bfd_coff_swap_sym_in (abfd
,
842 ((bfd_byte
*) obj_coff_external_syms (abfd
)
844 * bfd_coff_symesz (abfd
))),
846 if (sym
.n_scnum
!= 0 && sym
.n_scnum
!= sec
->target_index
)
849 /* xgettext: c-format */
850 (_("%pB: %#" PRIx64
": warning: symbol in unexpected section"),
851 abfd
, (uint64_t) paddr
);
855 if (sym
.n_sclass
!= C_EXT
)
857 symval
= (sym
.n_value
859 + sec
->output_section
->vma
860 + sec
->output_offset
);
864 struct coff_link_hash_entry
*h
;
866 h
= obj_coff_sym_hashes (abfd
)[irelfn
->r_symndx
];
867 BFD_ASSERT (h
!= NULL
);
868 if (h
->root
.type
!= bfd_link_hash_defined
869 && h
->root
.type
!= bfd_link_hash_defweak
)
871 /* This appears to be a reference to an undefined
872 symbol. Just ignore it--it will be caught by the
873 regular reloc processing. */
877 symval
= (h
->root
.u
.def
.value
878 + h
->root
.u
.def
.section
->output_section
->vma
879 + h
->root
.u
.def
.section
->output_offset
);
882 symval
+= bfd_get_32 (abfd
, contents
+ paddr
- sec
->vma
);
884 /* See if this function call can be shortened. */
888 + sec
->output_section
->vma
891 if (foff
< -0x1000 || foff
>= 0x1000)
893 /* After all that work, we can't shorten this function call. */
897 /* Shorten the function call. */
899 /* For simplicity of coding, we are going to modify the section
900 contents, the section relocs, and the BFD symbol table. We
901 must tell the rest of the code not to free up this
902 information. It would be possible to instead create a table
903 of changes which have to be made, as is done in coff-mips.c;
904 that would be more work, but would require less memory when
905 the linker is run. */
907 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
908 coff_section_data (abfd
, sec
)->keep_relocs
= TRUE
;
910 coff_section_data (abfd
, sec
)->contents
= contents
;
911 coff_section_data (abfd
, sec
)->keep_contents
= TRUE
;
913 obj_coff_keep_syms (abfd
) = TRUE
;
915 /* Replace the jsr with a bsr. */
917 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
918 replace the jsr with a bsr. */
919 irel
->r_type
= R_SH_PCDISP
;
920 irel
->r_symndx
= irelfn
->r_symndx
;
921 if (sym
.n_sclass
!= C_EXT
)
923 /* If this needs to be changed because of future relaxing,
924 it will be handled here like other internal PCDISP
927 (bfd_vma
) 0xb000 | ((foff
>> 1) & 0xfff),
928 contents
+ irel
->r_vaddr
- sec
->vma
);
932 /* We can't fully resolve this yet, because the external
933 symbol value may be changed by future relaxing. We let
934 the final link phase handle it. */
935 bfd_put_16 (abfd
, (bfd_vma
) 0xb000,
936 contents
+ irel
->r_vaddr
- sec
->vma
);
939 /* See if there is another R_SH_USES reloc referring to the same
941 for (irelscan
= internal_relocs
; irelscan
< irelend
; irelscan
++)
942 if (irelscan
->r_type
== R_SH_USES
943 && laddr
== irelscan
->r_vaddr
- sec
->vma
+ 4 + irelscan
->r_offset
)
945 if (irelscan
< irelend
)
947 /* Some other function call depends upon this register load,
948 and we have not yet converted that function call.
949 Indeed, we may never be able to convert it. There is
950 nothing else we can do at this point. */
954 /* Look for a R_SH_COUNT reloc on the location where the
955 function address is stored. Do this before deleting any
956 bytes, to avoid confusion about the address. */
957 for (irelcount
= internal_relocs
; irelcount
< irelend
; irelcount
++)
958 if (irelcount
->r_vaddr
== paddr
959 && irelcount
->r_type
== R_SH_COUNT
)
962 /* Delete the register load. */
963 if (! sh_relax_delete_bytes (abfd
, sec
, laddr
, 2))
966 /* That will change things, so, just in case it permits some
967 other function call to come within range, we should relax
968 again. Note that this is not required, and it may be slow. */
971 /* Now check whether we got a COUNT reloc. */
972 if (irelcount
>= irelend
)
975 /* xgettext: c-format */
976 (_("%pB: %#" PRIx64
": warning: could not find expected COUNT reloc"),
977 abfd
, (uint64_t) paddr
);
981 /* The number of uses is stored in the r_offset field. We've
983 if (irelcount
->r_offset
== 0)
985 /* xgettext: c-format */
986 _bfd_error_handler (_("%pB: %#" PRIx64
": warning: bad count"),
987 abfd
, (uint64_t) paddr
);
991 --irelcount
->r_offset
;
993 /* If there are no more uses, we can delete the address. Reload
994 the address from irelfn, in case it was changed by the
995 previous call to sh_relax_delete_bytes. */
996 if (irelcount
->r_offset
== 0)
998 if (! sh_relax_delete_bytes (abfd
, sec
,
999 irelfn
->r_vaddr
- sec
->vma
, 4))
1003 /* We've done all we can with that function call. */
1006 /* Look for load and store instructions that we can align on four
1010 bfd_boolean swapped
;
1012 /* Get the section contents. */
1013 if (contents
== NULL
)
1015 if (coff_section_data (abfd
, sec
)->contents
!= NULL
)
1016 contents
= coff_section_data (abfd
, sec
)->contents
;
1019 if (!bfd_malloc_and_get_section (abfd
, sec
, &contents
))
1024 if (! sh_align_loads (abfd
, sec
, internal_relocs
, contents
, &swapped
))
1029 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1030 coff_section_data (abfd
, sec
)->keep_relocs
= TRUE
;
1032 coff_section_data (abfd
, sec
)->contents
= contents
;
1033 coff_section_data (abfd
, sec
)->keep_contents
= TRUE
;
1035 obj_coff_keep_syms (abfd
) = TRUE
;
1039 if (internal_relocs
!= NULL
1040 && internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1042 if (! link_info
->keep_memory
)
1043 free (internal_relocs
);
1045 coff_section_data (abfd
, sec
)->relocs
= internal_relocs
;
1048 if (contents
!= NULL
&& contents
!= coff_section_data (abfd
, sec
)->contents
)
1050 if (! link_info
->keep_memory
)
1053 /* Cache the section contents for coff_link_input_bfd. */
1054 coff_section_data (abfd
, sec
)->contents
= contents
;
1060 if (internal_relocs
!= NULL
1061 && internal_relocs
!= coff_section_data (abfd
, sec
)->relocs
)
1062 free (internal_relocs
);
1063 if (contents
!= NULL
&& contents
!= coff_section_data (abfd
, sec
)->contents
)
1068 /* Delete some bytes from a section while relaxing. */
1071 sh_relax_delete_bytes (bfd
*abfd
,
1077 struct internal_reloc
*irel
, *irelend
;
1078 struct internal_reloc
*irelalign
;
1080 bfd_byte
*esym
, *esymend
;
1081 bfd_size_type symesz
;
1082 struct coff_link_hash_entry
**sym_hash
;
1085 contents
= coff_section_data (abfd
, sec
)->contents
;
1087 /* The deletion must stop at the next ALIGN reloc for an alignment
1088 power larger than the number of bytes we are deleting. */
1093 irel
= coff_section_data (abfd
, sec
)->relocs
;
1094 irelend
= irel
+ sec
->reloc_count
;
1095 for (; irel
< irelend
; irel
++)
1097 if (irel
->r_type
== R_SH_ALIGN
1098 && irel
->r_vaddr
- sec
->vma
> addr
1099 && count
< (1 << irel
->r_offset
))
1102 toaddr
= irel
->r_vaddr
- sec
->vma
;
1107 /* Actually delete the bytes. */
1108 memmove (contents
+ addr
, contents
+ addr
+ count
,
1109 (size_t) (toaddr
- addr
- count
));
1110 if (irelalign
== NULL
)
1116 #define NOP_OPCODE (0x0009)
1118 BFD_ASSERT ((count
& 1) == 0);
1119 for (i
= 0; i
< count
; i
+= 2)
1120 bfd_put_16 (abfd
, (bfd_vma
) NOP_OPCODE
, contents
+ toaddr
- count
+ i
);
1123 /* Adjust all the relocs. */
1124 for (irel
= coff_section_data (abfd
, sec
)->relocs
; irel
< irelend
; irel
++)
1126 bfd_vma nraddr
, stop
;
1129 struct internal_syment sym
;
1130 int off
, adjust
, oinsn
;
1131 bfd_signed_vma voff
= 0;
1132 bfd_boolean overflow
;
1134 /* Get the new reloc address. */
1135 nraddr
= irel
->r_vaddr
- sec
->vma
;
1136 if ((irel
->r_vaddr
- sec
->vma
> addr
1137 && irel
->r_vaddr
- sec
->vma
< toaddr
)
1138 || (irel
->r_type
== R_SH_ALIGN
1139 && irel
->r_vaddr
- sec
->vma
== toaddr
))
1142 /* See if this reloc was for the bytes we have deleted, in which
1143 case we no longer care about it. Don't delete relocs which
1144 represent addresses, though. */
1145 if (irel
->r_vaddr
- sec
->vma
>= addr
1146 && irel
->r_vaddr
- sec
->vma
< addr
+ count
1147 && irel
->r_type
!= R_SH_ALIGN
1148 && irel
->r_type
!= R_SH_CODE
1149 && irel
->r_type
!= R_SH_DATA
1150 && irel
->r_type
!= R_SH_LABEL
)
1151 irel
->r_type
= R_SH_UNUSED
;
1153 /* If this is a PC relative reloc, see if the range it covers
1154 includes the bytes we have deleted. */
1155 switch (irel
->r_type
)
1160 case R_SH_PCDISP8BY2
:
1162 case R_SH_PCRELIMM8BY2
:
1163 case R_SH_PCRELIMM8BY4
:
1164 start
= irel
->r_vaddr
- sec
->vma
;
1165 insn
= bfd_get_16 (abfd
, contents
+ nraddr
);
1169 switch (irel
->r_type
)
1172 start
= stop
= addr
;
1178 case R_SH_IMAGEBASE
:
1180 /* If this reloc is against a symbol defined in this
1181 section, and the symbol will not be adjusted below, we
1182 must check the addend to see it will put the value in
1183 range to be adjusted, and hence must be changed. */
1184 bfd_coff_swap_sym_in (abfd
,
1185 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1187 * bfd_coff_symesz (abfd
))),
1189 if (sym
.n_sclass
!= C_EXT
1190 && sym
.n_scnum
== sec
->target_index
1191 && ((bfd_vma
) sym
.n_value
<= addr
1192 || (bfd_vma
) sym
.n_value
>= toaddr
))
1196 val
= bfd_get_32 (abfd
, contents
+ nraddr
);
1198 if (val
> addr
&& val
< toaddr
)
1199 bfd_put_32 (abfd
, val
- count
, contents
+ nraddr
);
1201 start
= stop
= addr
;
1204 case R_SH_PCDISP8BY2
:
1208 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1212 bfd_coff_swap_sym_in (abfd
,
1213 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1215 * bfd_coff_symesz (abfd
))),
1217 if (sym
.n_sclass
== C_EXT
)
1218 start
= stop
= addr
;
1224 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ 4 + off
* 2);
1228 case R_SH_PCRELIMM8BY2
:
1230 stop
= start
+ 4 + off
* 2;
1233 case R_SH_PCRELIMM8BY4
:
1235 stop
= (start
&~ (bfd_vma
) 3) + 4 + off
* 4;
1241 /* These relocs types represent
1243 The r_offset field holds the difference between the reloc
1244 address and L1. That is the start of the reloc, and
1245 adding in the contents gives us the top. We must adjust
1246 both the r_offset field and the section contents. */
1248 start
= irel
->r_vaddr
- sec
->vma
;
1249 stop
= (bfd_vma
) ((bfd_signed_vma
) start
- (long) irel
->r_offset
);
1253 && (stop
<= addr
|| stop
>= toaddr
))
1254 irel
->r_offset
+= count
;
1255 else if (stop
> addr
1257 && (start
<= addr
|| start
>= toaddr
))
1258 irel
->r_offset
-= count
;
1262 if (irel
->r_type
== R_SH_SWITCH16
)
1263 voff
= bfd_get_signed_16 (abfd
, contents
+ nraddr
);
1264 else if (irel
->r_type
== R_SH_SWITCH8
)
1265 voff
= bfd_get_8 (abfd
, contents
+ nraddr
);
1267 voff
= bfd_get_signed_32 (abfd
, contents
+ nraddr
);
1268 stop
= (bfd_vma
) ((bfd_signed_vma
) start
+ voff
);
1273 start
= irel
->r_vaddr
- sec
->vma
;
1274 stop
= (bfd_vma
) ((bfd_signed_vma
) start
1275 + (long) irel
->r_offset
1282 && (stop
<= addr
|| stop
>= toaddr
))
1284 else if (stop
> addr
1286 && (start
<= addr
|| start
>= toaddr
))
1295 switch (irel
->r_type
)
1301 case R_SH_PCDISP8BY2
:
1302 case R_SH_PCRELIMM8BY2
:
1304 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1306 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1311 if ((oinsn
& 0xf000) != (insn
& 0xf000))
1313 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1316 case R_SH_PCRELIMM8BY4
:
1317 BFD_ASSERT (adjust
== count
|| count
>= 4);
1322 if ((irel
->r_vaddr
& 3) == 0)
1325 if ((oinsn
& 0xff00) != (insn
& 0xff00))
1327 bfd_put_16 (abfd
, (bfd_vma
) insn
, contents
+ nraddr
);
1332 if (voff
< 0 || voff
>= 0xff)
1334 bfd_put_8 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1339 if (voff
< - 0x8000 || voff
>= 0x8000)
1341 bfd_put_signed_16 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1346 bfd_put_signed_32 (abfd
, (bfd_vma
) voff
, contents
+ nraddr
);
1350 irel
->r_offset
+= adjust
;
1357 /* xgettext: c-format */
1358 (_("%pB: %#" PRIx64
": fatal: reloc overflow while relaxing"),
1359 abfd
, (uint64_t) irel
->r_vaddr
);
1360 bfd_set_error (bfd_error_bad_value
);
1365 irel
->r_vaddr
= nraddr
+ sec
->vma
;
1368 /* Look through all the other sections. If there contain any IMM32
1369 relocs against internal symbols which we are not going to adjust
1370 below, we may need to adjust the addends. */
1371 for (o
= abfd
->sections
; o
!= NULL
; o
= o
->next
)
1373 struct internal_reloc
*internal_relocs
;
1374 struct internal_reloc
*irelscan
, *irelscanend
;
1375 bfd_byte
*ocontents
;
1378 || (o
->flags
& SEC_RELOC
) == 0
1379 || o
->reloc_count
== 0)
1382 /* We always cache the relocs. Perhaps, if info->keep_memory is
1383 FALSE, we should free them, if we are permitted to, when we
1384 leave sh_coff_relax_section. */
1385 internal_relocs
= (_bfd_coff_read_internal_relocs
1386 (abfd
, o
, TRUE
, (bfd_byte
*) NULL
, FALSE
,
1387 (struct internal_reloc
*) NULL
));
1388 if (internal_relocs
== NULL
)
1392 irelscanend
= internal_relocs
+ o
->reloc_count
;
1393 for (irelscan
= internal_relocs
; irelscan
< irelscanend
; irelscan
++)
1395 struct internal_syment sym
;
1398 if (irelscan
->r_type
!= R_SH_IMM32
1399 && irelscan
->r_type
!= R_SH_IMAGEBASE
1400 && irelscan
->r_type
!= R_SH_IMM32CE
)
1402 if (irelscan
->r_type
!= R_SH_IMM32
)
1406 bfd_coff_swap_sym_in (abfd
,
1407 ((bfd_byte
*) obj_coff_external_syms (abfd
)
1408 + (irelscan
->r_symndx
1409 * bfd_coff_symesz (abfd
))),
1411 if (sym
.n_sclass
!= C_EXT
1412 && sym
.n_scnum
== sec
->target_index
1413 && ((bfd_vma
) sym
.n_value
<= addr
1414 || (bfd_vma
) sym
.n_value
>= toaddr
))
1418 if (ocontents
== NULL
)
1420 if (coff_section_data (abfd
, o
)->contents
!= NULL
)
1421 ocontents
= coff_section_data (abfd
, o
)->contents
;
1424 if (!bfd_malloc_and_get_section (abfd
, o
, &ocontents
))
1426 /* We always cache the section contents.
1427 Perhaps, if info->keep_memory is FALSE, we
1428 should free them, if we are permitted to,
1429 when we leave sh_coff_relax_section. */
1430 coff_section_data (abfd
, o
)->contents
= ocontents
;
1434 val
= bfd_get_32 (abfd
, ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1436 if (val
> addr
&& val
< toaddr
)
1437 bfd_put_32 (abfd
, val
- count
,
1438 ocontents
+ irelscan
->r_vaddr
- o
->vma
);
1440 coff_section_data (abfd
, o
)->keep_contents
= TRUE
;
1445 /* Adjusting the internal symbols will not work if something has
1446 already retrieved the generic symbols. It would be possible to
1447 make this work by adjusting the generic symbols at the same time.
1448 However, this case should not arise in normal usage. */
1449 if (obj_symbols (abfd
) != NULL
1450 || obj_raw_syments (abfd
) != NULL
)
1453 (_("%pB: fatal: generic symbols retrieved before relaxing"), abfd
);
1454 bfd_set_error (bfd_error_invalid_operation
);
1458 /* Adjust all the symbols. */
1459 sym_hash
= obj_coff_sym_hashes (abfd
);
1460 symesz
= bfd_coff_symesz (abfd
);
1461 esym
= (bfd_byte
*) obj_coff_external_syms (abfd
);
1462 esymend
= esym
+ obj_raw_syment_count (abfd
) * symesz
;
1463 while (esym
< esymend
)
1465 struct internal_syment isym
;
1467 bfd_coff_swap_sym_in (abfd
, esym
, &isym
);
1469 if (isym
.n_scnum
== sec
->target_index
1470 && (bfd_vma
) isym
.n_value
> addr
1471 && (bfd_vma
) isym
.n_value
< toaddr
)
1473 isym
.n_value
-= count
;
1475 bfd_coff_swap_sym_out (abfd
, &isym
, esym
);
1477 if (*sym_hash
!= NULL
)
1479 BFD_ASSERT ((*sym_hash
)->root
.type
== bfd_link_hash_defined
1480 || (*sym_hash
)->root
.type
== bfd_link_hash_defweak
);
1481 BFD_ASSERT ((*sym_hash
)->root
.u
.def
.value
>= addr
1482 && (*sym_hash
)->root
.u
.def
.value
< toaddr
);
1483 (*sym_hash
)->root
.u
.def
.value
-= count
;
1487 esym
+= (isym
.n_numaux
+ 1) * symesz
;
1488 sym_hash
+= isym
.n_numaux
+ 1;
1491 /* See if we can move the ALIGN reloc forward. We have adjusted
1492 r_vaddr for it already. */
1493 if (irelalign
!= NULL
)
1495 bfd_vma alignto
, alignaddr
;
1497 alignto
= BFD_ALIGN (toaddr
, 1 << irelalign
->r_offset
);
1498 alignaddr
= BFD_ALIGN (irelalign
->r_vaddr
- sec
->vma
,
1499 1 << irelalign
->r_offset
);
1500 if (alignto
!= alignaddr
)
1502 /* Tail recursion. */
1503 return sh_relax_delete_bytes (abfd
, sec
, alignaddr
,
1504 (int) (alignto
- alignaddr
));
1511 /* This is yet another version of the SH opcode table, used to rapidly
1512 get information about a particular instruction. */
1514 /* The opcode map is represented by an array of these structures. The
1515 array is indexed by the high order four bits in the instruction. */
1517 struct sh_major_opcode
1519 /* A pointer to the instruction list. This is an array which
1520 contains all the instructions with this major opcode. */
1521 const struct sh_minor_opcode
*minor_opcodes
;
1522 /* The number of elements in minor_opcodes. */
1523 unsigned short count
;
1526 /* This structure holds information for a set of SH opcodes. The
1527 instruction code is anded with the mask value, and the resulting
1528 value is used to search the order opcode list. */
1530 struct sh_minor_opcode
1532 /* The sorted opcode list. */
1533 const struct sh_opcode
*opcodes
;
1534 /* The number of elements in opcodes. */
1535 unsigned short count
;
1536 /* The mask value to use when searching the opcode list. */
1537 unsigned short mask
;
1540 /* This structure holds information for an SH instruction. An array
1541 of these structures is sorted in order by opcode. */
1545 /* The code for this instruction, after it has been anded with the
1546 mask value in the sh_major_opcode structure. */
1547 unsigned short opcode
;
1548 /* Flags for this instruction. */
1549 unsigned long flags
;
1552 /* Flag which appear in the sh_opcode structure. */
1554 /* This instruction loads a value from memory. */
1557 /* This instruction stores a value to memory. */
1560 /* This instruction is a branch. */
1561 #define BRANCH (0x4)
1563 /* This instruction has a delay slot. */
1566 /* This instruction uses the value in the register in the field at
1567 mask 0x0f00 of the instruction. */
1568 #define USES1 (0x10)
1569 #define USES1_REG(x) ((x & 0x0f00) >> 8)
1571 /* This instruction uses the value in the register in the field at
1572 mask 0x00f0 of the instruction. */
1573 #define USES2 (0x20)
1574 #define USES2_REG(x) ((x & 0x00f0) >> 4)
1576 /* This instruction uses the value in register 0. */
1577 #define USESR0 (0x40)
1579 /* This instruction sets the value in the register in the field at
1580 mask 0x0f00 of the instruction. */
1581 #define SETS1 (0x80)
1582 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
1584 /* This instruction sets the value in the register in the field at
1585 mask 0x00f0 of the instruction. */
1586 #define SETS2 (0x100)
1587 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
1589 /* This instruction sets register 0. */
1590 #define SETSR0 (0x200)
1592 /* This instruction sets a special register. */
1593 #define SETSSP (0x400)
1595 /* This instruction uses a special register. */
1596 #define USESSP (0x800)
1598 /* This instruction uses the floating point register in the field at
1599 mask 0x0f00 of the instruction. */
1600 #define USESF1 (0x1000)
1601 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
1603 /* This instruction uses the floating point register in the field at
1604 mask 0x00f0 of the instruction. */
1605 #define USESF2 (0x2000)
1606 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
1608 /* This instruction uses floating point register 0. */
1609 #define USESF0 (0x4000)
1611 /* This instruction sets the floating point register in the field at
1612 mask 0x0f00 of the instruction. */
1613 #define SETSF1 (0x8000)
1614 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1616 #define USESAS (0x10000)
1617 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1618 #define USESR8 (0x20000)
1619 #define SETSAS (0x40000)
1620 #define SETSAS_REG(x) USESAS_REG (x)
1622 #define MAP(a) a, sizeof a / sizeof a[0]
1624 #ifndef COFF_IMAGE_WITH_PE
1626 /* The opcode maps. */
1628 static const struct sh_opcode sh_opcode00
[] =
1630 { 0x0008, SETSSP
}, /* clrt */
1631 { 0x0009, 0 }, /* nop */
1632 { 0x000b, BRANCH
| DELAY
| USESSP
}, /* rts */
1633 { 0x0018, SETSSP
}, /* sett */
1634 { 0x0019, SETSSP
}, /* div0u */
1635 { 0x001b, 0 }, /* sleep */
1636 { 0x0028, SETSSP
}, /* clrmac */
1637 { 0x002b, BRANCH
| DELAY
| SETSSP
}, /* rte */
1638 { 0x0038, USESSP
| SETSSP
}, /* ldtlb */
1639 { 0x0048, SETSSP
}, /* clrs */
1640 { 0x0058, SETSSP
} /* sets */
1643 static const struct sh_opcode sh_opcode01
[] =
1645 { 0x0003, BRANCH
| DELAY
| USES1
| SETSSP
}, /* bsrf rn */
1646 { 0x000a, SETS1
| USESSP
}, /* sts mach,rn */
1647 { 0x001a, SETS1
| USESSP
}, /* sts macl,rn */
1648 { 0x0023, BRANCH
| DELAY
| USES1
}, /* braf rn */
1649 { 0x0029, SETS1
| USESSP
}, /* movt rn */
1650 { 0x002a, SETS1
| USESSP
}, /* sts pr,rn */
1651 { 0x005a, SETS1
| USESSP
}, /* sts fpul,rn */
1652 { 0x006a, SETS1
| USESSP
}, /* sts fpscr,rn / sts dsr,rn */
1653 { 0x0083, LOAD
| USES1
}, /* pref @rn */
1654 { 0x007a, SETS1
| USESSP
}, /* sts a0,rn */
1655 { 0x008a, SETS1
| USESSP
}, /* sts x0,rn */
1656 { 0x009a, SETS1
| USESSP
}, /* sts x1,rn */
1657 { 0x00aa, SETS1
| USESSP
}, /* sts y0,rn */
1658 { 0x00ba, SETS1
| USESSP
} /* sts y1,rn */
1661 static const struct sh_opcode sh_opcode02
[] =
1663 { 0x0002, SETS1
| USESSP
}, /* stc <special_reg>,rn */
1664 { 0x0004, STORE
| USES1
| USES2
| USESR0
}, /* mov.b rm,@(r0,rn) */
1665 { 0x0005, STORE
| USES1
| USES2
| USESR0
}, /* mov.w rm,@(r0,rn) */
1666 { 0x0006, STORE
| USES1
| USES2
| USESR0
}, /* mov.l rm,@(r0,rn) */
1667 { 0x0007, SETSSP
| USES1
| USES2
}, /* mul.l rm,rn */
1668 { 0x000c, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.b @(r0,rm),rn */
1669 { 0x000d, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.w @(r0,rm),rn */
1670 { 0x000e, LOAD
| SETS1
| USES2
| USESR0
}, /* mov.l @(r0,rm),rn */
1671 { 0x000f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.l @rm+,@rn+ */
1674 static const struct sh_minor_opcode sh_opcode0
[] =
1676 { MAP (sh_opcode00
), 0xffff },
1677 { MAP (sh_opcode01
), 0xf0ff },
1678 { MAP (sh_opcode02
), 0xf00f }
1681 static const struct sh_opcode sh_opcode10
[] =
1683 { 0x1000, STORE
| USES1
| USES2
} /* mov.l rm,@(disp,rn) */
1686 static const struct sh_minor_opcode sh_opcode1
[] =
1688 { MAP (sh_opcode10
), 0xf000 }
1691 static const struct sh_opcode sh_opcode20
[] =
1693 { 0x2000, STORE
| USES1
| USES2
}, /* mov.b rm,@rn */
1694 { 0x2001, STORE
| USES1
| USES2
}, /* mov.w rm,@rn */
1695 { 0x2002, STORE
| USES1
| USES2
}, /* mov.l rm,@rn */
1696 { 0x2004, STORE
| SETS1
| USES1
| USES2
}, /* mov.b rm,@-rn */
1697 { 0x2005, STORE
| SETS1
| USES1
| USES2
}, /* mov.w rm,@-rn */
1698 { 0x2006, STORE
| SETS1
| USES1
| USES2
}, /* mov.l rm,@-rn */
1699 { 0x2007, SETSSP
| USES1
| USES2
| USESSP
}, /* div0s */
1700 { 0x2008, SETSSP
| USES1
| USES2
}, /* tst rm,rn */
1701 { 0x2009, SETS1
| USES1
| USES2
}, /* and rm,rn */
1702 { 0x200a, SETS1
| USES1
| USES2
}, /* xor rm,rn */
1703 { 0x200b, SETS1
| USES1
| USES2
}, /* or rm,rn */
1704 { 0x200c, SETSSP
| USES1
| USES2
}, /* cmp/str rm,rn */
1705 { 0x200d, SETS1
| USES1
| USES2
}, /* xtrct rm,rn */
1706 { 0x200e, SETSSP
| USES1
| USES2
}, /* mulu.w rm,rn */
1707 { 0x200f, SETSSP
| USES1
| USES2
} /* muls.w rm,rn */
1710 static const struct sh_minor_opcode sh_opcode2
[] =
1712 { MAP (sh_opcode20
), 0xf00f }
1715 static const struct sh_opcode sh_opcode30
[] =
1717 { 0x3000, SETSSP
| USES1
| USES2
}, /* cmp/eq rm,rn */
1718 { 0x3002, SETSSP
| USES1
| USES2
}, /* cmp/hs rm,rn */
1719 { 0x3003, SETSSP
| USES1
| USES2
}, /* cmp/ge rm,rn */
1720 { 0x3004, SETSSP
| USESSP
| USES1
| USES2
}, /* div1 rm,rn */
1721 { 0x3005, SETSSP
| USES1
| USES2
}, /* dmulu.l rm,rn */
1722 { 0x3006, SETSSP
| USES1
| USES2
}, /* cmp/hi rm,rn */
1723 { 0x3007, SETSSP
| USES1
| USES2
}, /* cmp/gt rm,rn */
1724 { 0x3008, SETS1
| USES1
| USES2
}, /* sub rm,rn */
1725 { 0x300a, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* subc rm,rn */
1726 { 0x300b, SETS1
| SETSSP
| USES1
| USES2
}, /* subv rm,rn */
1727 { 0x300c, SETS1
| USES1
| USES2
}, /* add rm,rn */
1728 { 0x300d, SETSSP
| USES1
| USES2
}, /* dmuls.l rm,rn */
1729 { 0x300e, SETS1
| SETSSP
| USES1
| USES2
| USESSP
}, /* addc rm,rn */
1730 { 0x300f, SETS1
| SETSSP
| USES1
| USES2
} /* addv rm,rn */
1733 static const struct sh_minor_opcode sh_opcode3
[] =
1735 { MAP (sh_opcode30
), 0xf00f }
1738 static const struct sh_opcode sh_opcode40
[] =
1740 { 0x4000, SETS1
| SETSSP
| USES1
}, /* shll rn */
1741 { 0x4001, SETS1
| SETSSP
| USES1
}, /* shlr rn */
1742 { 0x4002, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l mach,@-rn */
1743 { 0x4004, SETS1
| SETSSP
| USES1
}, /* rotl rn */
1744 { 0x4005, SETS1
| SETSSP
| USES1
}, /* rotr rn */
1745 { 0x4006, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,mach */
1746 { 0x4008, SETS1
| USES1
}, /* shll2 rn */
1747 { 0x4009, SETS1
| USES1
}, /* shlr2 rn */
1748 { 0x400a, SETSSP
| USES1
}, /* lds rm,mach */
1749 { 0x400b, BRANCH
| DELAY
| USES1
}, /* jsr @rn */
1750 { 0x4010, SETS1
| SETSSP
| USES1
}, /* dt rn */
1751 { 0x4011, SETSSP
| USES1
}, /* cmp/pz rn */
1752 { 0x4012, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l macl,@-rn */
1753 { 0x4014, SETSSP
| USES1
}, /* setrc rm */
1754 { 0x4015, SETSSP
| USES1
}, /* cmp/pl rn */
1755 { 0x4016, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,macl */
1756 { 0x4018, SETS1
| USES1
}, /* shll8 rn */
1757 { 0x4019, SETS1
| USES1
}, /* shlr8 rn */
1758 { 0x401a, SETSSP
| USES1
}, /* lds rm,macl */
1759 { 0x401b, LOAD
| SETSSP
| USES1
}, /* tas.b @rn */
1760 { 0x4020, SETS1
| SETSSP
| USES1
}, /* shal rn */
1761 { 0x4021, SETS1
| SETSSP
| USES1
}, /* shar rn */
1762 { 0x4022, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l pr,@-rn */
1763 { 0x4024, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcl rn */
1764 { 0x4025, SETS1
| SETSSP
| USES1
| USESSP
}, /* rotcr rn */
1765 { 0x4026, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,pr */
1766 { 0x4028, SETS1
| USES1
}, /* shll16 rn */
1767 { 0x4029, SETS1
| USES1
}, /* shlr16 rn */
1768 { 0x402a, SETSSP
| USES1
}, /* lds rm,pr */
1769 { 0x402b, BRANCH
| DELAY
| USES1
}, /* jmp @rn */
1770 { 0x4052, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpul,@-rn */
1771 { 0x4056, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpul */
1772 { 0x405a, SETSSP
| USES1
}, /* lds.l rm,fpul */
1773 { 0x4062, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l fpscr / dsr,@-rn */
1774 { 0x4066, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,fpscr / dsr */
1775 { 0x406a, SETSSP
| USES1
}, /* lds rm,fpscr / lds rm,dsr */
1776 { 0x4072, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l a0,@-rn */
1777 { 0x4076, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,a0 */
1778 { 0x407a, SETSSP
| USES1
}, /* lds.l rm,a0 */
1779 { 0x4082, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x0,@-rn */
1780 { 0x4086, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x0 */
1781 { 0x408a, SETSSP
| USES1
}, /* lds.l rm,x0 */
1782 { 0x4092, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l x1,@-rn */
1783 { 0x4096, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,x1 */
1784 { 0x409a, SETSSP
| USES1
}, /* lds.l rm,x1 */
1785 { 0x40a2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y0,@-rn */
1786 { 0x40a6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y0 */
1787 { 0x40aa, SETSSP
| USES1
}, /* lds.l rm,y0 */
1788 { 0x40b2, STORE
| SETS1
| USES1
| USESSP
}, /* sts.l y1,@-rn */
1789 { 0x40b6, LOAD
| SETS1
| SETSSP
| USES1
}, /* lds.l @rm+,y1 */
1790 { 0x40ba, SETSSP
| USES1
} /* lds.l rm,y1 */
1793 static const struct sh_opcode sh_opcode41
[] =
1795 { 0x4003, STORE
| SETS1
| USES1
| USESSP
}, /* stc.l <special_reg>,@-rn */
1796 { 0x4007, LOAD
| SETS1
| SETSSP
| USES1
}, /* ldc.l @rm+,<special_reg> */
1797 { 0x400c, SETS1
| USES1
| USES2
}, /* shad rm,rn */
1798 { 0x400d, SETS1
| USES1
| USES2
}, /* shld rm,rn */
1799 { 0x400e, SETSSP
| USES1
}, /* ldc rm,<special_reg> */
1800 { 0x400f, LOAD
|SETS1
|SETS2
|SETSSP
|USES1
|USES2
|USESSP
}, /* mac.w @rm+,@rn+ */
1803 static const struct sh_minor_opcode sh_opcode4
[] =
1805 { MAP (sh_opcode40
), 0xf0ff },
1806 { MAP (sh_opcode41
), 0xf00f }
1809 static const struct sh_opcode sh_opcode50
[] =
1811 { 0x5000, LOAD
| SETS1
| USES2
} /* mov.l @(disp,rm),rn */
1814 static const struct sh_minor_opcode sh_opcode5
[] =
1816 { MAP (sh_opcode50
), 0xf000 }
1819 static const struct sh_opcode sh_opcode60
[] =
1821 { 0x6000, LOAD
| SETS1
| USES2
}, /* mov.b @rm,rn */
1822 { 0x6001, LOAD
| SETS1
| USES2
}, /* mov.w @rm,rn */
1823 { 0x6002, LOAD
| SETS1
| USES2
}, /* mov.l @rm,rn */
1824 { 0x6003, SETS1
| USES2
}, /* mov rm,rn */
1825 { 0x6004, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.b @rm+,rn */
1826 { 0x6005, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.w @rm+,rn */
1827 { 0x6006, LOAD
| SETS1
| SETS2
| USES2
}, /* mov.l @rm+,rn */
1828 { 0x6007, SETS1
| USES2
}, /* not rm,rn */
1829 { 0x6008, SETS1
| USES2
}, /* swap.b rm,rn */
1830 { 0x6009, SETS1
| USES2
}, /* swap.w rm,rn */
1831 { 0x600a, SETS1
| SETSSP
| USES2
| USESSP
}, /* negc rm,rn */
1832 { 0x600b, SETS1
| USES2
}, /* neg rm,rn */
1833 { 0x600c, SETS1
| USES2
}, /* extu.b rm,rn */
1834 { 0x600d, SETS1
| USES2
}, /* extu.w rm,rn */
1835 { 0x600e, SETS1
| USES2
}, /* exts.b rm,rn */
1836 { 0x600f, SETS1
| USES2
} /* exts.w rm,rn */
1839 static const struct sh_minor_opcode sh_opcode6
[] =
1841 { MAP (sh_opcode60
), 0xf00f }
1844 static const struct sh_opcode sh_opcode70
[] =
1846 { 0x7000, SETS1
| USES1
} /* add #imm,rn */
1849 static const struct sh_minor_opcode sh_opcode7
[] =
1851 { MAP (sh_opcode70
), 0xf000 }
1854 static const struct sh_opcode sh_opcode80
[] =
1856 { 0x8000, STORE
| USES2
| USESR0
}, /* mov.b r0,@(disp,rn) */
1857 { 0x8100, STORE
| USES2
| USESR0
}, /* mov.w r0,@(disp,rn) */
1858 { 0x8200, SETSSP
}, /* setrc #imm */
1859 { 0x8400, LOAD
| SETSR0
| USES2
}, /* mov.b @(disp,rm),r0 */
1860 { 0x8500, LOAD
| SETSR0
| USES2
}, /* mov.w @(disp,rn),r0 */
1861 { 0x8800, SETSSP
| USESR0
}, /* cmp/eq #imm,r0 */
1862 { 0x8900, BRANCH
| USESSP
}, /* bt label */
1863 { 0x8b00, BRANCH
| USESSP
}, /* bf label */
1864 { 0x8c00, SETSSP
}, /* ldrs @(disp,pc) */
1865 { 0x8d00, BRANCH
| DELAY
| USESSP
}, /* bt/s label */
1866 { 0x8e00, SETSSP
}, /* ldre @(disp,pc) */
1867 { 0x8f00, BRANCH
| DELAY
| USESSP
} /* bf/s label */
1870 static const struct sh_minor_opcode sh_opcode8
[] =
1872 { MAP (sh_opcode80
), 0xff00 }
1875 static const struct sh_opcode sh_opcode90
[] =
1877 { 0x9000, LOAD
| SETS1
} /* mov.w @(disp,pc),rn */
1880 static const struct sh_minor_opcode sh_opcode9
[] =
1882 { MAP (sh_opcode90
), 0xf000 }
1885 static const struct sh_opcode sh_opcodea0
[] =
1887 { 0xa000, BRANCH
| DELAY
} /* bra label */
1890 static const struct sh_minor_opcode sh_opcodea
[] =
1892 { MAP (sh_opcodea0
), 0xf000 }
1895 static const struct sh_opcode sh_opcodeb0
[] =
1897 { 0xb000, BRANCH
| DELAY
} /* bsr label */
1900 static const struct sh_minor_opcode sh_opcodeb
[] =
1902 { MAP (sh_opcodeb0
), 0xf000 }
1905 static const struct sh_opcode sh_opcodec0
[] =
1907 { 0xc000, STORE
| USESR0
| USESSP
}, /* mov.b r0,@(disp,gbr) */
1908 { 0xc100, STORE
| USESR0
| USESSP
}, /* mov.w r0,@(disp,gbr) */
1909 { 0xc200, STORE
| USESR0
| USESSP
}, /* mov.l r0,@(disp,gbr) */
1910 { 0xc300, BRANCH
| USESSP
}, /* trapa #imm */
1911 { 0xc400, LOAD
| SETSR0
| USESSP
}, /* mov.b @(disp,gbr),r0 */
1912 { 0xc500, LOAD
| SETSR0
| USESSP
}, /* mov.w @(disp,gbr),r0 */
1913 { 0xc600, LOAD
| SETSR0
| USESSP
}, /* mov.l @(disp,gbr),r0 */
1914 { 0xc700, SETSR0
}, /* mova @(disp,pc),r0 */
1915 { 0xc800, SETSSP
| USESR0
}, /* tst #imm,r0 */
1916 { 0xc900, SETSR0
| USESR0
}, /* and #imm,r0 */
1917 { 0xca00, SETSR0
| USESR0
}, /* xor #imm,r0 */
1918 { 0xcb00, SETSR0
| USESR0
}, /* or #imm,r0 */
1919 { 0xcc00, LOAD
| SETSSP
| USESR0
| USESSP
}, /* tst.b #imm,@(r0,gbr) */
1920 { 0xcd00, LOAD
| STORE
| USESR0
| USESSP
}, /* and.b #imm,@(r0,gbr) */
1921 { 0xce00, LOAD
| STORE
| USESR0
| USESSP
}, /* xor.b #imm,@(r0,gbr) */
1922 { 0xcf00, LOAD
| STORE
| USESR0
| USESSP
} /* or.b #imm,@(r0,gbr) */
1925 static const struct sh_minor_opcode sh_opcodec
[] =
1927 { MAP (sh_opcodec0
), 0xff00 }
1930 static const struct sh_opcode sh_opcoded0
[] =
1932 { 0xd000, LOAD
| SETS1
} /* mov.l @(disp,pc),rn */
1935 static const struct sh_minor_opcode sh_opcoded
[] =
1937 { MAP (sh_opcoded0
), 0xf000 }
1940 static const struct sh_opcode sh_opcodee0
[] =
1942 { 0xe000, SETS1
} /* mov #imm,rn */
1945 static const struct sh_minor_opcode sh_opcodee
[] =
1947 { MAP (sh_opcodee0
), 0xf000 }
1950 static const struct sh_opcode sh_opcodef0
[] =
1952 { 0xf000, SETSF1
| USESF1
| USESF2
}, /* fadd fm,fn */
1953 { 0xf001, SETSF1
| USESF1
| USESF2
}, /* fsub fm,fn */
1954 { 0xf002, SETSF1
| USESF1
| USESF2
}, /* fmul fm,fn */
1955 { 0xf003, SETSF1
| USESF1
| USESF2
}, /* fdiv fm,fn */
1956 { 0xf004, SETSSP
| USESF1
| USESF2
}, /* fcmp/eq fm,fn */
1957 { 0xf005, SETSSP
| USESF1
| USESF2
}, /* fcmp/gt fm,fn */
1958 { 0xf006, LOAD
| SETSF1
| USES2
| USESR0
}, /* fmov.s @(r0,rm),fn */
1959 { 0xf007, STORE
| USES1
| USESF2
| USESR0
}, /* fmov.s fm,@(r0,rn) */
1960 { 0xf008, LOAD
| SETSF1
| USES2
}, /* fmov.s @rm,fn */
1961 { 0xf009, LOAD
| SETS2
| SETSF1
| USES2
}, /* fmov.s @rm+,fn */
1962 { 0xf00a, STORE
| USES1
| USESF2
}, /* fmov.s fm,@rn */
1963 { 0xf00b, STORE
| SETS1
| USES1
| USESF2
}, /* fmov.s fm,@-rn */
1964 { 0xf00c, SETSF1
| USESF2
}, /* fmov fm,fn */
1965 { 0xf00e, SETSF1
| USESF1
| USESF2
| USESF0
} /* fmac f0,fm,fn */
1968 static const struct sh_opcode sh_opcodef1
[] =
1970 { 0xf00d, SETSF1
| USESSP
}, /* fsts fpul,fn */
1971 { 0xf01d, SETSSP
| USESF1
}, /* flds fn,fpul */
1972 { 0xf02d, SETSF1
| USESSP
}, /* float fpul,fn */
1973 { 0xf03d, SETSSP
| USESF1
}, /* ftrc fn,fpul */
1974 { 0xf04d, SETSF1
| USESF1
}, /* fneg fn */
1975 { 0xf05d, SETSF1
| USESF1
}, /* fabs fn */
1976 { 0xf06d, SETSF1
| USESF1
}, /* fsqrt fn */
1977 { 0xf07d, SETSSP
| USESF1
}, /* ftst/nan fn */
1978 { 0xf08d, SETSF1
}, /* fldi0 fn */
1979 { 0xf09d, SETSF1
} /* fldi1 fn */
1982 static const struct sh_minor_opcode sh_opcodef
[] =
1984 { MAP (sh_opcodef0
), 0xf00f },
1985 { MAP (sh_opcodef1
), 0xf0ff }
1988 static struct sh_major_opcode sh_opcodes
[] =
1990 { MAP (sh_opcode0
) },
1991 { MAP (sh_opcode1
) },
1992 { MAP (sh_opcode2
) },
1993 { MAP (sh_opcode3
) },
1994 { MAP (sh_opcode4
) },
1995 { MAP (sh_opcode5
) },
1996 { MAP (sh_opcode6
) },
1997 { MAP (sh_opcode7
) },
1998 { MAP (sh_opcode8
) },
1999 { MAP (sh_opcode9
) },
2000 { MAP (sh_opcodea
) },
2001 { MAP (sh_opcodeb
) },
2002 { MAP (sh_opcodec
) },
2003 { MAP (sh_opcoded
) },
2004 { MAP (sh_opcodee
) },
2005 { MAP (sh_opcodef
) }
2008 /* The double data transfer / parallel processing insns are not
2009 described here. This will cause sh_align_load_span to leave them alone. */
2011 static const struct sh_opcode sh_dsp_opcodef0
[] =
2013 { 0xf400, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @-as,ds */
2014 { 0xf401, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@-as */
2015 { 0xf404, USESAS
| LOAD
| SETSSP
}, /* movs.x @as,ds */
2016 { 0xf405, USESAS
| STORE
| USESSP
}, /* movs.x ds,@as */
2017 { 0xf408, USESAS
| SETSAS
| LOAD
| SETSSP
}, /* movs.x @as+,ds */
2018 { 0xf409, USESAS
| SETSAS
| STORE
| USESSP
}, /* movs.x ds,@as+ */
2019 { 0xf40c, USESAS
| SETSAS
| LOAD
| SETSSP
| USESR8
}, /* movs.x @as+r8,ds */
2020 { 0xf40d, USESAS
| SETSAS
| STORE
| USESSP
| USESR8
} /* movs.x ds,@as+r8 */
2023 static const struct sh_minor_opcode sh_dsp_opcodef
[] =
2025 { MAP (sh_dsp_opcodef0
), 0xfc0d }
2028 /* Given an instruction, return a pointer to the corresponding
2029 sh_opcode structure. Return NULL if the instruction is not
2032 static const struct sh_opcode
*
2033 sh_insn_info (unsigned int insn
)
2035 const struct sh_major_opcode
*maj
;
2036 const struct sh_minor_opcode
*min
, *minend
;
2038 maj
= &sh_opcodes
[(insn
& 0xf000) >> 12];
2039 min
= maj
->minor_opcodes
;
2040 minend
= min
+ maj
->count
;
2041 for (; min
< minend
; min
++)
2044 const struct sh_opcode
*op
, *opend
;
2046 l
= insn
& min
->mask
;
2048 opend
= op
+ min
->count
;
2050 /* Since the opcodes tables are sorted, we could use a binary
2051 search here if the count were above some cutoff value. */
2052 for (; op
< opend
; op
++)
2053 if (op
->opcode
== l
)
2060 /* See whether an instruction uses a general purpose register. */
2063 sh_insn_uses_reg (unsigned int insn
,
2064 const struct sh_opcode
*op
,
2071 if ((f
& USES1
) != 0
2072 && USES1_REG (insn
) == reg
)
2074 if ((f
& USES2
) != 0
2075 && USES2_REG (insn
) == reg
)
2077 if ((f
& USESR0
) != 0
2080 if ((f
& USESAS
) && reg
== USESAS_REG (insn
))
2082 if ((f
& USESR8
) && reg
== 8)
2088 /* See whether an instruction sets a general purpose register. */
2091 sh_insn_sets_reg (unsigned int insn
,
2092 const struct sh_opcode
*op
,
2099 if ((f
& SETS1
) != 0
2100 && SETS1_REG (insn
) == reg
)
2102 if ((f
& SETS2
) != 0
2103 && SETS2_REG (insn
) == reg
)
2105 if ((f
& SETSR0
) != 0
2108 if ((f
& SETSAS
) && reg
== SETSAS_REG (insn
))
2114 /* See whether an instruction uses or sets a general purpose register */
2117 sh_insn_uses_or_sets_reg (unsigned int insn
,
2118 const struct sh_opcode
*op
,
2121 if (sh_insn_uses_reg (insn
, op
, reg
))
2124 return sh_insn_sets_reg (insn
, op
, reg
);
2127 /* See whether an instruction uses a floating point register. */
2130 sh_insn_uses_freg (unsigned int insn
,
2131 const struct sh_opcode
*op
,
2138 /* We can't tell if this is a double-precision insn, so just play safe
2139 and assume that it might be. So not only have we test FREG against
2140 itself, but also even FREG against FREG+1 - if the using insn uses
2141 just the low part of a double precision value - but also an odd
2142 FREG against FREG-1 - if the setting insn sets just the low part
2143 of a double precision value.
2144 So what this all boils down to is that we have to ignore the lowest
2145 bit of the register number. */
2147 if ((f
& USESF1
) != 0
2148 && (USESF1_REG (insn
) & 0xe) == (freg
& 0xe))
2150 if ((f
& USESF2
) != 0
2151 && (USESF2_REG (insn
) & 0xe) == (freg
& 0xe))
2153 if ((f
& USESF0
) != 0
2160 /* See whether an instruction sets a floating point register. */
2163 sh_insn_sets_freg (unsigned int insn
,
2164 const struct sh_opcode
*op
,
2171 /* We can't tell if this is a double-precision insn, so just play safe
2172 and assume that it might be. So not only have we test FREG against
2173 itself, but also even FREG against FREG+1 - if the using insn uses
2174 just the low part of a double precision value - but also an odd
2175 FREG against FREG-1 - if the setting insn sets just the low part
2176 of a double precision value.
2177 So what this all boils down to is that we have to ignore the lowest
2178 bit of the register number. */
2180 if ((f
& SETSF1
) != 0
2181 && (SETSF1_REG (insn
) & 0xe) == (freg
& 0xe))
2187 /* See whether an instruction uses or sets a floating point register */
2190 sh_insn_uses_or_sets_freg (unsigned int insn
,
2191 const struct sh_opcode
*op
,
2194 if (sh_insn_uses_freg (insn
, op
, reg
))
2197 return sh_insn_sets_freg (insn
, op
, reg
);
2200 /* See whether instructions I1 and I2 conflict, assuming I1 comes
2201 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2202 This should return TRUE if there is a conflict, or FALSE if the
2203 instructions can be swapped safely. */
2206 sh_insns_conflict (unsigned int i1
,
2207 const struct sh_opcode
*op1
,
2209 const struct sh_opcode
*op2
)
2211 unsigned int f1
, f2
;
2216 /* Load of fpscr conflicts with floating point operations.
2217 FIXME: shouldn't test raw opcodes here. */
2218 if (((i1
& 0xf0ff) == 0x4066 && (i2
& 0xf000) == 0xf000)
2219 || ((i2
& 0xf0ff) == 0x4066 && (i1
& 0xf000) == 0xf000))
2222 if ((f1
& (BRANCH
| DELAY
)) != 0
2223 || (f2
& (BRANCH
| DELAY
)) != 0)
2226 if (((f1
| f2
) & SETSSP
)
2227 && (f1
& (SETSSP
| USESSP
))
2228 && (f2
& (SETSSP
| USESSP
)))
2231 if ((f1
& SETS1
) != 0
2232 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS1_REG (i1
)))
2234 if ((f1
& SETS2
) != 0
2235 && sh_insn_uses_or_sets_reg (i2
, op2
, SETS2_REG (i1
)))
2237 if ((f1
& SETSR0
) != 0
2238 && sh_insn_uses_or_sets_reg (i2
, op2
, 0))
2241 && sh_insn_uses_or_sets_reg (i2
, op2
, SETSAS_REG (i1
)))
2243 if ((f1
& SETSF1
) != 0
2244 && sh_insn_uses_or_sets_freg (i2
, op2
, SETSF1_REG (i1
)))
2247 if ((f2
& SETS1
) != 0
2248 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS1_REG (i2
)))
2250 if ((f2
& SETS2
) != 0
2251 && sh_insn_uses_or_sets_reg (i1
, op1
, SETS2_REG (i2
)))
2253 if ((f2
& SETSR0
) != 0
2254 && sh_insn_uses_or_sets_reg (i1
, op1
, 0))
2257 && sh_insn_uses_or_sets_reg (i1
, op1
, SETSAS_REG (i2
)))
2259 if ((f2
& SETSF1
) != 0
2260 && sh_insn_uses_or_sets_freg (i1
, op1
, SETSF1_REG (i2
)))
2263 /* The instructions do not conflict. */
2267 /* I1 is a load instruction, and I2 is some other instruction. Return
2268 TRUE if I1 loads a register which I2 uses. */
2271 sh_load_use (unsigned int i1
,
2272 const struct sh_opcode
*op1
,
2274 const struct sh_opcode
*op2
)
2280 if ((f1
& LOAD
) == 0)
2283 /* If both SETS1 and SETSSP are set, that means a load to a special
2284 register using postincrement addressing mode, which we don't care
2286 if ((f1
& SETS1
) != 0
2287 && (f1
& SETSSP
) == 0
2288 && sh_insn_uses_reg (i2
, op2
, (i1
& 0x0f00) >> 8))
2291 if ((f1
& SETSR0
) != 0
2292 && sh_insn_uses_reg (i2
, op2
, 0))
2295 if ((f1
& SETSF1
) != 0
2296 && sh_insn_uses_freg (i2
, op2
, (i1
& 0x0f00) >> 8))
2302 /* Try to align loads and stores within a span of memory. This is
2303 called by both the ELF and the COFF sh targets. ABFD and SEC are
2304 the BFD and section we are examining. CONTENTS is the contents of
2305 the section. SWAP is the routine to call to swap two instructions.
2306 RELOCS is a pointer to the internal relocation information, to be
2307 passed to SWAP. PLABEL is a pointer to the current label in a
2308 sorted list of labels; LABEL_END is the end of the list. START and
2309 STOP are the range of memory to examine. If a swap is made,
2310 *PSWAPPED is set to TRUE. */
2316 _bfd_sh_align_load_span (bfd
*abfd
,
2319 bfd_boolean (*swap
) (bfd
*, asection
*, void *, bfd_byte
*, bfd_vma
),
2325 bfd_boolean
*pswapped
)
2327 int dsp
= (abfd
->arch_info
->mach
== bfd_mach_sh_dsp
2328 || abfd
->arch_info
->mach
== bfd_mach_sh3_dsp
);
2331 /* The SH4 has a Harvard architecture, hence aligning loads is not
2332 desirable. In fact, it is counter-productive, since it interferes
2333 with the schedules generated by the compiler. */
2334 if (abfd
->arch_info
->mach
== bfd_mach_sh4
)
2337 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2341 sh_opcodes
[0xf].minor_opcodes
= sh_dsp_opcodef
;
2342 sh_opcodes
[0xf].count
= sizeof sh_dsp_opcodef
/ sizeof sh_dsp_opcodef
[0];
2345 /* Instructions should be aligned on 2 byte boundaries. */
2346 if ((start
& 1) == 1)
2349 /* Now look through the unaligned addresses. */
2353 for (; i
< stop
; i
+= 4)
2356 const struct sh_opcode
*op
;
2357 unsigned int prev_insn
= 0;
2358 const struct sh_opcode
*prev_op
= NULL
;
2360 insn
= bfd_get_16 (abfd
, contents
+ i
);
2361 op
= sh_insn_info (insn
);
2363 || (op
->flags
& (LOAD
| STORE
)) == 0)
2366 /* This is a load or store which is not on a four byte boundary. */
2368 while (*plabel
< label_end
&& **plabel
< i
)
2373 prev_insn
= bfd_get_16 (abfd
, contents
+ i
- 2);
2374 /* If INSN is the field b of a parallel processing insn, it is not
2375 a load / store after all. Note that the test here might mistake
2376 the field_b of a pcopy insn for the starting code of a parallel
2377 processing insn; this might miss a swapping opportunity, but at
2378 least we're on the safe side. */
2379 if (dsp
&& (prev_insn
& 0xfc00) == 0xf800)
2382 /* Check if prev_insn is actually the field b of a parallel
2383 processing insn. Again, this can give a spurious match
2385 if (dsp
&& i
- 2 > start
)
2387 unsigned pprev_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2389 if ((pprev_insn
& 0xfc00) == 0xf800)
2392 prev_op
= sh_insn_info (prev_insn
);
2395 prev_op
= sh_insn_info (prev_insn
);
2397 /* If the load/store instruction is in a delay slot, we
2400 || (prev_op
->flags
& DELAY
) != 0)
2404 && (*plabel
>= label_end
|| **plabel
!= i
)
2406 && (prev_op
->flags
& (LOAD
| STORE
)) == 0
2407 && ! sh_insns_conflict (prev_insn
, prev_op
, insn
, op
))
2411 /* The load/store instruction does not have a label, and
2412 there is a previous instruction; PREV_INSN is not
2413 itself a load/store instruction, and PREV_INSN and
2414 INSN do not conflict. */
2420 unsigned int prev2_insn
;
2421 const struct sh_opcode
*prev2_op
;
2423 prev2_insn
= bfd_get_16 (abfd
, contents
+ i
- 4);
2424 prev2_op
= sh_insn_info (prev2_insn
);
2426 /* If the instruction before PREV_INSN has a delay
2427 slot--that is, PREV_INSN is in a delay slot--we
2429 if (prev2_op
== NULL
2430 || (prev2_op
->flags
& DELAY
) != 0)
2433 /* If the instruction before PREV_INSN is a load,
2434 and it sets a register which INSN uses, then
2435 putting INSN immediately after PREV_INSN will
2436 cause a pipeline bubble, so there is no point to
2439 && (prev2_op
->flags
& LOAD
) != 0
2440 && sh_load_use (prev2_insn
, prev2_op
, insn
, op
))
2446 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
- 2))
2453 while (*plabel
< label_end
&& **plabel
< i
+ 2)
2457 && (*plabel
>= label_end
|| **plabel
!= i
+ 2))
2459 unsigned int next_insn
;
2460 const struct sh_opcode
*next_op
;
2462 /* There is an instruction after the load/store
2463 instruction, and it does not have a label. */
2464 next_insn
= bfd_get_16 (abfd
, contents
+ i
+ 2);
2465 next_op
= sh_insn_info (next_insn
);
2467 && (next_op
->flags
& (LOAD
| STORE
)) == 0
2468 && ! sh_insns_conflict (insn
, op
, next_insn
, next_op
))
2472 /* NEXT_INSN is not itself a load/store instruction,
2473 and it does not conflict with INSN. */
2477 /* If PREV_INSN is a load, and it sets a register
2478 which NEXT_INSN uses, then putting NEXT_INSN
2479 immediately after PREV_INSN will cause a pipeline
2480 bubble, so there is no reason to make this swap. */
2482 && (prev_op
->flags
& LOAD
) != 0
2483 && sh_load_use (prev_insn
, prev_op
, next_insn
, next_op
))
2486 /* If INSN is a load, and it sets a register which
2487 the insn after NEXT_INSN uses, then doing the
2488 swap will cause a pipeline bubble, so there is no
2489 reason to make the swap. However, if the insn
2490 after NEXT_INSN is itself a load or store
2491 instruction, then it is misaligned, so
2492 optimistically hope that it will be swapped
2493 itself, and just live with the pipeline bubble if
2497 && (op
->flags
& LOAD
) != 0)
2499 unsigned int next2_insn
;
2500 const struct sh_opcode
*next2_op
;
2502 next2_insn
= bfd_get_16 (abfd
, contents
+ i
+ 4);
2503 next2_op
= sh_insn_info (next2_insn
);
2504 if (next2_op
== NULL
2505 || ((next2_op
->flags
& (LOAD
| STORE
)) == 0
2506 && sh_load_use (insn
, op
, next2_insn
, next2_op
)))
2512 if (! (*swap
) (abfd
, sec
, relocs
, contents
, i
))
2523 #endif /* not COFF_IMAGE_WITH_PE */
2525 /* Swap two SH instructions. */
2528 sh_swap_insns (bfd
* abfd
,
2531 bfd_byte
* contents
,
2534 struct internal_reloc
*internal_relocs
= (struct internal_reloc
*) relocs
;
2535 unsigned short i1
, i2
;
2536 struct internal_reloc
*irel
, *irelend
;
2538 /* Swap the instructions themselves. */
2539 i1
= bfd_get_16 (abfd
, contents
+ addr
);
2540 i2
= bfd_get_16 (abfd
, contents
+ addr
+ 2);
2541 bfd_put_16 (abfd
, (bfd_vma
) i2
, contents
+ addr
);
2542 bfd_put_16 (abfd
, (bfd_vma
) i1
, contents
+ addr
+ 2);
2544 /* Adjust all reloc addresses. */
2545 irelend
= internal_relocs
+ sec
->reloc_count
;
2546 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2550 /* There are a few special types of relocs that we don't want to
2551 adjust. These relocs do not apply to the instruction itself,
2552 but are only associated with the address. */
2553 type
= irel
->r_type
;
2554 if (type
== R_SH_ALIGN
2555 || type
== R_SH_CODE
2556 || type
== R_SH_DATA
2557 || type
== R_SH_LABEL
)
2560 /* If an R_SH_USES reloc points to one of the addresses being
2561 swapped, we must adjust it. It would be incorrect to do this
2562 for a jump, though, since we want to execute both
2563 instructions after the jump. (We have avoided swapping
2564 around a label, so the jump will not wind up executing an
2565 instruction it shouldn't). */
2566 if (type
== R_SH_USES
)
2570 off
= irel
->r_vaddr
- sec
->vma
+ 4 + irel
->r_offset
;
2572 irel
->r_offset
+= 2;
2573 else if (off
== addr
+ 2)
2574 irel
->r_offset
-= 2;
2577 if (irel
->r_vaddr
- sec
->vma
== addr
)
2582 else if (irel
->r_vaddr
- sec
->vma
== addr
+ 2)
2593 unsigned short insn
, oinsn
;
2594 bfd_boolean overflow
;
2596 loc
= contents
+ irel
->r_vaddr
- sec
->vma
;
2603 case R_SH_PCDISP8BY2
:
2604 case R_SH_PCRELIMM8BY2
:
2605 insn
= bfd_get_16 (abfd
, loc
);
2608 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2610 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2614 insn
= bfd_get_16 (abfd
, loc
);
2617 if ((oinsn
& 0xf000) != (insn
& 0xf000))
2619 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2622 case R_SH_PCRELIMM8BY4
:
2623 /* This reloc ignores the least significant 3 bits of
2624 the program counter before adding in the offset.
2625 This means that if ADDR is at an even address, the
2626 swap will not affect the offset. If ADDR is an at an
2627 odd address, then the instruction will be crossing a
2628 four byte boundary, and must be adjusted. */
2629 if ((addr
& 3) != 0)
2631 insn
= bfd_get_16 (abfd
, loc
);
2634 if ((oinsn
& 0xff00) != (insn
& 0xff00))
2636 bfd_put_16 (abfd
, (bfd_vma
) insn
, loc
);
2645 /* xgettext: c-format */
2646 (_("%pB: %#" PRIx64
": fatal: reloc overflow while relaxing"),
2647 abfd
, (uint64_t) irel
->r_vaddr
);
2648 bfd_set_error (bfd_error_bad_value
);
2657 /* Look for loads and stores which we can align to four byte
2658 boundaries. See the longer comment above sh_relax_section for why
2659 this is desirable. This sets *PSWAPPED if some instruction was
2663 sh_align_loads (bfd
*abfd
,
2665 struct internal_reloc
*internal_relocs
,
2667 bfd_boolean
*pswapped
)
2669 struct internal_reloc
*irel
, *irelend
;
2670 bfd_vma
*labels
= NULL
;
2671 bfd_vma
*label
, *label_end
;
2676 irelend
= internal_relocs
+ sec
->reloc_count
;
2678 /* Get all the addresses with labels on them. */
2679 amt
= (bfd_size_type
) sec
->reloc_count
* sizeof (bfd_vma
);
2680 labels
= (bfd_vma
*) bfd_malloc (amt
);
2684 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2686 if (irel
->r_type
== R_SH_LABEL
)
2688 *label_end
= irel
->r_vaddr
- sec
->vma
;
2693 /* Note that the assembler currently always outputs relocs in
2694 address order. If that ever changes, this code will need to sort
2695 the label values and the relocs. */
2699 for (irel
= internal_relocs
; irel
< irelend
; irel
++)
2701 bfd_vma start
, stop
;
2703 if (irel
->r_type
!= R_SH_CODE
)
2706 start
= irel
->r_vaddr
- sec
->vma
;
2708 for (irel
++; irel
< irelend
; irel
++)
2709 if (irel
->r_type
== R_SH_DATA
)
2712 stop
= irel
->r_vaddr
- sec
->vma
;
2716 if (! _bfd_sh_align_load_span (abfd
, sec
, contents
, sh_swap_insns
,
2717 internal_relocs
, &label
,
2718 label_end
, start
, stop
, pswapped
))
2732 /* This is a modification of _bfd_coff_generic_relocate_section, which
2733 will handle SH relaxing. */
2736 sh_relocate_section (bfd
*output_bfd ATTRIBUTE_UNUSED
,
2737 struct bfd_link_info
*info
,
2739 asection
*input_section
,
2741 struct internal_reloc
*relocs
,
2742 struct internal_syment
*syms
,
2743 asection
**sections
)
2745 struct internal_reloc
*rel
;
2746 struct internal_reloc
*relend
;
2749 relend
= rel
+ input_section
->reloc_count
;
2750 for (; rel
< relend
; rel
++)
2753 struct coff_link_hash_entry
*h
;
2754 struct internal_syment
*sym
;
2757 reloc_howto_type
*howto
;
2758 bfd_reloc_status_type rstat
;
2760 /* Almost all relocs have to do with relaxing. If any work must
2761 be done for them, it has been done in sh_relax_section. */
2762 if (rel
->r_type
!= R_SH_IMM32
2764 && rel
->r_type
!= R_SH_IMM32CE
2765 && rel
->r_type
!= R_SH_IMAGEBASE
2767 && rel
->r_type
!= R_SH_PCDISP
)
2770 symndx
= rel
->r_symndx
;
2780 || (unsigned long) symndx
>= obj_raw_syment_count (input_bfd
))
2783 /* xgettext: c-format */
2784 (_("%pB: illegal symbol index %ld in relocs"),
2786 bfd_set_error (bfd_error_bad_value
);
2789 h
= obj_coff_sym_hashes (input_bfd
)[symndx
];
2790 sym
= syms
+ symndx
;
2793 if (sym
!= NULL
&& sym
->n_scnum
!= 0)
2794 addend
= - sym
->n_value
;
2798 if (rel
->r_type
== R_SH_PCDISP
)
2801 if (rel
->r_type
>= SH_COFF_HOWTO_COUNT
)
2804 howto
= &sh_coff_howtos
[rel
->r_type
];
2808 bfd_set_error (bfd_error_bad_value
);
2813 if (rel
->r_type
== R_SH_IMAGEBASE
)
2814 addend
-= pe_data (input_section
->output_section
->owner
)->pe_opthdr
.ImageBase
;
2823 /* There is nothing to do for an internal PCDISP reloc. */
2824 if (rel
->r_type
== R_SH_PCDISP
)
2829 sec
= bfd_abs_section_ptr
;
2834 sec
= sections
[symndx
];
2835 val
= (sec
->output_section
->vma
2836 + sec
->output_offset
2843 if (h
->root
.type
== bfd_link_hash_defined
2844 || h
->root
.type
== bfd_link_hash_defweak
)
2848 sec
= h
->root
.u
.def
.section
;
2849 val
= (h
->root
.u
.def
.value
2850 + sec
->output_section
->vma
2851 + sec
->output_offset
);
2853 else if (! bfd_link_relocatable (info
))
2854 (*info
->callbacks
->undefined_symbol
)
2855 (info
, h
->root
.root
.string
, input_bfd
, input_section
,
2856 rel
->r_vaddr
- input_section
->vma
, TRUE
);
2859 rstat
= _bfd_final_link_relocate (howto
, input_bfd
, input_section
,
2861 rel
->r_vaddr
- input_section
->vma
,
2870 case bfd_reloc_overflow
:
2873 char buf
[SYMNMLEN
+ 1];
2879 else if (sym
->_n
._n_n
._n_zeroes
== 0
2880 && sym
->_n
._n_n
._n_offset
!= 0)
2881 name
= obj_coff_strings (input_bfd
) + sym
->_n
._n_n
._n_offset
;
2884 strncpy (buf
, sym
->_n
._n_name
, SYMNMLEN
);
2885 buf
[SYMNMLEN
] = '\0';
2889 (*info
->callbacks
->reloc_overflow
)
2890 (info
, (h
? &h
->root
: NULL
), name
, howto
->name
,
2891 (bfd_vma
) 0, input_bfd
, input_section
,
2892 rel
->r_vaddr
- input_section
->vma
);
2900 /* This is a version of bfd_generic_get_relocated_section_contents
2901 which uses sh_relocate_section. */
2904 sh_coff_get_relocated_section_contents (bfd
*output_bfd
,
2905 struct bfd_link_info
*link_info
,
2906 struct bfd_link_order
*link_order
,
2908 bfd_boolean relocatable
,
2911 asection
*input_section
= link_order
->u
.indirect
.section
;
2912 bfd
*input_bfd
= input_section
->owner
;
2913 asection
**sections
= NULL
;
2914 struct internal_reloc
*internal_relocs
= NULL
;
2915 struct internal_syment
*internal_syms
= NULL
;
2917 /* We only need to handle the case of relaxing, or of having a
2918 particular set of section contents, specially. */
2920 || coff_section_data (input_bfd
, input_section
) == NULL
2921 || coff_section_data (input_bfd
, input_section
)->contents
== NULL
)
2922 return bfd_generic_get_relocated_section_contents (output_bfd
, link_info
,
2927 memcpy (data
, coff_section_data (input_bfd
, input_section
)->contents
,
2928 (size_t) input_section
->size
);
2930 if ((input_section
->flags
& SEC_RELOC
) != 0
2931 && input_section
->reloc_count
> 0)
2933 bfd_size_type symesz
= bfd_coff_symesz (input_bfd
);
2934 bfd_byte
*esym
, *esymend
;
2935 struct internal_syment
*isymp
;
2939 if (! _bfd_coff_get_external_symbols (input_bfd
))
2942 internal_relocs
= (_bfd_coff_read_internal_relocs
2943 (input_bfd
, input_section
, FALSE
, (bfd_byte
*) NULL
,
2944 FALSE
, (struct internal_reloc
*) NULL
));
2945 if (internal_relocs
== NULL
)
2948 amt
= obj_raw_syment_count (input_bfd
);
2949 amt
*= sizeof (struct internal_syment
);
2950 internal_syms
= (struct internal_syment
*) bfd_malloc (amt
);
2951 if (internal_syms
== NULL
)
2954 amt
= obj_raw_syment_count (input_bfd
);
2955 amt
*= sizeof (asection
*);
2956 sections
= (asection
**) bfd_malloc (amt
);
2957 if (sections
== NULL
)
2960 isymp
= internal_syms
;
2962 esym
= (bfd_byte
*) obj_coff_external_syms (input_bfd
);
2963 esymend
= esym
+ obj_raw_syment_count (input_bfd
) * symesz
;
2964 while (esym
< esymend
)
2966 bfd_coff_swap_sym_in (input_bfd
, esym
, isymp
);
2968 if (isymp
->n_scnum
!= 0)
2969 *secpp
= coff_section_from_bfd_index (input_bfd
, isymp
->n_scnum
);
2972 if (isymp
->n_value
== 0)
2973 *secpp
= bfd_und_section_ptr
;
2975 *secpp
= bfd_com_section_ptr
;
2978 esym
+= (isymp
->n_numaux
+ 1) * symesz
;
2979 secpp
+= isymp
->n_numaux
+ 1;
2980 isymp
+= isymp
->n_numaux
+ 1;
2983 if (! sh_relocate_section (output_bfd
, link_info
, input_bfd
,
2984 input_section
, data
, internal_relocs
,
2985 internal_syms
, sections
))
2990 free (internal_syms
);
2991 internal_syms
= NULL
;
2992 free (internal_relocs
);
2993 internal_relocs
= NULL
;
2999 if (internal_relocs
!= NULL
)
3000 free (internal_relocs
);
3001 if (internal_syms
!= NULL
)
3002 free (internal_syms
);
3003 if (sections
!= NULL
)
3008 /* The target vectors. */
3010 #ifndef TARGET_SHL_SYM
3011 CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec
, "coff-sh", BFD_IS_RELAXABLE
, 0, '_', NULL
, COFF_SWAP_TABLE
)
3014 #ifdef TARGET_SHL_SYM
3015 #define TARGET_SYM TARGET_SHL_SYM
3017 #define TARGET_SYM sh_coff_le_vec
3020 #ifndef TARGET_SHL_NAME
3021 #define TARGET_SHL_NAME "coff-shl"
3025 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3026 SEC_CODE
| SEC_DATA
, '_', NULL
, COFF_SWAP_TABLE
);
3028 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM
, TARGET_SHL_NAME
, BFD_IS_RELAXABLE
,
3029 0, '_', NULL
, COFF_SWAP_TABLE
)
3032 #ifndef TARGET_SHL_SYM
3034 /* Some people want versions of the SH COFF target which do not align
3035 to 16 byte boundaries. We implement that by adding a couple of new
3036 target vectors. These are just like the ones above, but they
3037 change the default section alignment. To generate them in the
3038 assembler, use -small. To use them in the linker, use -b
3039 coff-sh{l}-small and -oformat coff-sh{l}-small.
3041 Yes, this is a horrible hack. A general solution for setting
3042 section alignment in COFF is rather complex. ELF handles this
3045 /* Only recognize the small versions if the target was not defaulted.
3046 Otherwise we won't recognize the non default endianness. */
3048 static const bfd_target
*
3049 coff_small_object_p (bfd
*abfd
)
3051 if (abfd
->target_defaulted
)
3053 bfd_set_error (bfd_error_wrong_format
);
3056 return coff_object_p (abfd
);
3059 /* Set the section alignment for the small versions. */
3062 coff_small_new_section_hook (bfd
*abfd
, asection
*section
)
3064 if (! coff_new_section_hook (abfd
, section
))
3067 /* We must align to at least a four byte boundary, because longword
3068 accesses must be on a four byte boundary. */
3069 if (section
->alignment_power
== COFF_DEFAULT_SECTION_ALIGNMENT_POWER
)
3070 section
->alignment_power
= 2;
3075 /* This is copied from bfd_coff_std_swap_table so that we can change
3076 the default section alignment power. */
3078 static bfd_coff_backend_data bfd_coff_small_swap_table
=
3080 coff_swap_aux_in
, coff_swap_sym_in
, coff_swap_lineno_in
,
3081 coff_swap_aux_out
, coff_swap_sym_out
,
3082 coff_swap_lineno_out
, coff_swap_reloc_out
,
3083 coff_swap_filehdr_out
, coff_swap_aouthdr_out
,
3084 coff_swap_scnhdr_out
,
3085 FILHSZ
, AOUTSZ
, SCNHSZ
, SYMESZ
, AUXESZ
, RELSZ
, LINESZ
, FILNMLEN
,
3086 #ifdef COFF_LONG_FILENAMES
3091 COFF_DEFAULT_LONG_SECTION_NAMES
,
3093 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3098 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3104 coff_swap_filehdr_in
, coff_swap_aouthdr_in
, coff_swap_scnhdr_in
,
3105 coff_swap_reloc_in
, coff_bad_format_hook
, coff_set_arch_mach_hook
,
3106 coff_mkobject_hook
, styp_to_sec_flags
, coff_set_alignment_hook
,
3107 coff_slurp_symbol_table
, symname_in_debug_hook
, coff_pointerize_aux_hook
,
3108 coff_print_aux
, coff_reloc16_extra_cases
, coff_reloc16_estimate
,
3109 coff_classify_symbol
, coff_compute_section_file_positions
,
3110 coff_start_final_link
, coff_relocate_section
, coff_rtype_to_howto
,
3111 coff_adjust_symndx
, coff_link_add_one_symbol
,
3112 coff_link_output_has_begun
, coff_final_link_postscript
,
3116 #define coff_small_close_and_cleanup \
3117 coff_close_and_cleanup
3118 #define coff_small_bfd_free_cached_info \
3119 coff_bfd_free_cached_info
3120 #define coff_small_get_section_contents \
3121 coff_get_section_contents
3122 #define coff_small_get_section_contents_in_window \
3123 coff_get_section_contents_in_window
3125 extern const bfd_target sh_coff_small_le_vec
;
3127 const bfd_target sh_coff_small_vec
=
3129 "coff-sh-small", /* name */
3130 bfd_target_coff_flavour
,
3131 BFD_ENDIAN_BIG
, /* data byte order is big */
3132 BFD_ENDIAN_BIG
, /* header byte order is big */
3134 (HAS_RELOC
| EXEC_P
/* object flags */
3135 | HAS_LINENO
| HAS_DEBUG
3136 | HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3138 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3139 '_', /* leading symbol underscore */
3140 '/', /* ar_pad_char */
3141 15, /* ar_max_namelen */
3142 0, /* match priority. */
3143 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3144 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3145 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* data */
3146 bfd_getb64
, bfd_getb_signed_64
, bfd_putb64
,
3147 bfd_getb32
, bfd_getb_signed_32
, bfd_putb32
,
3148 bfd_getb16
, bfd_getb_signed_16
, bfd_putb16
, /* hdrs */
3150 { /* bfd_check_format */
3152 coff_small_object_p
,
3153 bfd_generic_archive_p
,
3156 { /* bfd_set_format */
3157 _bfd_bool_bfd_false_error
,
3159 _bfd_generic_mkarchive
,
3160 _bfd_bool_bfd_false_error
3162 { /* bfd_write_contents */
3163 _bfd_bool_bfd_false_error
,
3164 coff_write_object_contents
,
3165 _bfd_write_archive_contents
,
3166 _bfd_bool_bfd_false_error
3169 BFD_JUMP_TABLE_GENERIC (coff_small
),
3170 BFD_JUMP_TABLE_COPY (coff
),
3171 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3172 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3173 BFD_JUMP_TABLE_SYMBOLS (coff
),
3174 BFD_JUMP_TABLE_RELOCS (coff
),
3175 BFD_JUMP_TABLE_WRITE (coff
),
3176 BFD_JUMP_TABLE_LINK (coff
),
3177 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3179 &sh_coff_small_le_vec
,
3181 &bfd_coff_small_swap_table
3184 const bfd_target sh_coff_small_le_vec
=
3186 "coff-shl-small", /* name */
3187 bfd_target_coff_flavour
,
3188 BFD_ENDIAN_LITTLE
, /* data byte order is little */
3189 BFD_ENDIAN_LITTLE
, /* header byte order is little endian too*/
3191 (HAS_RELOC
| EXEC_P
/* object flags */
3192 | HAS_LINENO
| HAS_DEBUG
3193 | HAS_SYMS
| HAS_LOCALS
| WP_TEXT
| BFD_IS_RELAXABLE
),
3195 (SEC_HAS_CONTENTS
| SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
),
3196 '_', /* leading symbol underscore */
3197 '/', /* ar_pad_char */
3198 15, /* ar_max_namelen */
3199 0, /* match priority. */
3200 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3201 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3202 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* data */
3203 bfd_getl64
, bfd_getl_signed_64
, bfd_putl64
,
3204 bfd_getl32
, bfd_getl_signed_32
, bfd_putl32
,
3205 bfd_getl16
, bfd_getl_signed_16
, bfd_putl16
, /* hdrs */
3207 { /* bfd_check_format */
3209 coff_small_object_p
,
3210 bfd_generic_archive_p
,
3213 { /* bfd_set_format */
3214 _bfd_bool_bfd_false_error
,
3216 _bfd_generic_mkarchive
,
3217 _bfd_bool_bfd_false_error
3219 { /* bfd_write_contents */
3220 _bfd_bool_bfd_false_error
,
3221 coff_write_object_contents
,
3222 _bfd_write_archive_contents
,
3223 _bfd_bool_bfd_false_error
3226 BFD_JUMP_TABLE_GENERIC (coff_small
),
3227 BFD_JUMP_TABLE_COPY (coff
),
3228 BFD_JUMP_TABLE_CORE (_bfd_nocore
),
3229 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff
),
3230 BFD_JUMP_TABLE_SYMBOLS (coff
),
3231 BFD_JUMP_TABLE_RELOCS (coff
),
3232 BFD_JUMP_TABLE_WRITE (coff
),
3233 BFD_JUMP_TABLE_LINK (coff
),
3234 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic
),
3238 &bfd_coff_small_swap_table