1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2019 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The encoded size of the item to be relocated. This is *not* a
291 . power-of-two measure. Use bfd_get_reloc_size to find the size
292 . of the item in bytes. *}
293 . unsigned int size:3;
295 . {* The number of bits in the field to be relocated. This is used
296 . when doing overflow checking. *}
297 . unsigned int bitsize:7;
299 . {* The value the final relocation is shifted right by. This drops
300 . unwanted data from the relocation. *}
301 . unsigned int rightshift:6;
303 . {* The bit position of the reloc value in the destination.
304 . The relocated value is left shifted by this amount. *}
305 . unsigned int bitpos:6;
307 . {* What type of overflow error should be checked for when
309 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
311 . {* The relocation value should be negated before applying. *}
312 . unsigned int negate:1;
314 . {* The relocation is relative to the item being relocated. *}
315 . unsigned int pc_relative:1;
317 . {* Some formats record a relocation addend in the section contents
318 . rather than with the relocation. For ELF formats this is the
319 . distinction between USE_REL and USE_RELA (though the code checks
320 . for USE_REL == 1/0). The value of this field is TRUE if the
321 . addend is recorded with the section contents; when performing a
322 . partial link (ld -r) the section contents (the data) will be
323 . modified. The value of this field is FALSE if addends are
324 . recorded with the relocation (in arelent.addend); when performing
325 . a partial link the relocation will be modified.
326 . All relocations for all ELF USE_RELA targets should set this field
327 . to FALSE (values of TRUE should be looked on with suspicion).
328 . However, the converse is not true: not all relocations of all ELF
329 . USE_REL targets set this field to TRUE. Why this is so is peculiar
330 . to each particular target. For relocs that aren't used in partial
331 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
332 . unsigned int partial_inplace:1;
334 . {* When some formats create PC relative instructions, they leave
335 . the value of the pc of the place being relocated in the offset
336 . slot of the instruction, so that a PC relative relocation can
337 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
338 . Some formats leave the displacement part of an instruction
339 . empty (e.g., ELF); this flag signals the fact. *}
340 . unsigned int pcrel_offset:1;
342 . {* src_mask selects the part of the instruction (or data) to be used
343 . in the relocation sum. If the target relocations don't have an
344 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
345 . dst_mask to extract the addend from the section contents. If
346 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
347 . field should normally be zero. Non-zero values for ELF USE_RELA
348 . targets should be viewed with suspicion as normally the value in
349 . the dst_mask part of the section contents should be ignored. *}
352 . {* dst_mask selects which parts of the instruction (or data) are
353 . replaced with a relocated value. *}
356 . {* If this field is non null, then the supplied function is
357 . called rather than the normal function. This allows really
358 . strange relocation methods to be accommodated. *}
359 . bfd_reloc_status_type (*special_function)
360 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
363 . {* The textual name of the relocation type. *}
374 The HOWTO macro fills in a reloc_howto_type (a typedef for
375 const struct reloc_howto_struct).
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
387 . NULL, FALSE, 0, 0, FALSE)
396 unsigned int bfd_get_reloc_size (reloc_howto_type *);
399 For a reloc_howto_type that operates on a fixed number of bytes,
400 this returns the number of bytes operated on.
404 bfd_get_reloc_size (reloc_howto_type
*howto
)
424 How relocs are tied together in an <<asection>>:
426 .typedef struct relent_chain
429 . struct relent_chain *next;
435 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
436 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
443 bfd_reloc_status_type bfd_check_overflow
444 (enum complain_overflow how,
445 unsigned int bitsize,
446 unsigned int rightshift,
447 unsigned int addrsize,
451 Perform overflow checking on @var{relocation} which has
452 @var{bitsize} significant bits and will be shifted right by
453 @var{rightshift} bits, on a machine with addresses containing
454 @var{addrsize} significant bits. The result is either of
455 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
459 bfd_reloc_status_type
460 bfd_check_overflow (enum complain_overflow how
,
461 unsigned int bitsize
,
462 unsigned int rightshift
,
463 unsigned int addrsize
,
466 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
467 bfd_reloc_status_type flag
= bfd_reloc_ok
;
469 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
470 we'll be permissive: extra bits in the field mask will
471 automatically extend the address mask for purposes of the
473 fieldmask
= N_ONES (bitsize
);
474 signmask
= ~fieldmask
;
475 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
476 a
= (relocation
& addrmask
) >> rightshift
;
480 case complain_overflow_dont
:
483 case complain_overflow_signed
:
484 /* If any sign bits are set, all sign bits must be set. That
485 is, A must be a valid negative address after shifting. */
486 signmask
= ~ (fieldmask
>> 1);
489 case complain_overflow_bitfield
:
490 /* Bitfields are sometimes signed, sometimes unsigned. We
491 explicitly allow an address wrap too, which means a bitfield
492 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
493 if the value has some, but not all, bits set outside the
496 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
497 flag
= bfd_reloc_overflow
;
500 case complain_overflow_unsigned
:
501 /* We have an overflow if the address does not fit in the field. */
502 if ((a
& signmask
) != 0)
503 flag
= bfd_reloc_overflow
;
515 bfd_reloc_offset_in_range
518 bfd_boolean bfd_reloc_offset_in_range
519 (reloc_howto_type *howto,
522 bfd_size_type offset);
525 Returns TRUE if the reloc described by @var{HOWTO} can be
526 applied at @var{OFFSET} octets in @var{SECTION}.
530 /* HOWTO describes a relocation, at offset OCTET. Return whether the
531 relocation field is within SECTION of ABFD. */
534 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
539 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
540 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
542 /* The reloc field must be contained entirely within the section.
543 Allow zero length fields (marker relocs or NONE relocs where no
544 relocation will be performed) at the end of the section. */
545 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
548 /* Read and return the section contents at DATA converted to a host
549 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
552 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
557 return bfd_get_8 (abfd
, data
);
560 return bfd_get_16 (abfd
, data
);
563 return bfd_get_32 (abfd
, data
);
570 return bfd_get_64 (abfd
, data
);
574 return bfd_get_24 (abfd
, data
);
582 /* Convert VAL to target format and write to DATA. The number of
583 bytes written is given by the HOWTO. */
586 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
591 bfd_put_8 (abfd
, val
, data
);
595 bfd_put_16 (abfd
, val
, data
);
599 bfd_put_32 (abfd
, val
, data
);
607 bfd_put_64 (abfd
, val
, data
);
612 bfd_put_24 (abfd
, val
, data
);
620 /* Apply RELOCATION value to target bytes at DATA, according to
624 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
627 bfd_vma val
= read_reloc (abfd
, data
, howto
);
630 relocation
= -relocation
;
632 val
= ((val
& ~howto
->dst_mask
)
633 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
635 write_reloc (abfd
, val
, data
, howto
);
640 bfd_perform_relocation
643 bfd_reloc_status_type bfd_perform_relocation
645 arelent *reloc_entry,
647 asection *input_section,
649 char **error_message);
652 If @var{output_bfd} is supplied to this function, the
653 generated image will be relocatable; the relocations are
654 copied to the output file after they have been changed to
655 reflect the new state of the world. There are two ways of
656 reflecting the results of partial linkage in an output file:
657 by modifying the output data in place, and by modifying the
658 relocation record. Some native formats (e.g., basic a.out and
659 basic coff) have no way of specifying an addend in the
660 relocation type, so the addend has to go in the output data.
661 This is no big deal since in these formats the output data
662 slot will always be big enough for the addend. Complex reloc
663 types with addends were invented to solve just this problem.
664 The @var{error_message} argument is set to an error message if
665 this return @code{bfd_reloc_dangerous}.
669 bfd_reloc_status_type
670 bfd_perform_relocation (bfd
*abfd
,
671 arelent
*reloc_entry
,
673 asection
*input_section
,
675 char **error_message
)
678 bfd_reloc_status_type flag
= bfd_reloc_ok
;
679 bfd_size_type octets
;
680 bfd_vma output_base
= 0;
681 reloc_howto_type
*howto
= reloc_entry
->howto
;
682 asection
*reloc_target_output_section
;
685 symbol
= *(reloc_entry
->sym_ptr_ptr
);
687 /* If we are not producing relocatable output, return an error if
688 the symbol is not defined. An undefined weak symbol is
689 considered to have a value of zero (SVR4 ABI, p. 4-27). */
690 if (bfd_is_und_section (symbol
->section
)
691 && (symbol
->flags
& BSF_WEAK
) == 0
692 && output_bfd
== NULL
)
693 flag
= bfd_reloc_undefined
;
695 /* If there is a function supplied to handle this relocation type,
696 call it. It'll return `bfd_reloc_continue' if further processing
698 if (howto
&& howto
->special_function
)
700 bfd_reloc_status_type cont
;
702 /* Note - we do not call bfd_reloc_offset_in_range here as the
703 reloc_entry->address field might actually be valid for the
704 backend concerned. It is up to the special_function itself
705 to call bfd_reloc_offset_in_range if needed. */
706 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
707 input_section
, output_bfd
,
709 if (cont
!= bfd_reloc_continue
)
713 if (bfd_is_abs_section (symbol
->section
)
714 && output_bfd
!= NULL
)
716 reloc_entry
->address
+= input_section
->output_offset
;
720 /* PR 17512: file: 0f67f69d. */
722 return bfd_reloc_undefined
;
724 /* Is the address of the relocation really within the section? */
725 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
726 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
727 return bfd_reloc_outofrange
;
729 /* Work out which section the relocation is targeted at and the
730 initial relocation command value. */
732 /* Get symbol value. (Common symbols are special.) */
733 if (bfd_is_com_section (symbol
->section
))
736 relocation
= symbol
->value
;
738 reloc_target_output_section
= symbol
->section
->output_section
;
740 /* Convert input-section-relative symbol value to absolute. */
741 if ((output_bfd
&& ! howto
->partial_inplace
)
742 || reloc_target_output_section
== NULL
)
745 output_base
= reloc_target_output_section
->vma
;
747 relocation
+= output_base
+ symbol
->section
->output_offset
;
749 /* Add in supplied addend. */
750 relocation
+= reloc_entry
->addend
;
752 /* Here the variable relocation holds the final address of the
753 symbol we are relocating against, plus any addend. */
755 if (howto
->pc_relative
)
757 /* This is a PC relative relocation. We want to set RELOCATION
758 to the distance between the address of the symbol and the
759 location. RELOCATION is already the address of the symbol.
761 We start by subtracting the address of the section containing
764 If pcrel_offset is set, we must further subtract the position
765 of the location within the section. Some targets arrange for
766 the addend to be the negative of the position of the location
767 within the section; for example, i386-aout does this. For
768 i386-aout, pcrel_offset is FALSE. Some other targets do not
769 include the position of the location; for example, ELF.
770 For those targets, pcrel_offset is TRUE.
772 If we are producing relocatable output, then we must ensure
773 that this reloc will be correctly computed when the final
774 relocation is done. If pcrel_offset is FALSE we want to wind
775 up with the negative of the location within the section,
776 which means we must adjust the existing addend by the change
777 in the location within the section. If pcrel_offset is TRUE
778 we do not want to adjust the existing addend at all.
780 FIXME: This seems logical to me, but for the case of
781 producing relocatable output it is not what the code
782 actually does. I don't want to change it, because it seems
783 far too likely that something will break. */
786 input_section
->output_section
->vma
+ input_section
->output_offset
;
788 if (howto
->pcrel_offset
)
789 relocation
-= reloc_entry
->address
;
792 if (output_bfd
!= NULL
)
794 if (! howto
->partial_inplace
)
796 /* This is a partial relocation, and we want to apply the relocation
797 to the reloc entry rather than the raw data. Modify the reloc
798 inplace to reflect what we now know. */
799 reloc_entry
->addend
= relocation
;
800 reloc_entry
->address
+= input_section
->output_offset
;
805 /* This is a partial relocation, but inplace, so modify the
808 If we've relocated with a symbol with a section, change
809 into a ref to the section belonging to the symbol. */
811 reloc_entry
->address
+= input_section
->output_offset
;
814 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
815 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
816 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
818 /* For m68k-coff, the addend was being subtracted twice during
819 relocation with -r. Removing the line below this comment
820 fixes that problem; see PR 2953.
822 However, Ian wrote the following, regarding removing the line below,
823 which explains why it is still enabled: --djm
825 If you put a patch like that into BFD you need to check all the COFF
826 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
827 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
828 problem in a different way. There may very well be a reason that the
829 code works as it does.
831 Hmmm. The first obvious point is that bfd_perform_relocation should
832 not have any tests that depend upon the flavour. It's seem like
833 entirely the wrong place for such a thing. The second obvious point
834 is that the current code ignores the reloc addend when producing
835 relocatable output for COFF. That's peculiar. In fact, I really
836 have no idea what the point of the line you want to remove is.
838 A typical COFF reloc subtracts the old value of the symbol and adds in
839 the new value to the location in the object file (if it's a pc
840 relative reloc it adds the difference between the symbol value and the
841 location). When relocating we need to preserve that property.
843 BFD handles this by setting the addend to the negative of the old
844 value of the symbol. Unfortunately it handles common symbols in a
845 non-standard way (it doesn't subtract the old value) but that's a
846 different story (we can't change it without losing backward
847 compatibility with old object files) (coff-i386 does subtract the old
848 value, to be compatible with existing coff-i386 targets, like SCO).
850 So everything works fine when not producing relocatable output. When
851 we are producing relocatable output, logically we should do exactly
852 what we do when not producing relocatable output. Therefore, your
853 patch is correct. In fact, it should probably always just set
854 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
855 add the value into the object file. This won't hurt the COFF code,
856 which doesn't use the addend; I'm not sure what it will do to other
857 formats (the thing to check for would be whether any formats both use
858 the addend and set partial_inplace).
860 When I wanted to make coff-i386 produce relocatable output, I ran
861 into the problem that you are running into: I wanted to remove that
862 line. Rather than risk it, I made the coff-i386 relocs use a special
863 function; it's coff_i386_reloc in coff-i386.c. The function
864 specifically adds the addend field into the object file, knowing that
865 bfd_perform_relocation is not going to. If you remove that line, then
866 coff-i386.c will wind up adding the addend field in twice. It's
867 trivial to fix; it just needs to be done.
869 The problem with removing the line is just that it may break some
870 working code. With BFD it's hard to be sure of anything. The right
871 way to deal with this is simply to build and test at least all the
872 supported COFF targets. It should be straightforward if time and disk
873 space consuming. For each target:
875 2) generate some executable, and link it using -r (I would
876 probably use paranoia.o and link against newlib/libc.a, which
877 for all the supported targets would be available in
878 /usr/cygnus/progressive/H-host/target/lib/libc.a).
879 3) make the change to reloc.c
880 4) rebuild the linker
882 6) if the resulting object files are the same, you have at least
884 7) if they are different you have to figure out which version is
887 relocation
-= reloc_entry
->addend
;
888 reloc_entry
->addend
= 0;
892 reloc_entry
->addend
= relocation
;
897 /* FIXME: This overflow checking is incomplete, because the value
898 might have overflowed before we get here. For a correct check we
899 need to compute the value in a size larger than bitsize, but we
900 can't reasonably do that for a reloc the same size as a host
902 FIXME: We should also do overflow checking on the result after
903 adding in the value contained in the object file. */
904 if (howto
->complain_on_overflow
!= complain_overflow_dont
905 && flag
== bfd_reloc_ok
)
906 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
909 bfd_arch_bits_per_address (abfd
),
912 /* Either we are relocating all the way, or we don't want to apply
913 the relocation to the reloc entry (probably because there isn't
914 any room in the output format to describe addends to relocs). */
916 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
917 (OSF version 1.3, compiler version 3.11). It miscompiles the
931 x <<= (unsigned long) s.i0;
935 printf ("succeeded (%lx)\n", x);
939 relocation
>>= (bfd_vma
) howto
->rightshift
;
941 /* Shift everything up to where it's going to be used. */
942 relocation
<<= (bfd_vma
) howto
->bitpos
;
944 /* Wait for the day when all have the mask in them. */
947 i instruction to be left alone
948 o offset within instruction
949 r relocation offset to apply
958 (( i i i i i o o o o o from bfd_get<size>
959 and S S S S S) to get the size offset we want
960 + r r r r r r r r r r) to get the final value to place
961 and D D D D D to chop to right size
962 -----------------------
965 ( i i i i i o o o o o from bfd_get<size>
966 and N N N N N ) get instruction
967 -----------------------
973 -----------------------
974 = R R R R R R R R R R put into bfd_put<size>
977 data
= (bfd_byte
*) data
+ octets
;
978 apply_reloc (abfd
, data
, howto
, relocation
);
984 bfd_install_relocation
987 bfd_reloc_status_type bfd_install_relocation
989 arelent *reloc_entry,
990 void *data, bfd_vma data_start,
991 asection *input_section,
992 char **error_message);
995 This looks remarkably like <<bfd_perform_relocation>>, except it
996 does not expect that the section contents have been filled in.
997 I.e., it's suitable for use when creating, rather than applying
1000 For now, this function should be considered reserved for the
1004 bfd_reloc_status_type
1005 bfd_install_relocation (bfd
*abfd
,
1006 arelent
*reloc_entry
,
1008 bfd_vma data_start_offset
,
1009 asection
*input_section
,
1010 char **error_message
)
1013 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1014 bfd_size_type octets
;
1015 bfd_vma output_base
= 0;
1016 reloc_howto_type
*howto
= reloc_entry
->howto
;
1017 asection
*reloc_target_output_section
;
1021 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1023 /* If there is a function supplied to handle this relocation type,
1024 call it. It'll return `bfd_reloc_continue' if further processing
1026 if (howto
&& howto
->special_function
)
1028 bfd_reloc_status_type cont
;
1030 /* Note - we do not call bfd_reloc_offset_in_range here as the
1031 reloc_entry->address field might actually be valid for the
1032 backend concerned. It is up to the special_function itself
1033 to call bfd_reloc_offset_in_range if needed. */
1034 /* XXX - The special_function calls haven't been fixed up to deal
1035 with creating new relocations and section contents. */
1036 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1037 /* XXX - Non-portable! */
1038 ((bfd_byte
*) data_start
1039 - data_start_offset
),
1040 input_section
, abfd
, error_message
);
1041 if (cont
!= bfd_reloc_continue
)
1045 if (bfd_is_abs_section (symbol
->section
))
1047 reloc_entry
->address
+= input_section
->output_offset
;
1048 return bfd_reloc_ok
;
1051 /* No need to check for howto != NULL if !bfd_is_abs_section as
1052 it will have been checked in `bfd_perform_relocation already'. */
1054 /* Is the address of the relocation really within the section? */
1055 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1056 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1057 return bfd_reloc_outofrange
;
1059 /* Work out which section the relocation is targeted at and the
1060 initial relocation command value. */
1062 /* Get symbol value. (Common symbols are special.) */
1063 if (bfd_is_com_section (symbol
->section
))
1066 relocation
= symbol
->value
;
1068 reloc_target_output_section
= symbol
->section
->output_section
;
1070 /* Convert input-section-relative symbol value to absolute. */
1071 if (! howto
->partial_inplace
)
1074 output_base
= reloc_target_output_section
->vma
;
1076 relocation
+= output_base
+ symbol
->section
->output_offset
;
1078 /* Add in supplied addend. */
1079 relocation
+= reloc_entry
->addend
;
1081 /* Here the variable relocation holds the final address of the
1082 symbol we are relocating against, plus any addend. */
1084 if (howto
->pc_relative
)
1086 /* This is a PC relative relocation. We want to set RELOCATION
1087 to the distance between the address of the symbol and the
1088 location. RELOCATION is already the address of the symbol.
1090 We start by subtracting the address of the section containing
1093 If pcrel_offset is set, we must further subtract the position
1094 of the location within the section. Some targets arrange for
1095 the addend to be the negative of the position of the location
1096 within the section; for example, i386-aout does this. For
1097 i386-aout, pcrel_offset is FALSE. Some other targets do not
1098 include the position of the location; for example, ELF.
1099 For those targets, pcrel_offset is TRUE.
1101 If we are producing relocatable output, then we must ensure
1102 that this reloc will be correctly computed when the final
1103 relocation is done. If pcrel_offset is FALSE we want to wind
1104 up with the negative of the location within the section,
1105 which means we must adjust the existing addend by the change
1106 in the location within the section. If pcrel_offset is TRUE
1107 we do not want to adjust the existing addend at all.
1109 FIXME: This seems logical to me, but for the case of
1110 producing relocatable output it is not what the code
1111 actually does. I don't want to change it, because it seems
1112 far too likely that something will break. */
1115 input_section
->output_section
->vma
+ input_section
->output_offset
;
1117 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1118 relocation
-= reloc_entry
->address
;
1121 if (! howto
->partial_inplace
)
1123 /* This is a partial relocation, and we want to apply the relocation
1124 to the reloc entry rather than the raw data. Modify the reloc
1125 inplace to reflect what we now know. */
1126 reloc_entry
->addend
= relocation
;
1127 reloc_entry
->address
+= input_section
->output_offset
;
1132 /* This is a partial relocation, but inplace, so modify the
1135 If we've relocated with a symbol with a section, change
1136 into a ref to the section belonging to the symbol. */
1137 reloc_entry
->address
+= input_section
->output_offset
;
1140 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1141 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1142 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1145 /* For m68k-coff, the addend was being subtracted twice during
1146 relocation with -r. Removing the line below this comment
1147 fixes that problem; see PR 2953.
1149 However, Ian wrote the following, regarding removing the line below,
1150 which explains why it is still enabled: --djm
1152 If you put a patch like that into BFD you need to check all the COFF
1153 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1154 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1155 problem in a different way. There may very well be a reason that the
1156 code works as it does.
1158 Hmmm. The first obvious point is that bfd_install_relocation should
1159 not have any tests that depend upon the flavour. It's seem like
1160 entirely the wrong place for such a thing. The second obvious point
1161 is that the current code ignores the reloc addend when producing
1162 relocatable output for COFF. That's peculiar. In fact, I really
1163 have no idea what the point of the line you want to remove is.
1165 A typical COFF reloc subtracts the old value of the symbol and adds in
1166 the new value to the location in the object file (if it's a pc
1167 relative reloc it adds the difference between the symbol value and the
1168 location). When relocating we need to preserve that property.
1170 BFD handles this by setting the addend to the negative of the old
1171 value of the symbol. Unfortunately it handles common symbols in a
1172 non-standard way (it doesn't subtract the old value) but that's a
1173 different story (we can't change it without losing backward
1174 compatibility with old object files) (coff-i386 does subtract the old
1175 value, to be compatible with existing coff-i386 targets, like SCO).
1177 So everything works fine when not producing relocatable output. When
1178 we are producing relocatable output, logically we should do exactly
1179 what we do when not producing relocatable output. Therefore, your
1180 patch is correct. In fact, it should probably always just set
1181 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1182 add the value into the object file. This won't hurt the COFF code,
1183 which doesn't use the addend; I'm not sure what it will do to other
1184 formats (the thing to check for would be whether any formats both use
1185 the addend and set partial_inplace).
1187 When I wanted to make coff-i386 produce relocatable output, I ran
1188 into the problem that you are running into: I wanted to remove that
1189 line. Rather than risk it, I made the coff-i386 relocs use a special
1190 function; it's coff_i386_reloc in coff-i386.c. The function
1191 specifically adds the addend field into the object file, knowing that
1192 bfd_install_relocation is not going to. If you remove that line, then
1193 coff-i386.c will wind up adding the addend field in twice. It's
1194 trivial to fix; it just needs to be done.
1196 The problem with removing the line is just that it may break some
1197 working code. With BFD it's hard to be sure of anything. The right
1198 way to deal with this is simply to build and test at least all the
1199 supported COFF targets. It should be straightforward if time and disk
1200 space consuming. For each target:
1202 2) generate some executable, and link it using -r (I would
1203 probably use paranoia.o and link against newlib/libc.a, which
1204 for all the supported targets would be available in
1205 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1206 3) make the change to reloc.c
1207 4) rebuild the linker
1209 6) if the resulting object files are the same, you have at least
1211 7) if they are different you have to figure out which version is
1213 relocation
-= reloc_entry
->addend
;
1214 /* FIXME: There should be no target specific code here... */
1215 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1216 reloc_entry
->addend
= 0;
1220 reloc_entry
->addend
= relocation
;
1224 /* FIXME: This overflow checking is incomplete, because the value
1225 might have overflowed before we get here. For a correct check we
1226 need to compute the value in a size larger than bitsize, but we
1227 can't reasonably do that for a reloc the same size as a host
1229 FIXME: We should also do overflow checking on the result after
1230 adding in the value contained in the object file. */
1231 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1232 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1235 bfd_arch_bits_per_address (abfd
),
1238 /* Either we are relocating all the way, or we don't want to apply
1239 the relocation to the reloc entry (probably because there isn't
1240 any room in the output format to describe addends to relocs). */
1242 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1243 (OSF version 1.3, compiler version 3.11). It miscompiles the
1257 x <<= (unsigned long) s.i0;
1259 printf ("failed\n");
1261 printf ("succeeded (%lx)\n", x);
1265 relocation
>>= (bfd_vma
) howto
->rightshift
;
1267 /* Shift everything up to where it's going to be used. */
1268 relocation
<<= (bfd_vma
) howto
->bitpos
;
1270 /* Wait for the day when all have the mask in them. */
1273 i instruction to be left alone
1274 o offset within instruction
1275 r relocation offset to apply
1284 (( i i i i i o o o o o from bfd_get<size>
1285 and S S S S S) to get the size offset we want
1286 + r r r r r r r r r r) to get the final value to place
1287 and D D D D D to chop to right size
1288 -----------------------
1291 ( i i i i i o o o o o from bfd_get<size>
1292 and N N N N N ) get instruction
1293 -----------------------
1299 -----------------------
1300 = R R R R R R R R R R put into bfd_put<size>
1303 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1304 apply_reloc (abfd
, data
, howto
, relocation
);
1308 /* This relocation routine is used by some of the backend linkers.
1309 They do not construct asymbol or arelent structures, so there is no
1310 reason for them to use bfd_perform_relocation. Also,
1311 bfd_perform_relocation is so hacked up it is easier to write a new
1312 function than to try to deal with it.
1314 This routine does a final relocation. Whether it is useful for a
1315 relocatable link depends upon how the object format defines
1318 FIXME: This routine ignores any special_function in the HOWTO,
1319 since the existing special_function values have been written for
1320 bfd_perform_relocation.
1322 HOWTO is the reloc howto information.
1323 INPUT_BFD is the BFD which the reloc applies to.
1324 INPUT_SECTION is the section which the reloc applies to.
1325 CONTENTS is the contents of the section.
1326 ADDRESS is the address of the reloc within INPUT_SECTION.
1327 VALUE is the value of the symbol the reloc refers to.
1328 ADDEND is the addend of the reloc. */
1330 bfd_reloc_status_type
1331 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1333 asection
*input_section
,
1340 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1342 /* Sanity check the address. */
1343 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1344 return bfd_reloc_outofrange
;
1346 /* This function assumes that we are dealing with a basic relocation
1347 against a symbol. We want to compute the value of the symbol to
1348 relocate to. This is just VALUE, the value of the symbol, plus
1349 ADDEND, any addend associated with the reloc. */
1350 relocation
= value
+ addend
;
1352 /* If the relocation is PC relative, we want to set RELOCATION to
1353 the distance between the symbol (currently in RELOCATION) and the
1354 location we are relocating. Some targets (e.g., i386-aout)
1355 arrange for the contents of the section to be the negative of the
1356 offset of the location within the section; for such targets
1357 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1358 the contents of the section as zero; for such targets
1359 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1360 subtract out the offset of the location within the section (which
1361 is just ADDRESS). */
1362 if (howto
->pc_relative
)
1364 relocation
-= (input_section
->output_section
->vma
1365 + input_section
->output_offset
);
1366 if (howto
->pcrel_offset
)
1367 relocation
-= address
;
1370 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1372 + address
* bfd_octets_per_byte (input_bfd
));
1375 /* Relocate a given location using a given value and howto. */
1377 bfd_reloc_status_type
1378 _bfd_relocate_contents (reloc_howto_type
*howto
,
1384 bfd_reloc_status_type flag
;
1385 unsigned int rightshift
= howto
->rightshift
;
1386 unsigned int bitpos
= howto
->bitpos
;
1389 relocation
= -relocation
;
1391 /* Get the value we are going to relocate. */
1392 x
= read_reloc (input_bfd
, location
, howto
);
1394 /* Check for overflow. FIXME: We may drop bits during the addition
1395 which we don't check for. We must either check at every single
1396 operation, which would be tedious, or we must do the computations
1397 in a type larger than bfd_vma, which would be inefficient. */
1398 flag
= bfd_reloc_ok
;
1399 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1401 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1404 /* Get the values to be added together. For signed and unsigned
1405 relocations, we assume that all values should be truncated to
1406 the size of an address. For bitfields, all the bits matter.
1407 See also bfd_check_overflow. */
1408 fieldmask
= N_ONES (howto
->bitsize
);
1409 signmask
= ~fieldmask
;
1410 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1411 | (fieldmask
<< rightshift
));
1412 a
= (relocation
& addrmask
) >> rightshift
;
1413 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1414 addrmask
>>= rightshift
;
1416 switch (howto
->complain_on_overflow
)
1418 case complain_overflow_signed
:
1419 /* If any sign bits are set, all sign bits must be set.
1420 That is, A must be a valid negative address after
1422 signmask
= ~(fieldmask
>> 1);
1425 case complain_overflow_bitfield
:
1426 /* Much like the signed check, but for a field one bit
1427 wider. We allow a bitfield to represent numbers in the
1428 range -2**n to 2**n-1, where n is the number of bits in the
1429 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1430 can't overflow, which is exactly what we want. */
1432 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1433 flag
= bfd_reloc_overflow
;
1435 /* We only need this next bit of code if the sign bit of B
1436 is below the sign bit of A. This would only happen if
1437 SRC_MASK had fewer bits than BITSIZE. Note that if
1438 SRC_MASK has more bits than BITSIZE, we can get into
1439 trouble; we would need to verify that B is in range, as
1440 we do for A above. */
1441 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1444 /* Set all the bits above the sign bit. */
1447 /* Now we can do the addition. */
1450 /* See if the result has the correct sign. Bits above the
1451 sign bit are junk now; ignore them. If the sum is
1452 positive, make sure we did not have all negative inputs;
1453 if the sum is negative, make sure we did not have all
1454 positive inputs. The test below looks only at the sign
1455 bits, and it really just
1456 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1458 We mask with addrmask here to explicitly allow an address
1459 wrap-around. The Linux kernel relies on it, and it is
1460 the only way to write assembler code which can run when
1461 loaded at a location 0x80000000 away from the location at
1462 which it is linked. */
1463 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1464 flag
= bfd_reloc_overflow
;
1467 case complain_overflow_unsigned
:
1468 /* Checking for an unsigned overflow is relatively easy:
1469 trim the addresses and add, and trim the result as well.
1470 Overflow is normally indicated when the result does not
1471 fit in the field. However, we also need to consider the
1472 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1473 input is 0x80000000, and bfd_vma is only 32 bits; then we
1474 will get sum == 0, but there is an overflow, since the
1475 inputs did not fit in the field. Instead of doing a
1476 separate test, we can check for this by or-ing in the
1477 operands when testing for the sum overflowing its final
1479 sum
= (a
+ b
) & addrmask
;
1480 if ((a
| b
| sum
) & signmask
)
1481 flag
= bfd_reloc_overflow
;
1489 /* Put RELOCATION in the right bits. */
1490 relocation
>>= (bfd_vma
) rightshift
;
1491 relocation
<<= (bfd_vma
) bitpos
;
1493 /* Add RELOCATION to the right bits of X. */
1494 x
= ((x
& ~howto
->dst_mask
)
1495 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1497 /* Put the relocated value back in the object file. */
1498 write_reloc (input_bfd
, x
, location
, howto
);
1502 /* Clear a given location using a given howto, by applying a fixed relocation
1503 value and discarding any in-place addend. This is used for fixed-up
1504 relocations against discarded symbols, to make ignorable debug or unwind
1505 information more obvious. */
1507 bfd_reloc_status_type
1508 _bfd_clear_contents (reloc_howto_type
*howto
,
1510 asection
*input_section
,
1517 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1518 return bfd_reloc_outofrange
;
1520 /* Get the value we are going to relocate. */
1521 location
= buf
+ off
;
1522 x
= read_reloc (input_bfd
, location
, howto
);
1524 /* Zero out the unwanted bits of X. */
1525 x
&= ~howto
->dst_mask
;
1527 /* For a range list, use 1 instead of 0 as placeholder. 0
1528 would terminate the list, hiding any later entries. */
1529 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1530 ".debug_ranges") == 0
1531 && (howto
->dst_mask
& 1) != 0)
1534 /* Put the relocated value back in the object file. */
1535 write_reloc (input_bfd
, x
, location
, howto
);
1536 return bfd_reloc_ok
;
1542 howto manager, , typedef arelent, Relocations
1547 When an application wants to create a relocation, but doesn't
1548 know what the target machine might call it, it can find out by
1549 using this bit of code.
1558 The insides of a reloc code. The idea is that, eventually, there
1559 will be one enumerator for every type of relocation we ever do.
1560 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1561 return a howto pointer.
1563 This does mean that the application must determine the correct
1564 enumerator value; you can't get a howto pointer from a random set
1585 Basic absolute relocations of N bits.
1600 PC-relative relocations. Sometimes these are relative to the address
1601 of the relocation itself; sometimes they are relative to the start of
1602 the section containing the relocation. It depends on the specific target.
1607 Section relative relocations. Some targets need this for DWARF2.
1610 BFD_RELOC_32_GOT_PCREL
1612 BFD_RELOC_16_GOT_PCREL
1614 BFD_RELOC_8_GOT_PCREL
1620 BFD_RELOC_LO16_GOTOFF
1622 BFD_RELOC_HI16_GOTOFF
1624 BFD_RELOC_HI16_S_GOTOFF
1628 BFD_RELOC_64_PLT_PCREL
1630 BFD_RELOC_32_PLT_PCREL
1632 BFD_RELOC_24_PLT_PCREL
1634 BFD_RELOC_16_PLT_PCREL
1636 BFD_RELOC_8_PLT_PCREL
1644 BFD_RELOC_LO16_PLTOFF
1646 BFD_RELOC_HI16_PLTOFF
1648 BFD_RELOC_HI16_S_PLTOFF
1662 BFD_RELOC_68K_GLOB_DAT
1664 BFD_RELOC_68K_JMP_SLOT
1666 BFD_RELOC_68K_RELATIVE
1668 BFD_RELOC_68K_TLS_GD32
1670 BFD_RELOC_68K_TLS_GD16
1672 BFD_RELOC_68K_TLS_GD8
1674 BFD_RELOC_68K_TLS_LDM32
1676 BFD_RELOC_68K_TLS_LDM16
1678 BFD_RELOC_68K_TLS_LDM8
1680 BFD_RELOC_68K_TLS_LDO32
1682 BFD_RELOC_68K_TLS_LDO16
1684 BFD_RELOC_68K_TLS_LDO8
1686 BFD_RELOC_68K_TLS_IE32
1688 BFD_RELOC_68K_TLS_IE16
1690 BFD_RELOC_68K_TLS_IE8
1692 BFD_RELOC_68K_TLS_LE32
1694 BFD_RELOC_68K_TLS_LE16
1696 BFD_RELOC_68K_TLS_LE8
1698 Relocations used by 68K ELF.
1701 BFD_RELOC_32_BASEREL
1703 BFD_RELOC_16_BASEREL
1705 BFD_RELOC_LO16_BASEREL
1707 BFD_RELOC_HI16_BASEREL
1709 BFD_RELOC_HI16_S_BASEREL
1715 Linkage-table relative.
1720 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1723 BFD_RELOC_32_PCREL_S2
1725 BFD_RELOC_16_PCREL_S2
1727 BFD_RELOC_23_PCREL_S2
1729 These PC-relative relocations are stored as word displacements --
1730 i.e., byte displacements shifted right two bits. The 30-bit word
1731 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1732 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1733 signed 16-bit displacement is used on the MIPS, and the 23-bit
1734 displacement is used on the Alpha.
1741 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1742 the target word. These are used on the SPARC.
1749 For systems that allocate a Global Pointer register, these are
1750 displacements off that register. These relocation types are
1751 handled specially, because the value the register will have is
1752 decided relatively late.
1757 BFD_RELOC_SPARC_WDISP22
1763 BFD_RELOC_SPARC_GOT10
1765 BFD_RELOC_SPARC_GOT13
1767 BFD_RELOC_SPARC_GOT22
1769 BFD_RELOC_SPARC_PC10
1771 BFD_RELOC_SPARC_PC22
1773 BFD_RELOC_SPARC_WPLT30
1775 BFD_RELOC_SPARC_COPY
1777 BFD_RELOC_SPARC_GLOB_DAT
1779 BFD_RELOC_SPARC_JMP_SLOT
1781 BFD_RELOC_SPARC_RELATIVE
1783 BFD_RELOC_SPARC_UA16
1785 BFD_RELOC_SPARC_UA32
1787 BFD_RELOC_SPARC_UA64
1789 BFD_RELOC_SPARC_GOTDATA_HIX22
1791 BFD_RELOC_SPARC_GOTDATA_LOX10
1793 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1795 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1797 BFD_RELOC_SPARC_GOTDATA_OP
1799 BFD_RELOC_SPARC_JMP_IREL
1801 BFD_RELOC_SPARC_IRELATIVE
1803 SPARC ELF relocations. There is probably some overlap with other
1804 relocation types already defined.
1807 BFD_RELOC_SPARC_BASE13
1809 BFD_RELOC_SPARC_BASE22
1811 I think these are specific to SPARC a.out (e.g., Sun 4).
1821 BFD_RELOC_SPARC_OLO10
1823 BFD_RELOC_SPARC_HH22
1825 BFD_RELOC_SPARC_HM10
1827 BFD_RELOC_SPARC_LM22
1829 BFD_RELOC_SPARC_PC_HH22
1831 BFD_RELOC_SPARC_PC_HM10
1833 BFD_RELOC_SPARC_PC_LM22
1835 BFD_RELOC_SPARC_WDISP16
1837 BFD_RELOC_SPARC_WDISP19
1845 BFD_RELOC_SPARC_DISP64
1848 BFD_RELOC_SPARC_PLT32
1850 BFD_RELOC_SPARC_PLT64
1852 BFD_RELOC_SPARC_HIX22
1854 BFD_RELOC_SPARC_LOX10
1862 BFD_RELOC_SPARC_REGISTER
1866 BFD_RELOC_SPARC_SIZE32
1868 BFD_RELOC_SPARC_SIZE64
1870 BFD_RELOC_SPARC_WDISP10
1875 BFD_RELOC_SPARC_REV32
1877 SPARC little endian relocation
1879 BFD_RELOC_SPARC_TLS_GD_HI22
1881 BFD_RELOC_SPARC_TLS_GD_LO10
1883 BFD_RELOC_SPARC_TLS_GD_ADD
1885 BFD_RELOC_SPARC_TLS_GD_CALL
1887 BFD_RELOC_SPARC_TLS_LDM_HI22
1889 BFD_RELOC_SPARC_TLS_LDM_LO10
1891 BFD_RELOC_SPARC_TLS_LDM_ADD
1893 BFD_RELOC_SPARC_TLS_LDM_CALL
1895 BFD_RELOC_SPARC_TLS_LDO_HIX22
1897 BFD_RELOC_SPARC_TLS_LDO_LOX10
1899 BFD_RELOC_SPARC_TLS_LDO_ADD
1901 BFD_RELOC_SPARC_TLS_IE_HI22
1903 BFD_RELOC_SPARC_TLS_IE_LO10
1905 BFD_RELOC_SPARC_TLS_IE_LD
1907 BFD_RELOC_SPARC_TLS_IE_LDX
1909 BFD_RELOC_SPARC_TLS_IE_ADD
1911 BFD_RELOC_SPARC_TLS_LE_HIX22
1913 BFD_RELOC_SPARC_TLS_LE_LOX10
1915 BFD_RELOC_SPARC_TLS_DTPMOD32
1917 BFD_RELOC_SPARC_TLS_DTPMOD64
1919 BFD_RELOC_SPARC_TLS_DTPOFF32
1921 BFD_RELOC_SPARC_TLS_DTPOFF64
1923 BFD_RELOC_SPARC_TLS_TPOFF32
1925 BFD_RELOC_SPARC_TLS_TPOFF64
1927 SPARC TLS relocations
1936 BFD_RELOC_SPU_IMM10W
1940 BFD_RELOC_SPU_IMM16W
1944 BFD_RELOC_SPU_PCREL9a
1946 BFD_RELOC_SPU_PCREL9b
1948 BFD_RELOC_SPU_PCREL16
1958 BFD_RELOC_SPU_ADD_PIC
1963 BFD_RELOC_ALPHA_GPDISP_HI16
1965 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1966 "addend" in some special way.
1967 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1968 writing; when reading, it will be the absolute section symbol. The
1969 addend is the displacement in bytes of the "lda" instruction from
1970 the "ldah" instruction (which is at the address of this reloc).
1972 BFD_RELOC_ALPHA_GPDISP_LO16
1974 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1975 with GPDISP_HI16 relocs. The addend is ignored when writing the
1976 relocations out, and is filled in with the file's GP value on
1977 reading, for convenience.
1980 BFD_RELOC_ALPHA_GPDISP
1982 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1983 relocation except that there is no accompanying GPDISP_LO16
1987 BFD_RELOC_ALPHA_LITERAL
1989 BFD_RELOC_ALPHA_ELF_LITERAL
1991 BFD_RELOC_ALPHA_LITUSE
1993 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1994 the assembler turns it into a LDQ instruction to load the address of
1995 the symbol, and then fills in a register in the real instruction.
1997 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1998 section symbol. The addend is ignored when writing, but is filled
1999 in with the file's GP value on reading, for convenience, as with the
2002 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2003 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2004 but it generates output not based on the position within the .got
2005 section, but relative to the GP value chosen for the file during the
2008 The LITUSE reloc, on the instruction using the loaded address, gives
2009 information to the linker that it might be able to use to optimize
2010 away some literal section references. The symbol is ignored (read
2011 as the absolute section symbol), and the "addend" indicates the type
2012 of instruction using the register:
2013 1 - "memory" fmt insn
2014 2 - byte-manipulation (byte offset reg)
2015 3 - jsr (target of branch)
2018 BFD_RELOC_ALPHA_HINT
2020 The HINT relocation indicates a value that should be filled into the
2021 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2022 prediction logic which may be provided on some processors.
2025 BFD_RELOC_ALPHA_LINKAGE
2027 The LINKAGE relocation outputs a linkage pair in the object file,
2028 which is filled by the linker.
2031 BFD_RELOC_ALPHA_CODEADDR
2033 The CODEADDR relocation outputs a STO_CA in the object file,
2034 which is filled by the linker.
2037 BFD_RELOC_ALPHA_GPREL_HI16
2039 BFD_RELOC_ALPHA_GPREL_LO16
2041 The GPREL_HI/LO relocations together form a 32-bit offset from the
2045 BFD_RELOC_ALPHA_BRSGP
2047 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2048 share a common GP, and the target address is adjusted for
2049 STO_ALPHA_STD_GPLOAD.
2054 The NOP relocation outputs a NOP if the longword displacement
2055 between two procedure entry points is < 2^21.
2060 The BSR relocation outputs a BSR if the longword displacement
2061 between two procedure entry points is < 2^21.
2066 The LDA relocation outputs a LDA if the longword displacement
2067 between two procedure entry points is < 2^16.
2072 The BOH relocation outputs a BSR if the longword displacement
2073 between two procedure entry points is < 2^21, or else a hint.
2076 BFD_RELOC_ALPHA_TLSGD
2078 BFD_RELOC_ALPHA_TLSLDM
2080 BFD_RELOC_ALPHA_DTPMOD64
2082 BFD_RELOC_ALPHA_GOTDTPREL16
2084 BFD_RELOC_ALPHA_DTPREL64
2086 BFD_RELOC_ALPHA_DTPREL_HI16
2088 BFD_RELOC_ALPHA_DTPREL_LO16
2090 BFD_RELOC_ALPHA_DTPREL16
2092 BFD_RELOC_ALPHA_GOTTPREL16
2094 BFD_RELOC_ALPHA_TPREL64
2096 BFD_RELOC_ALPHA_TPREL_HI16
2098 BFD_RELOC_ALPHA_TPREL_LO16
2100 BFD_RELOC_ALPHA_TPREL16
2102 Alpha thread-local storage relocations.
2107 BFD_RELOC_MICROMIPS_JMP
2109 The MIPS jump instruction.
2112 BFD_RELOC_MIPS16_JMP
2114 The MIPS16 jump instruction.
2117 BFD_RELOC_MIPS16_GPREL
2119 MIPS16 GP relative reloc.
2124 High 16 bits of 32-bit value; simple reloc.
2129 High 16 bits of 32-bit value but the low 16 bits will be sign
2130 extended and added to form the final result. If the low 16
2131 bits form a negative number, we need to add one to the high value
2132 to compensate for the borrow when the low bits are added.
2140 BFD_RELOC_HI16_PCREL
2142 High 16 bits of 32-bit pc-relative value
2144 BFD_RELOC_HI16_S_PCREL
2146 High 16 bits of 32-bit pc-relative value, adjusted
2148 BFD_RELOC_LO16_PCREL
2150 Low 16 bits of pc-relative value
2153 BFD_RELOC_MIPS16_GOT16
2155 BFD_RELOC_MIPS16_CALL16
2157 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2158 16-bit immediate fields
2160 BFD_RELOC_MIPS16_HI16
2162 MIPS16 high 16 bits of 32-bit value.
2164 BFD_RELOC_MIPS16_HI16_S
2166 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2167 extended and added to form the final result. If the low 16
2168 bits form a negative number, we need to add one to the high value
2169 to compensate for the borrow when the low bits are added.
2171 BFD_RELOC_MIPS16_LO16
2176 BFD_RELOC_MIPS16_TLS_GD
2178 BFD_RELOC_MIPS16_TLS_LDM
2180 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2182 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2184 BFD_RELOC_MIPS16_TLS_GOTTPREL
2186 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2188 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2190 MIPS16 TLS relocations
2193 BFD_RELOC_MIPS_LITERAL
2195 BFD_RELOC_MICROMIPS_LITERAL
2197 Relocation against a MIPS literal section.
2200 BFD_RELOC_MICROMIPS_7_PCREL_S1
2202 BFD_RELOC_MICROMIPS_10_PCREL_S1
2204 BFD_RELOC_MICROMIPS_16_PCREL_S1
2206 microMIPS PC-relative relocations.
2209 BFD_RELOC_MIPS16_16_PCREL_S1
2211 MIPS16 PC-relative relocation.
2214 BFD_RELOC_MIPS_21_PCREL_S2
2216 BFD_RELOC_MIPS_26_PCREL_S2
2218 BFD_RELOC_MIPS_18_PCREL_S3
2220 BFD_RELOC_MIPS_19_PCREL_S2
2222 MIPS PC-relative relocations.
2225 BFD_RELOC_MICROMIPS_GPREL16
2227 BFD_RELOC_MICROMIPS_HI16
2229 BFD_RELOC_MICROMIPS_HI16_S
2231 BFD_RELOC_MICROMIPS_LO16
2233 microMIPS versions of generic BFD relocs.
2236 BFD_RELOC_MIPS_GOT16
2238 BFD_RELOC_MICROMIPS_GOT16
2240 BFD_RELOC_MIPS_CALL16
2242 BFD_RELOC_MICROMIPS_CALL16
2244 BFD_RELOC_MIPS_GOT_HI16
2246 BFD_RELOC_MICROMIPS_GOT_HI16
2248 BFD_RELOC_MIPS_GOT_LO16
2250 BFD_RELOC_MICROMIPS_GOT_LO16
2252 BFD_RELOC_MIPS_CALL_HI16
2254 BFD_RELOC_MICROMIPS_CALL_HI16
2256 BFD_RELOC_MIPS_CALL_LO16
2258 BFD_RELOC_MICROMIPS_CALL_LO16
2262 BFD_RELOC_MICROMIPS_SUB
2264 BFD_RELOC_MIPS_GOT_PAGE
2266 BFD_RELOC_MICROMIPS_GOT_PAGE
2268 BFD_RELOC_MIPS_GOT_OFST
2270 BFD_RELOC_MICROMIPS_GOT_OFST
2272 BFD_RELOC_MIPS_GOT_DISP
2274 BFD_RELOC_MICROMIPS_GOT_DISP
2276 BFD_RELOC_MIPS_SHIFT5
2278 BFD_RELOC_MIPS_SHIFT6
2280 BFD_RELOC_MIPS_INSERT_A
2282 BFD_RELOC_MIPS_INSERT_B
2284 BFD_RELOC_MIPS_DELETE
2286 BFD_RELOC_MIPS_HIGHEST
2288 BFD_RELOC_MICROMIPS_HIGHEST
2290 BFD_RELOC_MIPS_HIGHER
2292 BFD_RELOC_MICROMIPS_HIGHER
2294 BFD_RELOC_MIPS_SCN_DISP
2296 BFD_RELOC_MICROMIPS_SCN_DISP
2298 BFD_RELOC_MIPS_REL16
2300 BFD_RELOC_MIPS_RELGOT
2304 BFD_RELOC_MICROMIPS_JALR
2306 BFD_RELOC_MIPS_TLS_DTPMOD32
2308 BFD_RELOC_MIPS_TLS_DTPREL32
2310 BFD_RELOC_MIPS_TLS_DTPMOD64
2312 BFD_RELOC_MIPS_TLS_DTPREL64
2314 BFD_RELOC_MIPS_TLS_GD
2316 BFD_RELOC_MICROMIPS_TLS_GD
2318 BFD_RELOC_MIPS_TLS_LDM
2320 BFD_RELOC_MICROMIPS_TLS_LDM
2322 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2324 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2326 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2328 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2330 BFD_RELOC_MIPS_TLS_GOTTPREL
2332 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2334 BFD_RELOC_MIPS_TLS_TPREL32
2336 BFD_RELOC_MIPS_TLS_TPREL64
2338 BFD_RELOC_MIPS_TLS_TPREL_HI16
2340 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2342 BFD_RELOC_MIPS_TLS_TPREL_LO16
2344 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2348 MIPS ELF relocations.
2354 BFD_RELOC_MIPS_JUMP_SLOT
2356 MIPS ELF relocations (VxWorks and PLT extensions).
2360 BFD_RELOC_MOXIE_10_PCREL
2362 Moxie ELF relocations.
2374 BFD_RELOC_FT32_RELAX
2382 BFD_RELOC_FT32_DIFF32
2384 FT32 ELF relocations.
2388 BFD_RELOC_FRV_LABEL16
2390 BFD_RELOC_FRV_LABEL24
2396 BFD_RELOC_FRV_GPREL12
2398 BFD_RELOC_FRV_GPRELU12
2400 BFD_RELOC_FRV_GPREL32
2402 BFD_RELOC_FRV_GPRELHI
2404 BFD_RELOC_FRV_GPRELLO
2412 BFD_RELOC_FRV_FUNCDESC
2414 BFD_RELOC_FRV_FUNCDESC_GOT12
2416 BFD_RELOC_FRV_FUNCDESC_GOTHI
2418 BFD_RELOC_FRV_FUNCDESC_GOTLO
2420 BFD_RELOC_FRV_FUNCDESC_VALUE
2422 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2424 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2426 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2428 BFD_RELOC_FRV_GOTOFF12
2430 BFD_RELOC_FRV_GOTOFFHI
2432 BFD_RELOC_FRV_GOTOFFLO
2434 BFD_RELOC_FRV_GETTLSOFF
2436 BFD_RELOC_FRV_TLSDESC_VALUE
2438 BFD_RELOC_FRV_GOTTLSDESC12
2440 BFD_RELOC_FRV_GOTTLSDESCHI
2442 BFD_RELOC_FRV_GOTTLSDESCLO
2444 BFD_RELOC_FRV_TLSMOFF12
2446 BFD_RELOC_FRV_TLSMOFFHI
2448 BFD_RELOC_FRV_TLSMOFFLO
2450 BFD_RELOC_FRV_GOTTLSOFF12
2452 BFD_RELOC_FRV_GOTTLSOFFHI
2454 BFD_RELOC_FRV_GOTTLSOFFLO
2456 BFD_RELOC_FRV_TLSOFF
2458 BFD_RELOC_FRV_TLSDESC_RELAX
2460 BFD_RELOC_FRV_GETTLSOFF_RELAX
2462 BFD_RELOC_FRV_TLSOFF_RELAX
2464 BFD_RELOC_FRV_TLSMOFF
2466 Fujitsu Frv Relocations.
2470 BFD_RELOC_MN10300_GOTOFF24
2472 This is a 24bit GOT-relative reloc for the mn10300.
2474 BFD_RELOC_MN10300_GOT32
2476 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2479 BFD_RELOC_MN10300_GOT24
2481 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2484 BFD_RELOC_MN10300_GOT16
2486 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2489 BFD_RELOC_MN10300_COPY
2491 Copy symbol at runtime.
2493 BFD_RELOC_MN10300_GLOB_DAT
2497 BFD_RELOC_MN10300_JMP_SLOT
2501 BFD_RELOC_MN10300_RELATIVE
2503 Adjust by program base.
2505 BFD_RELOC_MN10300_SYM_DIFF
2507 Together with another reloc targeted at the same location,
2508 allows for a value that is the difference of two symbols
2509 in the same section.
2511 BFD_RELOC_MN10300_ALIGN
2513 The addend of this reloc is an alignment power that must
2514 be honoured at the offset's location, regardless of linker
2517 BFD_RELOC_MN10300_TLS_GD
2519 BFD_RELOC_MN10300_TLS_LD
2521 BFD_RELOC_MN10300_TLS_LDO
2523 BFD_RELOC_MN10300_TLS_GOTIE
2525 BFD_RELOC_MN10300_TLS_IE
2527 BFD_RELOC_MN10300_TLS_LE
2529 BFD_RELOC_MN10300_TLS_DTPMOD
2531 BFD_RELOC_MN10300_TLS_DTPOFF
2533 BFD_RELOC_MN10300_TLS_TPOFF
2535 Various TLS-related relocations.
2537 BFD_RELOC_MN10300_32_PCREL
2539 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2542 BFD_RELOC_MN10300_16_PCREL
2544 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2555 BFD_RELOC_386_GLOB_DAT
2557 BFD_RELOC_386_JUMP_SLOT
2559 BFD_RELOC_386_RELATIVE
2561 BFD_RELOC_386_GOTOFF
2565 BFD_RELOC_386_TLS_TPOFF
2567 BFD_RELOC_386_TLS_IE
2569 BFD_RELOC_386_TLS_GOTIE
2571 BFD_RELOC_386_TLS_LE
2573 BFD_RELOC_386_TLS_GD
2575 BFD_RELOC_386_TLS_LDM
2577 BFD_RELOC_386_TLS_LDO_32
2579 BFD_RELOC_386_TLS_IE_32
2581 BFD_RELOC_386_TLS_LE_32
2583 BFD_RELOC_386_TLS_DTPMOD32
2585 BFD_RELOC_386_TLS_DTPOFF32
2587 BFD_RELOC_386_TLS_TPOFF32
2589 BFD_RELOC_386_TLS_GOTDESC
2591 BFD_RELOC_386_TLS_DESC_CALL
2593 BFD_RELOC_386_TLS_DESC
2595 BFD_RELOC_386_IRELATIVE
2597 BFD_RELOC_386_GOT32X
2599 i386/elf relocations
2602 BFD_RELOC_X86_64_GOT32
2604 BFD_RELOC_X86_64_PLT32
2606 BFD_RELOC_X86_64_COPY
2608 BFD_RELOC_X86_64_GLOB_DAT
2610 BFD_RELOC_X86_64_JUMP_SLOT
2612 BFD_RELOC_X86_64_RELATIVE
2614 BFD_RELOC_X86_64_GOTPCREL
2616 BFD_RELOC_X86_64_32S
2618 BFD_RELOC_X86_64_DTPMOD64
2620 BFD_RELOC_X86_64_DTPOFF64
2622 BFD_RELOC_X86_64_TPOFF64
2624 BFD_RELOC_X86_64_TLSGD
2626 BFD_RELOC_X86_64_TLSLD
2628 BFD_RELOC_X86_64_DTPOFF32
2630 BFD_RELOC_X86_64_GOTTPOFF
2632 BFD_RELOC_X86_64_TPOFF32
2634 BFD_RELOC_X86_64_GOTOFF64
2636 BFD_RELOC_X86_64_GOTPC32
2638 BFD_RELOC_X86_64_GOT64
2640 BFD_RELOC_X86_64_GOTPCREL64
2642 BFD_RELOC_X86_64_GOTPC64
2644 BFD_RELOC_X86_64_GOTPLT64
2646 BFD_RELOC_X86_64_PLTOFF64
2648 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2650 BFD_RELOC_X86_64_TLSDESC_CALL
2652 BFD_RELOC_X86_64_TLSDESC
2654 BFD_RELOC_X86_64_IRELATIVE
2656 BFD_RELOC_X86_64_PC32_BND
2658 BFD_RELOC_X86_64_PLT32_BND
2660 BFD_RELOC_X86_64_GOTPCRELX
2662 BFD_RELOC_X86_64_REX_GOTPCRELX
2664 x86-64/elf relocations
2667 BFD_RELOC_NS32K_IMM_8
2669 BFD_RELOC_NS32K_IMM_16
2671 BFD_RELOC_NS32K_IMM_32
2673 BFD_RELOC_NS32K_IMM_8_PCREL
2675 BFD_RELOC_NS32K_IMM_16_PCREL
2677 BFD_RELOC_NS32K_IMM_32_PCREL
2679 BFD_RELOC_NS32K_DISP_8
2681 BFD_RELOC_NS32K_DISP_16
2683 BFD_RELOC_NS32K_DISP_32
2685 BFD_RELOC_NS32K_DISP_8_PCREL
2687 BFD_RELOC_NS32K_DISP_16_PCREL
2689 BFD_RELOC_NS32K_DISP_32_PCREL
2694 BFD_RELOC_PDP11_DISP_8_PCREL
2696 BFD_RELOC_PDP11_DISP_6_PCREL
2701 BFD_RELOC_PJ_CODE_HI16
2703 BFD_RELOC_PJ_CODE_LO16
2705 BFD_RELOC_PJ_CODE_DIR16
2707 BFD_RELOC_PJ_CODE_DIR32
2709 BFD_RELOC_PJ_CODE_REL16
2711 BFD_RELOC_PJ_CODE_REL32
2713 Picojava relocs. Not all of these appear in object files.
2724 BFD_RELOC_PPC_B16_BRTAKEN
2726 BFD_RELOC_PPC_B16_BRNTAKEN
2730 BFD_RELOC_PPC_BA16_BRTAKEN
2732 BFD_RELOC_PPC_BA16_BRNTAKEN
2736 BFD_RELOC_PPC_GLOB_DAT
2738 BFD_RELOC_PPC_JMP_SLOT
2740 BFD_RELOC_PPC_RELATIVE
2742 BFD_RELOC_PPC_LOCAL24PC
2744 BFD_RELOC_PPC_EMB_NADDR32
2746 BFD_RELOC_PPC_EMB_NADDR16
2748 BFD_RELOC_PPC_EMB_NADDR16_LO
2750 BFD_RELOC_PPC_EMB_NADDR16_HI
2752 BFD_RELOC_PPC_EMB_NADDR16_HA
2754 BFD_RELOC_PPC_EMB_SDAI16
2756 BFD_RELOC_PPC_EMB_SDA2I16
2758 BFD_RELOC_PPC_EMB_SDA2REL
2760 BFD_RELOC_PPC_EMB_SDA21
2762 BFD_RELOC_PPC_EMB_MRKREF
2764 BFD_RELOC_PPC_EMB_RELSEC16
2766 BFD_RELOC_PPC_EMB_RELST_LO
2768 BFD_RELOC_PPC_EMB_RELST_HI
2770 BFD_RELOC_PPC_EMB_RELST_HA
2772 BFD_RELOC_PPC_EMB_BIT_FLD
2774 BFD_RELOC_PPC_EMB_RELSDA
2776 BFD_RELOC_PPC_VLE_REL8
2778 BFD_RELOC_PPC_VLE_REL15
2780 BFD_RELOC_PPC_VLE_REL24
2782 BFD_RELOC_PPC_VLE_LO16A
2784 BFD_RELOC_PPC_VLE_LO16D
2786 BFD_RELOC_PPC_VLE_HI16A
2788 BFD_RELOC_PPC_VLE_HI16D
2790 BFD_RELOC_PPC_VLE_HA16A
2792 BFD_RELOC_PPC_VLE_HA16D
2794 BFD_RELOC_PPC_VLE_SDA21
2796 BFD_RELOC_PPC_VLE_SDA21_LO
2798 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2800 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2802 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2804 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2806 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2808 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2810 BFD_RELOC_PPC_16DX_HA
2812 BFD_RELOC_PPC_REL16DX_HA
2814 BFD_RELOC_PPC64_HIGHER
2816 BFD_RELOC_PPC64_HIGHER_S
2818 BFD_RELOC_PPC64_HIGHEST
2820 BFD_RELOC_PPC64_HIGHEST_S
2822 BFD_RELOC_PPC64_TOC16_LO
2824 BFD_RELOC_PPC64_TOC16_HI
2826 BFD_RELOC_PPC64_TOC16_HA
2830 BFD_RELOC_PPC64_PLTGOT16
2832 BFD_RELOC_PPC64_PLTGOT16_LO
2834 BFD_RELOC_PPC64_PLTGOT16_HI
2836 BFD_RELOC_PPC64_PLTGOT16_HA
2838 BFD_RELOC_PPC64_ADDR16_DS
2840 BFD_RELOC_PPC64_ADDR16_LO_DS
2842 BFD_RELOC_PPC64_GOT16_DS
2844 BFD_RELOC_PPC64_GOT16_LO_DS
2846 BFD_RELOC_PPC64_PLT16_LO_DS
2848 BFD_RELOC_PPC64_SECTOFF_DS
2850 BFD_RELOC_PPC64_SECTOFF_LO_DS
2852 BFD_RELOC_PPC64_TOC16_DS
2854 BFD_RELOC_PPC64_TOC16_LO_DS
2856 BFD_RELOC_PPC64_PLTGOT16_DS
2858 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2860 BFD_RELOC_PPC64_ADDR16_HIGH
2862 BFD_RELOC_PPC64_ADDR16_HIGHA
2864 BFD_RELOC_PPC64_REL16_HIGH
2866 BFD_RELOC_PPC64_REL16_HIGHA
2868 BFD_RELOC_PPC64_REL16_HIGHER
2870 BFD_RELOC_PPC64_REL16_HIGHERA
2872 BFD_RELOC_PPC64_REL16_HIGHEST
2874 BFD_RELOC_PPC64_REL16_HIGHESTA
2876 BFD_RELOC_PPC64_ADDR64_LOCAL
2878 BFD_RELOC_PPC64_ENTRY
2880 BFD_RELOC_PPC64_REL24_NOTOC
2884 BFD_RELOC_PPC64_D34_LO
2886 BFD_RELOC_PPC64_D34_HI30
2888 BFD_RELOC_PPC64_D34_HA30
2890 BFD_RELOC_PPC64_PCREL34
2892 BFD_RELOC_PPC64_GOT_PCREL34
2894 BFD_RELOC_PPC64_PLT_PCREL34
2896 BFD_RELOC_PPC64_ADDR16_HIGHER34
2898 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2900 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2902 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2904 BFD_RELOC_PPC64_REL16_HIGHER34
2906 BFD_RELOC_PPC64_REL16_HIGHERA34
2908 BFD_RELOC_PPC64_REL16_HIGHEST34
2910 BFD_RELOC_PPC64_REL16_HIGHESTA34
2914 BFD_RELOC_PPC64_PCREL28
2916 Power(rs6000) and PowerPC relocations.
2925 BFD_RELOC_PPC_DTPMOD
2927 BFD_RELOC_PPC_TPREL16
2929 BFD_RELOC_PPC_TPREL16_LO
2931 BFD_RELOC_PPC_TPREL16_HI
2933 BFD_RELOC_PPC_TPREL16_HA
2937 BFD_RELOC_PPC_DTPREL16
2939 BFD_RELOC_PPC_DTPREL16_LO
2941 BFD_RELOC_PPC_DTPREL16_HI
2943 BFD_RELOC_PPC_DTPREL16_HA
2945 BFD_RELOC_PPC_DTPREL
2947 BFD_RELOC_PPC_GOT_TLSGD16
2949 BFD_RELOC_PPC_GOT_TLSGD16_LO
2951 BFD_RELOC_PPC_GOT_TLSGD16_HI
2953 BFD_RELOC_PPC_GOT_TLSGD16_HA
2955 BFD_RELOC_PPC_GOT_TLSLD16
2957 BFD_RELOC_PPC_GOT_TLSLD16_LO
2959 BFD_RELOC_PPC_GOT_TLSLD16_HI
2961 BFD_RELOC_PPC_GOT_TLSLD16_HA
2963 BFD_RELOC_PPC_GOT_TPREL16
2965 BFD_RELOC_PPC_GOT_TPREL16_LO
2967 BFD_RELOC_PPC_GOT_TPREL16_HI
2969 BFD_RELOC_PPC_GOT_TPREL16_HA
2971 BFD_RELOC_PPC_GOT_DTPREL16
2973 BFD_RELOC_PPC_GOT_DTPREL16_LO
2975 BFD_RELOC_PPC_GOT_DTPREL16_HI
2977 BFD_RELOC_PPC_GOT_DTPREL16_HA
2979 BFD_RELOC_PPC64_TPREL16_DS
2981 BFD_RELOC_PPC64_TPREL16_LO_DS
2983 BFD_RELOC_PPC64_TPREL16_HIGH
2985 BFD_RELOC_PPC64_TPREL16_HIGHA
2987 BFD_RELOC_PPC64_TPREL16_HIGHER
2989 BFD_RELOC_PPC64_TPREL16_HIGHERA
2991 BFD_RELOC_PPC64_TPREL16_HIGHEST
2993 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2995 BFD_RELOC_PPC64_DTPREL16_DS
2997 BFD_RELOC_PPC64_DTPREL16_LO_DS
2999 BFD_RELOC_PPC64_DTPREL16_HIGH
3001 BFD_RELOC_PPC64_DTPREL16_HIGHA
3003 BFD_RELOC_PPC64_DTPREL16_HIGHER
3005 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3007 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3009 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3011 BFD_RELOC_PPC64_TPREL34
3013 BFD_RELOC_PPC64_DTPREL34
3015 BFD_RELOC_PPC64_GOT_TLSGD34
3017 BFD_RELOC_PPC64_GOT_TLSLD34
3019 BFD_RELOC_PPC64_GOT_TPREL34
3021 BFD_RELOC_PPC64_GOT_DTPREL34
3023 BFD_RELOC_PPC64_TLS_PCREL
3025 PowerPC and PowerPC64 thread-local storage relocations.
3030 IBM 370/390 relocations
3035 The type of reloc used to build a constructor table - at the moment
3036 probably a 32 bit wide absolute relocation, but the target can choose.
3037 It generally does map to one of the other relocation types.
3040 BFD_RELOC_ARM_PCREL_BRANCH
3042 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3043 not stored in the instruction.
3045 BFD_RELOC_ARM_PCREL_BLX
3047 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3048 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3049 field in the instruction.
3051 BFD_RELOC_THUMB_PCREL_BLX
3053 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3054 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3055 field in the instruction.
3057 BFD_RELOC_ARM_PCREL_CALL
3059 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3061 BFD_RELOC_ARM_PCREL_JUMP
3063 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3066 BFD_RELOC_THUMB_PCREL_BRANCH5
3068 ARM 5-bit pc-relative branch for Branch Future instructions.
3071 BFD_RELOC_THUMB_PCREL_BFCSEL
3073 ARM 6-bit pc-relative branch for BFCSEL instruction.
3076 BFD_RELOC_ARM_THUMB_BF17
3078 ARM 17-bit pc-relative branch for Branch Future instructions.
3081 BFD_RELOC_ARM_THUMB_BF13
3083 ARM 13-bit pc-relative branch for BFCSEL instruction.
3086 BFD_RELOC_ARM_THUMB_BF19
3088 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3091 BFD_RELOC_ARM_THUMB_LOOP12
3093 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3096 BFD_RELOC_THUMB_PCREL_BRANCH7
3098 BFD_RELOC_THUMB_PCREL_BRANCH9
3100 BFD_RELOC_THUMB_PCREL_BRANCH12
3102 BFD_RELOC_THUMB_PCREL_BRANCH20
3104 BFD_RELOC_THUMB_PCREL_BRANCH23
3106 BFD_RELOC_THUMB_PCREL_BRANCH25
3108 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3109 The lowest bit must be zero and is not stored in the instruction.
3110 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3111 "nn" one smaller in all cases. Note further that BRANCH23
3112 corresponds to R_ARM_THM_CALL.
3115 BFD_RELOC_ARM_OFFSET_IMM
3117 12-bit immediate offset, used in ARM-format ldr and str instructions.
3120 BFD_RELOC_ARM_THUMB_OFFSET
3122 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3125 BFD_RELOC_ARM_TARGET1
3127 Pc-relative or absolute relocation depending on target. Used for
3128 entries in .init_array sections.
3130 BFD_RELOC_ARM_ROSEGREL32
3132 Read-only segment base relative address.
3134 BFD_RELOC_ARM_SBREL32
3136 Data segment base relative address.
3138 BFD_RELOC_ARM_TARGET2
3140 This reloc is used for references to RTTI data from exception handling
3141 tables. The actual definition depends on the target. It may be a
3142 pc-relative or some form of GOT-indirect relocation.
3144 BFD_RELOC_ARM_PREL31
3146 31-bit PC relative address.
3152 BFD_RELOC_ARM_MOVW_PCREL
3154 BFD_RELOC_ARM_MOVT_PCREL
3156 BFD_RELOC_ARM_THUMB_MOVW
3158 BFD_RELOC_ARM_THUMB_MOVT
3160 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3162 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3164 Low and High halfword relocations for MOVW and MOVT instructions.
3167 BFD_RELOC_ARM_GOTFUNCDESC
3169 BFD_RELOC_ARM_GOTOFFFUNCDESC
3171 BFD_RELOC_ARM_FUNCDESC
3173 BFD_RELOC_ARM_FUNCDESC_VALUE
3175 BFD_RELOC_ARM_TLS_GD32_FDPIC
3177 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3179 BFD_RELOC_ARM_TLS_IE32_FDPIC
3181 ARM FDPIC specific relocations.
3184 BFD_RELOC_ARM_JUMP_SLOT
3186 BFD_RELOC_ARM_GLOB_DAT
3192 BFD_RELOC_ARM_RELATIVE
3194 BFD_RELOC_ARM_GOTOFF
3198 BFD_RELOC_ARM_GOT_PREL
3200 Relocations for setting up GOTs and PLTs for shared libraries.
3203 BFD_RELOC_ARM_TLS_GD32
3205 BFD_RELOC_ARM_TLS_LDO32
3207 BFD_RELOC_ARM_TLS_LDM32
3209 BFD_RELOC_ARM_TLS_DTPOFF32
3211 BFD_RELOC_ARM_TLS_DTPMOD32
3213 BFD_RELOC_ARM_TLS_TPOFF32
3215 BFD_RELOC_ARM_TLS_IE32
3217 BFD_RELOC_ARM_TLS_LE32
3219 BFD_RELOC_ARM_TLS_GOTDESC
3221 BFD_RELOC_ARM_TLS_CALL
3223 BFD_RELOC_ARM_THM_TLS_CALL
3225 BFD_RELOC_ARM_TLS_DESCSEQ
3227 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3229 BFD_RELOC_ARM_TLS_DESC
3231 ARM thread-local storage relocations.
3234 BFD_RELOC_ARM_ALU_PC_G0_NC
3236 BFD_RELOC_ARM_ALU_PC_G0
3238 BFD_RELOC_ARM_ALU_PC_G1_NC
3240 BFD_RELOC_ARM_ALU_PC_G1
3242 BFD_RELOC_ARM_ALU_PC_G2
3244 BFD_RELOC_ARM_LDR_PC_G0
3246 BFD_RELOC_ARM_LDR_PC_G1
3248 BFD_RELOC_ARM_LDR_PC_G2
3250 BFD_RELOC_ARM_LDRS_PC_G0
3252 BFD_RELOC_ARM_LDRS_PC_G1
3254 BFD_RELOC_ARM_LDRS_PC_G2
3256 BFD_RELOC_ARM_LDC_PC_G0
3258 BFD_RELOC_ARM_LDC_PC_G1
3260 BFD_RELOC_ARM_LDC_PC_G2
3262 BFD_RELOC_ARM_ALU_SB_G0_NC
3264 BFD_RELOC_ARM_ALU_SB_G0
3266 BFD_RELOC_ARM_ALU_SB_G1_NC
3268 BFD_RELOC_ARM_ALU_SB_G1
3270 BFD_RELOC_ARM_ALU_SB_G2
3272 BFD_RELOC_ARM_LDR_SB_G0
3274 BFD_RELOC_ARM_LDR_SB_G1
3276 BFD_RELOC_ARM_LDR_SB_G2
3278 BFD_RELOC_ARM_LDRS_SB_G0
3280 BFD_RELOC_ARM_LDRS_SB_G1
3282 BFD_RELOC_ARM_LDRS_SB_G2
3284 BFD_RELOC_ARM_LDC_SB_G0
3286 BFD_RELOC_ARM_LDC_SB_G1
3288 BFD_RELOC_ARM_LDC_SB_G2
3290 ARM group relocations.
3295 Annotation of BX instructions.
3298 BFD_RELOC_ARM_IRELATIVE
3300 ARM support for STT_GNU_IFUNC.
3303 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3305 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3307 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3309 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3311 Thumb1 relocations to support execute-only code.
3314 BFD_RELOC_ARM_IMMEDIATE
3316 BFD_RELOC_ARM_ADRL_IMMEDIATE
3318 BFD_RELOC_ARM_T32_IMMEDIATE
3320 BFD_RELOC_ARM_T32_ADD_IMM
3322 BFD_RELOC_ARM_T32_IMM12
3324 BFD_RELOC_ARM_T32_ADD_PC12
3326 BFD_RELOC_ARM_SHIFT_IMM
3336 BFD_RELOC_ARM_CP_OFF_IMM
3338 BFD_RELOC_ARM_CP_OFF_IMM_S2
3340 BFD_RELOC_ARM_T32_CP_OFF_IMM
3342 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3344 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3346 BFD_RELOC_ARM_ADR_IMM
3348 BFD_RELOC_ARM_LDR_IMM
3350 BFD_RELOC_ARM_LITERAL
3352 BFD_RELOC_ARM_IN_POOL
3354 BFD_RELOC_ARM_OFFSET_IMM8
3356 BFD_RELOC_ARM_T32_OFFSET_U8
3358 BFD_RELOC_ARM_T32_OFFSET_IMM
3360 BFD_RELOC_ARM_HWLITERAL
3362 BFD_RELOC_ARM_THUMB_ADD
3364 BFD_RELOC_ARM_THUMB_IMM
3366 BFD_RELOC_ARM_THUMB_SHIFT
3368 These relocs are only used within the ARM assembler. They are not
3369 (at present) written to any object files.
3372 BFD_RELOC_SH_PCDISP8BY2
3374 BFD_RELOC_SH_PCDISP12BY2
3382 BFD_RELOC_SH_DISP12BY2
3384 BFD_RELOC_SH_DISP12BY4
3386 BFD_RELOC_SH_DISP12BY8
3390 BFD_RELOC_SH_DISP20BY8
3394 BFD_RELOC_SH_IMM4BY2
3396 BFD_RELOC_SH_IMM4BY4
3400 BFD_RELOC_SH_IMM8BY2
3402 BFD_RELOC_SH_IMM8BY4
3404 BFD_RELOC_SH_PCRELIMM8BY2
3406 BFD_RELOC_SH_PCRELIMM8BY4
3408 BFD_RELOC_SH_SWITCH16
3410 BFD_RELOC_SH_SWITCH32
3424 BFD_RELOC_SH_LOOP_START
3426 BFD_RELOC_SH_LOOP_END
3430 BFD_RELOC_SH_GLOB_DAT
3432 BFD_RELOC_SH_JMP_SLOT
3434 BFD_RELOC_SH_RELATIVE
3438 BFD_RELOC_SH_GOT_LOW16
3440 BFD_RELOC_SH_GOT_MEDLOW16
3442 BFD_RELOC_SH_GOT_MEDHI16
3444 BFD_RELOC_SH_GOT_HI16
3446 BFD_RELOC_SH_GOTPLT_LOW16
3448 BFD_RELOC_SH_GOTPLT_MEDLOW16
3450 BFD_RELOC_SH_GOTPLT_MEDHI16
3452 BFD_RELOC_SH_GOTPLT_HI16
3454 BFD_RELOC_SH_PLT_LOW16
3456 BFD_RELOC_SH_PLT_MEDLOW16
3458 BFD_RELOC_SH_PLT_MEDHI16
3460 BFD_RELOC_SH_PLT_HI16
3462 BFD_RELOC_SH_GOTOFF_LOW16
3464 BFD_RELOC_SH_GOTOFF_MEDLOW16
3466 BFD_RELOC_SH_GOTOFF_MEDHI16
3468 BFD_RELOC_SH_GOTOFF_HI16
3470 BFD_RELOC_SH_GOTPC_LOW16
3472 BFD_RELOC_SH_GOTPC_MEDLOW16
3474 BFD_RELOC_SH_GOTPC_MEDHI16
3476 BFD_RELOC_SH_GOTPC_HI16
3480 BFD_RELOC_SH_GLOB_DAT64
3482 BFD_RELOC_SH_JMP_SLOT64
3484 BFD_RELOC_SH_RELATIVE64
3486 BFD_RELOC_SH_GOT10BY4
3488 BFD_RELOC_SH_GOT10BY8
3490 BFD_RELOC_SH_GOTPLT10BY4
3492 BFD_RELOC_SH_GOTPLT10BY8
3494 BFD_RELOC_SH_GOTPLT32
3496 BFD_RELOC_SH_SHMEDIA_CODE
3502 BFD_RELOC_SH_IMMS6BY32
3508 BFD_RELOC_SH_IMMS10BY2
3510 BFD_RELOC_SH_IMMS10BY4
3512 BFD_RELOC_SH_IMMS10BY8
3518 BFD_RELOC_SH_IMM_LOW16
3520 BFD_RELOC_SH_IMM_LOW16_PCREL
3522 BFD_RELOC_SH_IMM_MEDLOW16
3524 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3526 BFD_RELOC_SH_IMM_MEDHI16
3528 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3530 BFD_RELOC_SH_IMM_HI16
3532 BFD_RELOC_SH_IMM_HI16_PCREL
3536 BFD_RELOC_SH_TLS_GD_32
3538 BFD_RELOC_SH_TLS_LD_32
3540 BFD_RELOC_SH_TLS_LDO_32
3542 BFD_RELOC_SH_TLS_IE_32
3544 BFD_RELOC_SH_TLS_LE_32
3546 BFD_RELOC_SH_TLS_DTPMOD32
3548 BFD_RELOC_SH_TLS_DTPOFF32
3550 BFD_RELOC_SH_TLS_TPOFF32
3554 BFD_RELOC_SH_GOTOFF20
3556 BFD_RELOC_SH_GOTFUNCDESC
3558 BFD_RELOC_SH_GOTFUNCDESC20
3560 BFD_RELOC_SH_GOTOFFFUNCDESC
3562 BFD_RELOC_SH_GOTOFFFUNCDESC20
3564 BFD_RELOC_SH_FUNCDESC
3566 Renesas / SuperH SH relocs. Not all of these appear in object files.
3589 BFD_RELOC_ARC_SECTOFF
3591 BFD_RELOC_ARC_S21H_PCREL
3593 BFD_RELOC_ARC_S21W_PCREL
3595 BFD_RELOC_ARC_S25H_PCREL
3597 BFD_RELOC_ARC_S25W_PCREL
3601 BFD_RELOC_ARC_SDA_LDST
3603 BFD_RELOC_ARC_SDA_LDST1
3605 BFD_RELOC_ARC_SDA_LDST2
3607 BFD_RELOC_ARC_SDA16_LD
3609 BFD_RELOC_ARC_SDA16_LD1
3611 BFD_RELOC_ARC_SDA16_LD2
3613 BFD_RELOC_ARC_S13_PCREL
3619 BFD_RELOC_ARC_32_ME_S
3621 BFD_RELOC_ARC_N32_ME
3623 BFD_RELOC_ARC_SECTOFF_ME
3625 BFD_RELOC_ARC_SDA32_ME
3629 BFD_RELOC_AC_SECTOFF_U8
3631 BFD_RELOC_AC_SECTOFF_U8_1
3633 BFD_RELOC_AC_SECTOFF_U8_2
3635 BFD_RELOC_AC_SECTOFF_S9
3637 BFD_RELOC_AC_SECTOFF_S9_1
3639 BFD_RELOC_AC_SECTOFF_S9_2
3641 BFD_RELOC_ARC_SECTOFF_ME_1
3643 BFD_RELOC_ARC_SECTOFF_ME_2
3645 BFD_RELOC_ARC_SECTOFF_1
3647 BFD_RELOC_ARC_SECTOFF_2
3649 BFD_RELOC_ARC_SDA_12
3651 BFD_RELOC_ARC_SDA16_ST2
3653 BFD_RELOC_ARC_32_PCREL
3659 BFD_RELOC_ARC_GOTPC32
3665 BFD_RELOC_ARC_GLOB_DAT
3667 BFD_RELOC_ARC_JMP_SLOT
3669 BFD_RELOC_ARC_RELATIVE
3671 BFD_RELOC_ARC_GOTOFF
3675 BFD_RELOC_ARC_S21W_PCREL_PLT
3677 BFD_RELOC_ARC_S25H_PCREL_PLT
3679 BFD_RELOC_ARC_TLS_DTPMOD
3681 BFD_RELOC_ARC_TLS_TPOFF
3683 BFD_RELOC_ARC_TLS_GD_GOT
3685 BFD_RELOC_ARC_TLS_GD_LD
3687 BFD_RELOC_ARC_TLS_GD_CALL
3689 BFD_RELOC_ARC_TLS_IE_GOT
3691 BFD_RELOC_ARC_TLS_DTPOFF
3693 BFD_RELOC_ARC_TLS_DTPOFF_S9
3695 BFD_RELOC_ARC_TLS_LE_S9
3697 BFD_RELOC_ARC_TLS_LE_32
3699 BFD_RELOC_ARC_S25W_PCREL_PLT
3701 BFD_RELOC_ARC_S21H_PCREL_PLT
3703 BFD_RELOC_ARC_NPS_CMEM16
3705 BFD_RELOC_ARC_JLI_SECTOFF
3710 BFD_RELOC_BFIN_16_IMM
3712 ADI Blackfin 16 bit immediate absolute reloc.
3714 BFD_RELOC_BFIN_16_HIGH
3716 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3718 BFD_RELOC_BFIN_4_PCREL
3720 ADI Blackfin 'a' part of LSETUP.
3722 BFD_RELOC_BFIN_5_PCREL
3726 BFD_RELOC_BFIN_16_LOW
3728 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3730 BFD_RELOC_BFIN_10_PCREL
3734 BFD_RELOC_BFIN_11_PCREL
3736 ADI Blackfin 'b' part of LSETUP.
3738 BFD_RELOC_BFIN_12_PCREL_JUMP
3742 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3744 ADI Blackfin Short jump, pcrel.
3746 BFD_RELOC_BFIN_24_PCREL_CALL_X
3748 ADI Blackfin Call.x not implemented.
3750 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3752 ADI Blackfin Long Jump pcrel.
3754 BFD_RELOC_BFIN_GOT17M4
3756 BFD_RELOC_BFIN_GOTHI
3758 BFD_RELOC_BFIN_GOTLO
3760 BFD_RELOC_BFIN_FUNCDESC
3762 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3764 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3766 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3768 BFD_RELOC_BFIN_FUNCDESC_VALUE
3770 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3772 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3774 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3776 BFD_RELOC_BFIN_GOTOFF17M4
3778 BFD_RELOC_BFIN_GOTOFFHI
3780 BFD_RELOC_BFIN_GOTOFFLO
3782 ADI Blackfin FD-PIC relocations.
3786 ADI Blackfin GOT relocation.
3788 BFD_RELOC_BFIN_PLTPC
3790 ADI Blackfin PLTPC relocation.
3792 BFD_ARELOC_BFIN_PUSH
3794 ADI Blackfin arithmetic relocation.
3796 BFD_ARELOC_BFIN_CONST
3798 ADI Blackfin arithmetic relocation.
3802 ADI Blackfin arithmetic relocation.
3806 ADI Blackfin arithmetic relocation.
3808 BFD_ARELOC_BFIN_MULT
3810 ADI Blackfin arithmetic relocation.
3814 ADI Blackfin arithmetic relocation.
3818 ADI Blackfin arithmetic relocation.
3820 BFD_ARELOC_BFIN_LSHIFT
3822 ADI Blackfin arithmetic relocation.
3824 BFD_ARELOC_BFIN_RSHIFT
3826 ADI Blackfin arithmetic relocation.
3830 ADI Blackfin arithmetic relocation.
3834 ADI Blackfin arithmetic relocation.
3838 ADI Blackfin arithmetic relocation.
3840 BFD_ARELOC_BFIN_LAND
3842 ADI Blackfin arithmetic relocation.
3846 ADI Blackfin arithmetic relocation.
3850 ADI Blackfin arithmetic relocation.
3854 ADI Blackfin arithmetic relocation.
3856 BFD_ARELOC_BFIN_COMP
3858 ADI Blackfin arithmetic relocation.
3860 BFD_ARELOC_BFIN_PAGE
3862 ADI Blackfin arithmetic relocation.
3864 BFD_ARELOC_BFIN_HWPAGE
3866 ADI Blackfin arithmetic relocation.
3868 BFD_ARELOC_BFIN_ADDR
3870 ADI Blackfin arithmetic relocation.
3873 BFD_RELOC_D10V_10_PCREL_R
3875 Mitsubishi D10V relocs.
3876 This is a 10-bit reloc with the right 2 bits
3879 BFD_RELOC_D10V_10_PCREL_L
3881 Mitsubishi D10V relocs.
3882 This is a 10-bit reloc with the right 2 bits
3883 assumed to be 0. This is the same as the previous reloc
3884 except it is in the left container, i.e.,
3885 shifted left 15 bits.
3889 This is an 18-bit reloc with the right 2 bits
3892 BFD_RELOC_D10V_18_PCREL
3894 This is an 18-bit reloc with the right 2 bits
3900 Mitsubishi D30V relocs.
3901 This is a 6-bit absolute reloc.
3903 BFD_RELOC_D30V_9_PCREL
3905 This is a 6-bit pc-relative reloc with
3906 the right 3 bits assumed to be 0.
3908 BFD_RELOC_D30V_9_PCREL_R
3910 This is a 6-bit pc-relative reloc with
3911 the right 3 bits assumed to be 0. Same
3912 as the previous reloc but on the right side
3917 This is a 12-bit absolute reloc with the
3918 right 3 bitsassumed to be 0.
3920 BFD_RELOC_D30V_15_PCREL
3922 This is a 12-bit pc-relative reloc with
3923 the right 3 bits assumed to be 0.
3925 BFD_RELOC_D30V_15_PCREL_R
3927 This is a 12-bit pc-relative reloc with
3928 the right 3 bits assumed to be 0. Same
3929 as the previous reloc but on the right side
3934 This is an 18-bit absolute reloc with
3935 the right 3 bits assumed to be 0.
3937 BFD_RELOC_D30V_21_PCREL
3939 This is an 18-bit pc-relative reloc with
3940 the right 3 bits assumed to be 0.
3942 BFD_RELOC_D30V_21_PCREL_R
3944 This is an 18-bit pc-relative reloc with
3945 the right 3 bits assumed to be 0. Same
3946 as the previous reloc but on the right side
3951 This is a 32-bit absolute reloc.
3953 BFD_RELOC_D30V_32_PCREL
3955 This is a 32-bit pc-relative reloc.
3958 BFD_RELOC_DLX_HI16_S
3973 BFD_RELOC_M32C_RL_JUMP
3975 BFD_RELOC_M32C_RL_1ADDR
3977 BFD_RELOC_M32C_RL_2ADDR
3979 Renesas M16C/M32C Relocations.
3984 Renesas M32R (formerly Mitsubishi M32R) relocs.
3985 This is a 24 bit absolute address.
3987 BFD_RELOC_M32R_10_PCREL
3989 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3991 BFD_RELOC_M32R_18_PCREL
3993 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3995 BFD_RELOC_M32R_26_PCREL
3997 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3999 BFD_RELOC_M32R_HI16_ULO
4001 This is a 16-bit reloc containing the high 16 bits of an address
4002 used when the lower 16 bits are treated as unsigned.
4004 BFD_RELOC_M32R_HI16_SLO
4006 This is a 16-bit reloc containing the high 16 bits of an address
4007 used when the lower 16 bits are treated as signed.
4011 This is a 16-bit reloc containing the lower 16 bits of an address.
4013 BFD_RELOC_M32R_SDA16
4015 This is a 16-bit reloc containing the small data area offset for use in
4016 add3, load, and store instructions.
4018 BFD_RELOC_M32R_GOT24
4020 BFD_RELOC_M32R_26_PLTREL
4024 BFD_RELOC_M32R_GLOB_DAT
4026 BFD_RELOC_M32R_JMP_SLOT
4028 BFD_RELOC_M32R_RELATIVE
4030 BFD_RELOC_M32R_GOTOFF
4032 BFD_RELOC_M32R_GOTOFF_HI_ULO
4034 BFD_RELOC_M32R_GOTOFF_HI_SLO
4036 BFD_RELOC_M32R_GOTOFF_LO
4038 BFD_RELOC_M32R_GOTPC24
4040 BFD_RELOC_M32R_GOT16_HI_ULO
4042 BFD_RELOC_M32R_GOT16_HI_SLO
4044 BFD_RELOC_M32R_GOT16_LO
4046 BFD_RELOC_M32R_GOTPC_HI_ULO
4048 BFD_RELOC_M32R_GOTPC_HI_SLO
4050 BFD_RELOC_M32R_GOTPC_LO
4059 This is a 20 bit absolute address.
4061 BFD_RELOC_NDS32_9_PCREL
4063 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4065 BFD_RELOC_NDS32_WORD_9_PCREL
4067 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4069 BFD_RELOC_NDS32_15_PCREL
4071 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4073 BFD_RELOC_NDS32_17_PCREL
4075 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4077 BFD_RELOC_NDS32_25_PCREL
4079 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4081 BFD_RELOC_NDS32_HI20
4083 This is a 20-bit reloc containing the high 20 bits of an address
4084 used with the lower 12 bits
4086 BFD_RELOC_NDS32_LO12S3
4088 This is a 12-bit reloc containing the lower 12 bits of an address
4089 then shift right by 3. This is used with ldi,sdi...
4091 BFD_RELOC_NDS32_LO12S2
4093 This is a 12-bit reloc containing the lower 12 bits of an address
4094 then shift left by 2. This is used with lwi,swi...
4096 BFD_RELOC_NDS32_LO12S1
4098 This is a 12-bit reloc containing the lower 12 bits of an address
4099 then shift left by 1. This is used with lhi,shi...
4101 BFD_RELOC_NDS32_LO12S0
4103 This is a 12-bit reloc containing the lower 12 bits of an address
4104 then shift left by 0. This is used with lbisbi...
4106 BFD_RELOC_NDS32_LO12S0_ORI
4108 This is a 12-bit reloc containing the lower 12 bits of an address
4109 then shift left by 0. This is only used with branch relaxations
4111 BFD_RELOC_NDS32_SDA15S3
4113 This is a 15-bit reloc containing the small data area 18-bit signed offset
4114 and shift left by 3 for use in ldi, sdi...
4116 BFD_RELOC_NDS32_SDA15S2
4118 This is a 15-bit reloc containing the small data area 17-bit signed offset
4119 and shift left by 2 for use in lwi, swi...
4121 BFD_RELOC_NDS32_SDA15S1
4123 This is a 15-bit reloc containing the small data area 16-bit signed offset
4124 and shift left by 1 for use in lhi, shi...
4126 BFD_RELOC_NDS32_SDA15S0
4128 This is a 15-bit reloc containing the small data area 15-bit signed offset
4129 and shift left by 0 for use in lbi, sbi...
4131 BFD_RELOC_NDS32_SDA16S3
4133 This is a 16-bit reloc containing the small data area 16-bit signed offset
4136 BFD_RELOC_NDS32_SDA17S2
4138 This is a 17-bit reloc containing the small data area 17-bit signed offset
4139 and shift left by 2 for use in lwi.gp, swi.gp...
4141 BFD_RELOC_NDS32_SDA18S1
4143 This is a 18-bit reloc containing the small data area 18-bit signed offset
4144 and shift left by 1 for use in lhi.gp, shi.gp...
4146 BFD_RELOC_NDS32_SDA19S0
4148 This is a 19-bit reloc containing the small data area 19-bit signed offset
4149 and shift left by 0 for use in lbi.gp, sbi.gp...
4151 BFD_RELOC_NDS32_GOT20
4153 BFD_RELOC_NDS32_9_PLTREL
4155 BFD_RELOC_NDS32_25_PLTREL
4157 BFD_RELOC_NDS32_COPY
4159 BFD_RELOC_NDS32_GLOB_DAT
4161 BFD_RELOC_NDS32_JMP_SLOT
4163 BFD_RELOC_NDS32_RELATIVE
4165 BFD_RELOC_NDS32_GOTOFF
4167 BFD_RELOC_NDS32_GOTOFF_HI20
4169 BFD_RELOC_NDS32_GOTOFF_LO12
4171 BFD_RELOC_NDS32_GOTPC20
4173 BFD_RELOC_NDS32_GOT_HI20
4175 BFD_RELOC_NDS32_GOT_LO12
4177 BFD_RELOC_NDS32_GOTPC_HI20
4179 BFD_RELOC_NDS32_GOTPC_LO12
4183 BFD_RELOC_NDS32_INSN16
4185 BFD_RELOC_NDS32_LABEL
4187 BFD_RELOC_NDS32_LONGCALL1
4189 BFD_RELOC_NDS32_LONGCALL2
4191 BFD_RELOC_NDS32_LONGCALL3
4193 BFD_RELOC_NDS32_LONGJUMP1
4195 BFD_RELOC_NDS32_LONGJUMP2
4197 BFD_RELOC_NDS32_LONGJUMP3
4199 BFD_RELOC_NDS32_LOADSTORE
4201 BFD_RELOC_NDS32_9_FIXED
4203 BFD_RELOC_NDS32_15_FIXED
4205 BFD_RELOC_NDS32_17_FIXED
4207 BFD_RELOC_NDS32_25_FIXED
4209 BFD_RELOC_NDS32_LONGCALL4
4211 BFD_RELOC_NDS32_LONGCALL5
4213 BFD_RELOC_NDS32_LONGCALL6
4215 BFD_RELOC_NDS32_LONGJUMP4
4217 BFD_RELOC_NDS32_LONGJUMP5
4219 BFD_RELOC_NDS32_LONGJUMP6
4221 BFD_RELOC_NDS32_LONGJUMP7
4225 BFD_RELOC_NDS32_PLTREL_HI20
4227 BFD_RELOC_NDS32_PLTREL_LO12
4229 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4231 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4235 BFD_RELOC_NDS32_SDA12S2_DP
4237 BFD_RELOC_NDS32_SDA12S2_SP
4239 BFD_RELOC_NDS32_LO12S2_DP
4241 BFD_RELOC_NDS32_LO12S2_SP
4245 BFD_RELOC_NDS32_DWARF2_OP1
4247 BFD_RELOC_NDS32_DWARF2_OP2
4249 BFD_RELOC_NDS32_DWARF2_LEB
4251 for dwarf2 debug_line.
4253 BFD_RELOC_NDS32_UPDATE_TA
4255 for eliminate 16-bit instructions
4257 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4259 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4261 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4263 BFD_RELOC_NDS32_GOT_LO15
4265 BFD_RELOC_NDS32_GOT_LO19
4267 BFD_RELOC_NDS32_GOTOFF_LO15
4269 BFD_RELOC_NDS32_GOTOFF_LO19
4271 BFD_RELOC_NDS32_GOT15S2
4273 BFD_RELOC_NDS32_GOT17S2
4275 for PIC object relaxation
4280 This is a 5 bit absolute address.
4282 BFD_RELOC_NDS32_10_UPCREL
4284 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4286 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4288 If fp were omitted, fp can used as another gp.
4290 BFD_RELOC_NDS32_RELAX_ENTRY
4292 BFD_RELOC_NDS32_GOT_SUFF
4294 BFD_RELOC_NDS32_GOTOFF_SUFF
4296 BFD_RELOC_NDS32_PLT_GOT_SUFF
4298 BFD_RELOC_NDS32_MULCALL_SUFF
4302 BFD_RELOC_NDS32_PTR_COUNT
4304 BFD_RELOC_NDS32_PTR_RESOLVED
4306 BFD_RELOC_NDS32_PLTBLOCK
4308 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4310 BFD_RELOC_NDS32_RELAX_REGION_END
4312 BFD_RELOC_NDS32_MINUEND
4314 BFD_RELOC_NDS32_SUBTRAHEND
4316 BFD_RELOC_NDS32_DIFF8
4318 BFD_RELOC_NDS32_DIFF16
4320 BFD_RELOC_NDS32_DIFF32
4322 BFD_RELOC_NDS32_DIFF_ULEB128
4324 BFD_RELOC_NDS32_EMPTY
4326 relaxation relative relocation types
4328 BFD_RELOC_NDS32_25_ABS
4330 This is a 25 bit absolute address.
4332 BFD_RELOC_NDS32_DATA
4334 BFD_RELOC_NDS32_TRAN
4336 BFD_RELOC_NDS32_17IFC_PCREL
4338 BFD_RELOC_NDS32_10IFCU_PCREL
4340 For ex9 and ifc using.
4342 BFD_RELOC_NDS32_TPOFF
4344 BFD_RELOC_NDS32_GOTTPOFF
4346 BFD_RELOC_NDS32_TLS_LE_HI20
4348 BFD_RELOC_NDS32_TLS_LE_LO12
4350 BFD_RELOC_NDS32_TLS_LE_20
4352 BFD_RELOC_NDS32_TLS_LE_15S0
4354 BFD_RELOC_NDS32_TLS_LE_15S1
4356 BFD_RELOC_NDS32_TLS_LE_15S2
4358 BFD_RELOC_NDS32_TLS_LE_ADD
4360 BFD_RELOC_NDS32_TLS_LE_LS
4362 BFD_RELOC_NDS32_TLS_IE_HI20
4364 BFD_RELOC_NDS32_TLS_IE_LO12
4366 BFD_RELOC_NDS32_TLS_IE_LO12S2
4368 BFD_RELOC_NDS32_TLS_IEGP_HI20
4370 BFD_RELOC_NDS32_TLS_IEGP_LO12
4372 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4374 BFD_RELOC_NDS32_TLS_IEGP_LW
4376 BFD_RELOC_NDS32_TLS_DESC
4378 BFD_RELOC_NDS32_TLS_DESC_HI20
4380 BFD_RELOC_NDS32_TLS_DESC_LO12
4382 BFD_RELOC_NDS32_TLS_DESC_20
4384 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4386 BFD_RELOC_NDS32_TLS_DESC_ADD
4388 BFD_RELOC_NDS32_TLS_DESC_FUNC
4390 BFD_RELOC_NDS32_TLS_DESC_CALL
4392 BFD_RELOC_NDS32_TLS_DESC_MEM
4394 BFD_RELOC_NDS32_REMOVE
4396 BFD_RELOC_NDS32_GROUP
4402 For floating load store relaxation.
4406 BFD_RELOC_V850_9_PCREL
4408 This is a 9-bit reloc
4410 BFD_RELOC_V850_22_PCREL
4412 This is a 22-bit reloc
4415 BFD_RELOC_V850_SDA_16_16_OFFSET
4417 This is a 16 bit offset from the short data area pointer.
4419 BFD_RELOC_V850_SDA_15_16_OFFSET
4421 This is a 16 bit offset (of which only 15 bits are used) from the
4422 short data area pointer.
4424 BFD_RELOC_V850_ZDA_16_16_OFFSET
4426 This is a 16 bit offset from the zero data area pointer.
4428 BFD_RELOC_V850_ZDA_15_16_OFFSET
4430 This is a 16 bit offset (of which only 15 bits are used) from the
4431 zero data area pointer.
4433 BFD_RELOC_V850_TDA_6_8_OFFSET
4435 This is an 8 bit offset (of which only 6 bits are used) from the
4436 tiny data area pointer.
4438 BFD_RELOC_V850_TDA_7_8_OFFSET
4440 This is an 8bit offset (of which only 7 bits are used) from the tiny
4443 BFD_RELOC_V850_TDA_7_7_OFFSET
4445 This is a 7 bit offset from the tiny data area pointer.
4447 BFD_RELOC_V850_TDA_16_16_OFFSET
4449 This is a 16 bit offset from the tiny data area pointer.
4452 BFD_RELOC_V850_TDA_4_5_OFFSET
4454 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4457 BFD_RELOC_V850_TDA_4_4_OFFSET
4459 This is a 4 bit offset from the tiny data area pointer.
4461 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4463 This is a 16 bit offset from the short data area pointer, with the
4464 bits placed non-contiguously in the instruction.
4466 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4468 This is a 16 bit offset from the zero data area pointer, with the
4469 bits placed non-contiguously in the instruction.
4471 BFD_RELOC_V850_CALLT_6_7_OFFSET
4473 This is a 6 bit offset from the call table base pointer.
4475 BFD_RELOC_V850_CALLT_16_16_OFFSET
4477 This is a 16 bit offset from the call table base pointer.
4479 BFD_RELOC_V850_LONGCALL
4481 Used for relaxing indirect function calls.
4483 BFD_RELOC_V850_LONGJUMP
4485 Used for relaxing indirect jumps.
4487 BFD_RELOC_V850_ALIGN
4489 Used to maintain alignment whilst relaxing.
4491 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4493 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4496 BFD_RELOC_V850_16_PCREL
4498 This is a 16-bit reloc.
4500 BFD_RELOC_V850_17_PCREL
4502 This is a 17-bit reloc.
4506 This is a 23-bit reloc.
4508 BFD_RELOC_V850_32_PCREL
4510 This is a 32-bit reloc.
4512 BFD_RELOC_V850_32_ABS
4514 This is a 32-bit reloc.
4516 BFD_RELOC_V850_16_SPLIT_OFFSET
4518 This is a 16-bit reloc.
4520 BFD_RELOC_V850_16_S1
4522 This is a 16-bit reloc.
4524 BFD_RELOC_V850_LO16_S1
4526 Low 16 bits. 16 bit shifted by 1.
4528 BFD_RELOC_V850_CALLT_15_16_OFFSET
4530 This is a 16 bit offset from the call table base pointer.
4532 BFD_RELOC_V850_32_GOTPCREL
4536 BFD_RELOC_V850_16_GOT
4540 BFD_RELOC_V850_32_GOT
4544 BFD_RELOC_V850_22_PLT_PCREL
4548 BFD_RELOC_V850_32_PLT_PCREL
4556 BFD_RELOC_V850_GLOB_DAT
4560 BFD_RELOC_V850_JMP_SLOT
4564 BFD_RELOC_V850_RELATIVE
4568 BFD_RELOC_V850_16_GOTOFF
4572 BFD_RELOC_V850_32_GOTOFF
4587 This is a 8bit DP reloc for the tms320c30, where the most
4588 significant 8 bits of a 24 bit word are placed into the least
4589 significant 8 bits of the opcode.
4592 BFD_RELOC_TIC54X_PARTLS7
4594 This is a 7bit reloc for the tms320c54x, where the least
4595 significant 7 bits of a 16 bit word are placed into the least
4596 significant 7 bits of the opcode.
4599 BFD_RELOC_TIC54X_PARTMS9
4601 This is a 9bit DP reloc for the tms320c54x, where the most
4602 significant 9 bits of a 16 bit word are placed into the least
4603 significant 9 bits of the opcode.
4608 This is an extended address 23-bit reloc for the tms320c54x.
4611 BFD_RELOC_TIC54X_16_OF_23
4613 This is a 16-bit reloc for the tms320c54x, where the least
4614 significant 16 bits of a 23-bit extended address are placed into
4618 BFD_RELOC_TIC54X_MS7_OF_23
4620 This is a reloc for the tms320c54x, where the most
4621 significant 7 bits of a 23-bit extended address are placed into
4625 BFD_RELOC_C6000_PCR_S21
4627 BFD_RELOC_C6000_PCR_S12
4629 BFD_RELOC_C6000_PCR_S10
4631 BFD_RELOC_C6000_PCR_S7
4633 BFD_RELOC_C6000_ABS_S16
4635 BFD_RELOC_C6000_ABS_L16
4637 BFD_RELOC_C6000_ABS_H16
4639 BFD_RELOC_C6000_SBR_U15_B
4641 BFD_RELOC_C6000_SBR_U15_H
4643 BFD_RELOC_C6000_SBR_U15_W
4645 BFD_RELOC_C6000_SBR_S16
4647 BFD_RELOC_C6000_SBR_L16_B
4649 BFD_RELOC_C6000_SBR_L16_H
4651 BFD_RELOC_C6000_SBR_L16_W
4653 BFD_RELOC_C6000_SBR_H16_B
4655 BFD_RELOC_C6000_SBR_H16_H
4657 BFD_RELOC_C6000_SBR_H16_W
4659 BFD_RELOC_C6000_SBR_GOT_U15_W
4661 BFD_RELOC_C6000_SBR_GOT_L16_W
4663 BFD_RELOC_C6000_SBR_GOT_H16_W
4665 BFD_RELOC_C6000_DSBT_INDEX
4667 BFD_RELOC_C6000_PREL31
4669 BFD_RELOC_C6000_COPY
4671 BFD_RELOC_C6000_JUMP_SLOT
4673 BFD_RELOC_C6000_EHTYPE
4675 BFD_RELOC_C6000_PCR_H16
4677 BFD_RELOC_C6000_PCR_L16
4679 BFD_RELOC_C6000_ALIGN
4681 BFD_RELOC_C6000_FPHEAD
4683 BFD_RELOC_C6000_NOCMP
4685 TMS320C6000 relocations.
4690 This is a 48 bit reloc for the FR30 that stores 32 bits.
4694 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4697 BFD_RELOC_FR30_6_IN_4
4699 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4702 BFD_RELOC_FR30_8_IN_8
4704 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4707 BFD_RELOC_FR30_9_IN_8
4709 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4712 BFD_RELOC_FR30_10_IN_8
4714 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4717 BFD_RELOC_FR30_9_PCREL
4719 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4720 short offset into 8 bits.
4722 BFD_RELOC_FR30_12_PCREL
4724 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4725 short offset into 11 bits.
4728 BFD_RELOC_MCORE_PCREL_IMM8BY4
4730 BFD_RELOC_MCORE_PCREL_IMM11BY2
4732 BFD_RELOC_MCORE_PCREL_IMM4BY2
4734 BFD_RELOC_MCORE_PCREL_32
4736 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4740 Motorola Mcore relocations.
4749 BFD_RELOC_MEP_PCREL8A2
4751 BFD_RELOC_MEP_PCREL12A2
4753 BFD_RELOC_MEP_PCREL17A2
4755 BFD_RELOC_MEP_PCREL24A2
4757 BFD_RELOC_MEP_PCABS24A2
4769 BFD_RELOC_MEP_TPREL7
4771 BFD_RELOC_MEP_TPREL7A2
4773 BFD_RELOC_MEP_TPREL7A4
4775 BFD_RELOC_MEP_UIMM24
4777 BFD_RELOC_MEP_ADDR24A4
4779 BFD_RELOC_MEP_GNU_VTINHERIT
4781 BFD_RELOC_MEP_GNU_VTENTRY
4783 Toshiba Media Processor Relocations.
4787 BFD_RELOC_METAG_HIADDR16
4789 BFD_RELOC_METAG_LOADDR16
4791 BFD_RELOC_METAG_RELBRANCH
4793 BFD_RELOC_METAG_GETSETOFF
4795 BFD_RELOC_METAG_HIOG
4797 BFD_RELOC_METAG_LOOG
4799 BFD_RELOC_METAG_REL8
4801 BFD_RELOC_METAG_REL16
4803 BFD_RELOC_METAG_HI16_GOTOFF
4805 BFD_RELOC_METAG_LO16_GOTOFF
4807 BFD_RELOC_METAG_GETSET_GOTOFF
4809 BFD_RELOC_METAG_GETSET_GOT
4811 BFD_RELOC_METAG_HI16_GOTPC
4813 BFD_RELOC_METAG_LO16_GOTPC
4815 BFD_RELOC_METAG_HI16_PLT
4817 BFD_RELOC_METAG_LO16_PLT
4819 BFD_RELOC_METAG_RELBRANCH_PLT
4821 BFD_RELOC_METAG_GOTOFF
4825 BFD_RELOC_METAG_COPY
4827 BFD_RELOC_METAG_JMP_SLOT
4829 BFD_RELOC_METAG_RELATIVE
4831 BFD_RELOC_METAG_GLOB_DAT
4833 BFD_RELOC_METAG_TLS_GD
4835 BFD_RELOC_METAG_TLS_LDM
4837 BFD_RELOC_METAG_TLS_LDO_HI16
4839 BFD_RELOC_METAG_TLS_LDO_LO16
4841 BFD_RELOC_METAG_TLS_LDO
4843 BFD_RELOC_METAG_TLS_IE
4845 BFD_RELOC_METAG_TLS_IENONPIC
4847 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4849 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4851 BFD_RELOC_METAG_TLS_TPOFF
4853 BFD_RELOC_METAG_TLS_DTPMOD
4855 BFD_RELOC_METAG_TLS_DTPOFF
4857 BFD_RELOC_METAG_TLS_LE
4859 BFD_RELOC_METAG_TLS_LE_HI16
4861 BFD_RELOC_METAG_TLS_LE_LO16
4863 Imagination Technologies Meta relocations.
4868 BFD_RELOC_MMIX_GETA_1
4870 BFD_RELOC_MMIX_GETA_2
4872 BFD_RELOC_MMIX_GETA_3
4874 These are relocations for the GETA instruction.
4876 BFD_RELOC_MMIX_CBRANCH
4878 BFD_RELOC_MMIX_CBRANCH_J
4880 BFD_RELOC_MMIX_CBRANCH_1
4882 BFD_RELOC_MMIX_CBRANCH_2
4884 BFD_RELOC_MMIX_CBRANCH_3
4886 These are relocations for a conditional branch instruction.
4888 BFD_RELOC_MMIX_PUSHJ
4890 BFD_RELOC_MMIX_PUSHJ_1
4892 BFD_RELOC_MMIX_PUSHJ_2
4894 BFD_RELOC_MMIX_PUSHJ_3
4896 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4898 These are relocations for the PUSHJ instruction.
4902 BFD_RELOC_MMIX_JMP_1
4904 BFD_RELOC_MMIX_JMP_2
4906 BFD_RELOC_MMIX_JMP_3
4908 These are relocations for the JMP instruction.
4910 BFD_RELOC_MMIX_ADDR19
4912 This is a relocation for a relative address as in a GETA instruction or
4915 BFD_RELOC_MMIX_ADDR27
4917 This is a relocation for a relative address as in a JMP instruction.
4919 BFD_RELOC_MMIX_REG_OR_BYTE
4921 This is a relocation for an instruction field that may be a general
4922 register or a value 0..255.
4926 This is a relocation for an instruction field that may be a general
4929 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4931 This is a relocation for two instruction fields holding a register and
4932 an offset, the equivalent of the relocation.
4934 BFD_RELOC_MMIX_LOCAL
4936 This relocation is an assertion that the expression is not allocated as
4937 a global register. It does not modify contents.
4940 BFD_RELOC_AVR_7_PCREL
4942 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4943 short offset into 7 bits.
4945 BFD_RELOC_AVR_13_PCREL
4947 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4948 short offset into 12 bits.
4952 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4953 program memory address) into 16 bits.
4955 BFD_RELOC_AVR_LO8_LDI
4957 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4958 data memory address) into 8 bit immediate value of LDI insn.
4960 BFD_RELOC_AVR_HI8_LDI
4962 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4963 of data memory address) into 8 bit immediate value of LDI insn.
4965 BFD_RELOC_AVR_HH8_LDI
4967 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4968 of program memory address) into 8 bit immediate value of LDI insn.
4970 BFD_RELOC_AVR_MS8_LDI
4972 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4973 of 32 bit value) into 8 bit immediate value of LDI insn.
4975 BFD_RELOC_AVR_LO8_LDI_NEG
4977 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4978 (usually data memory address) into 8 bit immediate value of SUBI insn.
4980 BFD_RELOC_AVR_HI8_LDI_NEG
4982 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4983 (high 8 bit of data memory address) into 8 bit immediate value of
4986 BFD_RELOC_AVR_HH8_LDI_NEG
4988 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4989 (most high 8 bit of program memory address) into 8 bit immediate value
4990 of LDI or SUBI insn.
4992 BFD_RELOC_AVR_MS8_LDI_NEG
4994 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4995 of 32 bit value) into 8 bit immediate value of LDI insn.
4997 BFD_RELOC_AVR_LO8_LDI_PM
4999 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5000 command address) into 8 bit immediate value of LDI insn.
5002 BFD_RELOC_AVR_LO8_LDI_GS
5004 This is a 16 bit reloc for the AVR that stores 8 bit value
5005 (command address) into 8 bit immediate value of LDI insn. If the address
5006 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5009 BFD_RELOC_AVR_HI8_LDI_PM
5011 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5012 of command address) into 8 bit immediate value of LDI insn.
5014 BFD_RELOC_AVR_HI8_LDI_GS
5016 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5017 of command address) into 8 bit immediate value of LDI insn. If the address
5018 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5021 BFD_RELOC_AVR_HH8_LDI_PM
5023 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5024 of command address) into 8 bit immediate value of LDI insn.
5026 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5028 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5029 (usually command address) into 8 bit immediate value of SUBI insn.
5031 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5033 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5034 (high 8 bit of 16 bit command address) into 8 bit immediate value
5037 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5039 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5040 (high 6 bit of 22 bit command address) into 8 bit immediate
5045 This is a 32 bit reloc for the AVR that stores 23 bit value
5050 This is a 16 bit reloc for the AVR that stores all needed bits
5051 for absolute addressing with ldi with overflow check to linktime
5055 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5058 BFD_RELOC_AVR_6_ADIW
5060 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5065 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5066 in .byte lo8(symbol)
5070 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5071 in .byte hi8(symbol)
5075 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5076 in .byte hlo8(symbol)
5080 BFD_RELOC_AVR_DIFF16
5082 BFD_RELOC_AVR_DIFF32
5084 AVR relocations to mark the difference of two local symbols.
5085 These are only needed to support linker relaxation and can be ignored
5086 when not relaxing. The field is set to the value of the difference
5087 assuming no relaxation. The relocation encodes the position of the
5088 second symbol so the linker can determine whether to adjust the field
5091 BFD_RELOC_AVR_LDS_STS_16
5093 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5094 lds and sts instructions supported only tiny core.
5098 This is a 6 bit reloc for the AVR that stores an I/O register
5099 number for the IN and OUT instructions
5103 This is a 5 bit reloc for the AVR that stores an I/O register
5104 number for the SBIC, SBIS, SBI and CBI instructions
5107 BFD_RELOC_RISCV_HI20
5109 BFD_RELOC_RISCV_PCREL_HI20
5111 BFD_RELOC_RISCV_PCREL_LO12_I
5113 BFD_RELOC_RISCV_PCREL_LO12_S
5115 BFD_RELOC_RISCV_LO12_I
5117 BFD_RELOC_RISCV_LO12_S
5119 BFD_RELOC_RISCV_GPREL12_I
5121 BFD_RELOC_RISCV_GPREL12_S
5123 BFD_RELOC_RISCV_TPREL_HI20
5125 BFD_RELOC_RISCV_TPREL_LO12_I
5127 BFD_RELOC_RISCV_TPREL_LO12_S
5129 BFD_RELOC_RISCV_TPREL_ADD
5131 BFD_RELOC_RISCV_CALL
5133 BFD_RELOC_RISCV_CALL_PLT
5135 BFD_RELOC_RISCV_ADD8
5137 BFD_RELOC_RISCV_ADD16
5139 BFD_RELOC_RISCV_ADD32
5141 BFD_RELOC_RISCV_ADD64
5143 BFD_RELOC_RISCV_SUB8
5145 BFD_RELOC_RISCV_SUB16
5147 BFD_RELOC_RISCV_SUB32
5149 BFD_RELOC_RISCV_SUB64
5151 BFD_RELOC_RISCV_GOT_HI20
5153 BFD_RELOC_RISCV_TLS_GOT_HI20
5155 BFD_RELOC_RISCV_TLS_GD_HI20
5159 BFD_RELOC_RISCV_TLS_DTPMOD32
5161 BFD_RELOC_RISCV_TLS_DTPREL32
5163 BFD_RELOC_RISCV_TLS_DTPMOD64
5165 BFD_RELOC_RISCV_TLS_DTPREL64
5167 BFD_RELOC_RISCV_TLS_TPREL32
5169 BFD_RELOC_RISCV_TLS_TPREL64
5171 BFD_RELOC_RISCV_ALIGN
5173 BFD_RELOC_RISCV_RVC_BRANCH
5175 BFD_RELOC_RISCV_RVC_JUMP
5177 BFD_RELOC_RISCV_RVC_LUI
5179 BFD_RELOC_RISCV_GPREL_I
5181 BFD_RELOC_RISCV_GPREL_S
5183 BFD_RELOC_RISCV_TPREL_I
5185 BFD_RELOC_RISCV_TPREL_S
5187 BFD_RELOC_RISCV_RELAX
5191 BFD_RELOC_RISCV_SUB6
5193 BFD_RELOC_RISCV_SET6
5195 BFD_RELOC_RISCV_SET8
5197 BFD_RELOC_RISCV_SET16
5199 BFD_RELOC_RISCV_SET32
5201 BFD_RELOC_RISCV_32_PCREL
5208 BFD_RELOC_RL78_NEG16
5210 BFD_RELOC_RL78_NEG24
5212 BFD_RELOC_RL78_NEG32
5214 BFD_RELOC_RL78_16_OP
5216 BFD_RELOC_RL78_24_OP
5218 BFD_RELOC_RL78_32_OP
5226 BFD_RELOC_RL78_DIR3U_PCREL
5230 BFD_RELOC_RL78_GPRELB
5232 BFD_RELOC_RL78_GPRELW
5234 BFD_RELOC_RL78_GPRELL
5238 BFD_RELOC_RL78_OP_SUBTRACT
5240 BFD_RELOC_RL78_OP_NEG
5242 BFD_RELOC_RL78_OP_AND
5244 BFD_RELOC_RL78_OP_SHRA
5248 BFD_RELOC_RL78_ABS16
5250 BFD_RELOC_RL78_ABS16_REV
5252 BFD_RELOC_RL78_ABS32
5254 BFD_RELOC_RL78_ABS32_REV
5256 BFD_RELOC_RL78_ABS16U
5258 BFD_RELOC_RL78_ABS16UW
5260 BFD_RELOC_RL78_ABS16UL
5262 BFD_RELOC_RL78_RELAX
5272 BFD_RELOC_RL78_SADDR
5274 Renesas RL78 Relocations.
5297 BFD_RELOC_RX_DIR3U_PCREL
5309 BFD_RELOC_RX_OP_SUBTRACT
5317 BFD_RELOC_RX_ABS16_REV
5321 BFD_RELOC_RX_ABS32_REV
5325 BFD_RELOC_RX_ABS16UW
5327 BFD_RELOC_RX_ABS16UL
5331 Renesas RX Relocations.
5344 32 bit PC relative PLT address.
5348 Copy symbol at runtime.
5350 BFD_RELOC_390_GLOB_DAT
5354 BFD_RELOC_390_JMP_SLOT
5358 BFD_RELOC_390_RELATIVE
5360 Adjust by program base.
5364 32 bit PC relative offset to GOT.
5370 BFD_RELOC_390_PC12DBL
5372 PC relative 12 bit shifted by 1.
5374 BFD_RELOC_390_PLT12DBL
5376 12 bit PC rel. PLT shifted by 1.
5378 BFD_RELOC_390_PC16DBL
5380 PC relative 16 bit shifted by 1.
5382 BFD_RELOC_390_PLT16DBL
5384 16 bit PC rel. PLT shifted by 1.
5386 BFD_RELOC_390_PC24DBL
5388 PC relative 24 bit shifted by 1.
5390 BFD_RELOC_390_PLT24DBL
5392 24 bit PC rel. PLT shifted by 1.
5394 BFD_RELOC_390_PC32DBL
5396 PC relative 32 bit shifted by 1.
5398 BFD_RELOC_390_PLT32DBL
5400 32 bit PC rel. PLT shifted by 1.
5402 BFD_RELOC_390_GOTPCDBL
5404 32 bit PC rel. GOT shifted by 1.
5412 64 bit PC relative PLT address.
5414 BFD_RELOC_390_GOTENT
5416 32 bit rel. offset to GOT entry.
5418 BFD_RELOC_390_GOTOFF64
5420 64 bit offset to GOT.
5422 BFD_RELOC_390_GOTPLT12
5424 12-bit offset to symbol-entry within GOT, with PLT handling.
5426 BFD_RELOC_390_GOTPLT16
5428 16-bit offset to symbol-entry within GOT, with PLT handling.
5430 BFD_RELOC_390_GOTPLT32
5432 32-bit offset to symbol-entry within GOT, with PLT handling.
5434 BFD_RELOC_390_GOTPLT64
5436 64-bit offset to symbol-entry within GOT, with PLT handling.
5438 BFD_RELOC_390_GOTPLTENT
5440 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5442 BFD_RELOC_390_PLTOFF16
5444 16-bit rel. offset from the GOT to a PLT entry.
5446 BFD_RELOC_390_PLTOFF32
5448 32-bit rel. offset from the GOT to a PLT entry.
5450 BFD_RELOC_390_PLTOFF64
5452 64-bit rel. offset from the GOT to a PLT entry.
5455 BFD_RELOC_390_TLS_LOAD
5457 BFD_RELOC_390_TLS_GDCALL
5459 BFD_RELOC_390_TLS_LDCALL
5461 BFD_RELOC_390_TLS_GD32
5463 BFD_RELOC_390_TLS_GD64
5465 BFD_RELOC_390_TLS_GOTIE12
5467 BFD_RELOC_390_TLS_GOTIE32
5469 BFD_RELOC_390_TLS_GOTIE64
5471 BFD_RELOC_390_TLS_LDM32
5473 BFD_RELOC_390_TLS_LDM64
5475 BFD_RELOC_390_TLS_IE32
5477 BFD_RELOC_390_TLS_IE64
5479 BFD_RELOC_390_TLS_IEENT
5481 BFD_RELOC_390_TLS_LE32
5483 BFD_RELOC_390_TLS_LE64
5485 BFD_RELOC_390_TLS_LDO32
5487 BFD_RELOC_390_TLS_LDO64
5489 BFD_RELOC_390_TLS_DTPMOD
5491 BFD_RELOC_390_TLS_DTPOFF
5493 BFD_RELOC_390_TLS_TPOFF
5495 s390 tls relocations.
5502 BFD_RELOC_390_GOTPLT20
5504 BFD_RELOC_390_TLS_GOTIE20
5506 Long displacement extension.
5509 BFD_RELOC_390_IRELATIVE
5511 STT_GNU_IFUNC relocation.
5514 BFD_RELOC_SCORE_GPREL15
5517 Low 16 bit for load/store
5519 BFD_RELOC_SCORE_DUMMY2
5523 This is a 24-bit reloc with the right 1 bit assumed to be 0
5525 BFD_RELOC_SCORE_BRANCH
5527 This is a 19-bit reloc with the right 1 bit assumed to be 0
5529 BFD_RELOC_SCORE_IMM30
5531 This is a 32-bit reloc for 48-bit instructions.
5533 BFD_RELOC_SCORE_IMM32
5535 This is a 32-bit reloc for 48-bit instructions.
5537 BFD_RELOC_SCORE16_JMP
5539 This is a 11-bit reloc with the right 1 bit assumed to be 0
5541 BFD_RELOC_SCORE16_BRANCH
5543 This is a 8-bit reloc with the right 1 bit assumed to be 0
5545 BFD_RELOC_SCORE_BCMP
5547 This is a 9-bit reloc with the right 1 bit assumed to be 0
5549 BFD_RELOC_SCORE_GOT15
5551 BFD_RELOC_SCORE_GOT_LO16
5553 BFD_RELOC_SCORE_CALL15
5555 BFD_RELOC_SCORE_DUMMY_HI16
5557 Undocumented Score relocs
5562 Scenix IP2K - 9-bit register number / data address
5566 Scenix IP2K - 4-bit register/data bank number
5568 BFD_RELOC_IP2K_ADDR16CJP
5570 Scenix IP2K - low 13 bits of instruction word address
5572 BFD_RELOC_IP2K_PAGE3
5574 Scenix IP2K - high 3 bits of instruction word address
5576 BFD_RELOC_IP2K_LO8DATA
5578 BFD_RELOC_IP2K_HI8DATA
5580 BFD_RELOC_IP2K_EX8DATA
5582 Scenix IP2K - ext/low/high 8 bits of data address
5584 BFD_RELOC_IP2K_LO8INSN
5586 BFD_RELOC_IP2K_HI8INSN
5588 Scenix IP2K - low/high 8 bits of instruction word address
5590 BFD_RELOC_IP2K_PC_SKIP
5592 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5596 Scenix IP2K - 16 bit word address in text section.
5598 BFD_RELOC_IP2K_FR_OFFSET
5600 Scenix IP2K - 7-bit sp or dp offset
5602 BFD_RELOC_VPE4KMATH_DATA
5604 BFD_RELOC_VPE4KMATH_INSN
5606 Scenix VPE4K coprocessor - data/insn-space addressing
5609 BFD_RELOC_VTABLE_INHERIT
5611 BFD_RELOC_VTABLE_ENTRY
5613 These two relocations are used by the linker to determine which of
5614 the entries in a C++ virtual function table are actually used. When
5615 the --gc-sections option is given, the linker will zero out the entries
5616 that are not used, so that the code for those functions need not be
5617 included in the output.
5619 VTABLE_INHERIT is a zero-space relocation used to describe to the
5620 linker the inheritance tree of a C++ virtual function table. The
5621 relocation's symbol should be the parent class' vtable, and the
5622 relocation should be located at the child vtable.
5624 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5625 virtual function table entry. The reloc's symbol should refer to the
5626 table of the class mentioned in the code. Off of that base, an offset
5627 describes the entry that is being used. For Rela hosts, this offset
5628 is stored in the reloc's addend. For Rel hosts, we are forced to put
5629 this offset in the reloc's section offset.
5632 BFD_RELOC_IA64_IMM14
5634 BFD_RELOC_IA64_IMM22
5636 BFD_RELOC_IA64_IMM64
5638 BFD_RELOC_IA64_DIR32MSB
5640 BFD_RELOC_IA64_DIR32LSB
5642 BFD_RELOC_IA64_DIR64MSB
5644 BFD_RELOC_IA64_DIR64LSB
5646 BFD_RELOC_IA64_GPREL22
5648 BFD_RELOC_IA64_GPREL64I
5650 BFD_RELOC_IA64_GPREL32MSB
5652 BFD_RELOC_IA64_GPREL32LSB
5654 BFD_RELOC_IA64_GPREL64MSB
5656 BFD_RELOC_IA64_GPREL64LSB
5658 BFD_RELOC_IA64_LTOFF22
5660 BFD_RELOC_IA64_LTOFF64I
5662 BFD_RELOC_IA64_PLTOFF22
5664 BFD_RELOC_IA64_PLTOFF64I
5666 BFD_RELOC_IA64_PLTOFF64MSB
5668 BFD_RELOC_IA64_PLTOFF64LSB
5670 BFD_RELOC_IA64_FPTR64I
5672 BFD_RELOC_IA64_FPTR32MSB
5674 BFD_RELOC_IA64_FPTR32LSB
5676 BFD_RELOC_IA64_FPTR64MSB
5678 BFD_RELOC_IA64_FPTR64LSB
5680 BFD_RELOC_IA64_PCREL21B
5682 BFD_RELOC_IA64_PCREL21BI
5684 BFD_RELOC_IA64_PCREL21M
5686 BFD_RELOC_IA64_PCREL21F
5688 BFD_RELOC_IA64_PCREL22
5690 BFD_RELOC_IA64_PCREL60B
5692 BFD_RELOC_IA64_PCREL64I
5694 BFD_RELOC_IA64_PCREL32MSB
5696 BFD_RELOC_IA64_PCREL32LSB
5698 BFD_RELOC_IA64_PCREL64MSB
5700 BFD_RELOC_IA64_PCREL64LSB
5702 BFD_RELOC_IA64_LTOFF_FPTR22
5704 BFD_RELOC_IA64_LTOFF_FPTR64I
5706 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5708 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5710 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5712 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5714 BFD_RELOC_IA64_SEGREL32MSB
5716 BFD_RELOC_IA64_SEGREL32LSB
5718 BFD_RELOC_IA64_SEGREL64MSB
5720 BFD_RELOC_IA64_SEGREL64LSB
5722 BFD_RELOC_IA64_SECREL32MSB
5724 BFD_RELOC_IA64_SECREL32LSB
5726 BFD_RELOC_IA64_SECREL64MSB
5728 BFD_RELOC_IA64_SECREL64LSB
5730 BFD_RELOC_IA64_REL32MSB
5732 BFD_RELOC_IA64_REL32LSB
5734 BFD_RELOC_IA64_REL64MSB
5736 BFD_RELOC_IA64_REL64LSB
5738 BFD_RELOC_IA64_LTV32MSB
5740 BFD_RELOC_IA64_LTV32LSB
5742 BFD_RELOC_IA64_LTV64MSB
5744 BFD_RELOC_IA64_LTV64LSB
5746 BFD_RELOC_IA64_IPLTMSB
5748 BFD_RELOC_IA64_IPLTLSB
5752 BFD_RELOC_IA64_LTOFF22X
5754 BFD_RELOC_IA64_LDXMOV
5756 BFD_RELOC_IA64_TPREL14
5758 BFD_RELOC_IA64_TPREL22
5760 BFD_RELOC_IA64_TPREL64I
5762 BFD_RELOC_IA64_TPREL64MSB
5764 BFD_RELOC_IA64_TPREL64LSB
5766 BFD_RELOC_IA64_LTOFF_TPREL22
5768 BFD_RELOC_IA64_DTPMOD64MSB
5770 BFD_RELOC_IA64_DTPMOD64LSB
5772 BFD_RELOC_IA64_LTOFF_DTPMOD22
5774 BFD_RELOC_IA64_DTPREL14
5776 BFD_RELOC_IA64_DTPREL22
5778 BFD_RELOC_IA64_DTPREL64I
5780 BFD_RELOC_IA64_DTPREL32MSB
5782 BFD_RELOC_IA64_DTPREL32LSB
5784 BFD_RELOC_IA64_DTPREL64MSB
5786 BFD_RELOC_IA64_DTPREL64LSB
5788 BFD_RELOC_IA64_LTOFF_DTPREL22
5790 Intel IA64 Relocations.
5793 BFD_RELOC_M68HC11_HI8
5795 Motorola 68HC11 reloc.
5796 This is the 8 bit high part of an absolute address.
5798 BFD_RELOC_M68HC11_LO8
5800 Motorola 68HC11 reloc.
5801 This is the 8 bit low part of an absolute address.
5803 BFD_RELOC_M68HC11_3B
5805 Motorola 68HC11 reloc.
5806 This is the 3 bit of a value.
5808 BFD_RELOC_M68HC11_RL_JUMP
5810 Motorola 68HC11 reloc.
5811 This reloc marks the beginning of a jump/call instruction.
5812 It is used for linker relaxation to correctly identify beginning
5813 of instruction and change some branches to use PC-relative
5816 BFD_RELOC_M68HC11_RL_GROUP
5818 Motorola 68HC11 reloc.
5819 This reloc marks a group of several instructions that gcc generates
5820 and for which the linker relaxation pass can modify and/or remove
5823 BFD_RELOC_M68HC11_LO16
5825 Motorola 68HC11 reloc.
5826 This is the 16-bit lower part of an address. It is used for 'call'
5827 instruction to specify the symbol address without any special
5828 transformation (due to memory bank window).
5830 BFD_RELOC_M68HC11_PAGE
5832 Motorola 68HC11 reloc.
5833 This is a 8-bit reloc that specifies the page number of an address.
5834 It is used by 'call' instruction to specify the page number of
5837 BFD_RELOC_M68HC11_24
5839 Motorola 68HC11 reloc.
5840 This is a 24-bit reloc that represents the address with a 16-bit
5841 value and a 8-bit page number. The symbol address is transformed
5842 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5844 BFD_RELOC_M68HC12_5B
5846 Motorola 68HC12 reloc.
5847 This is the 5 bits of a value.
5849 BFD_RELOC_XGATE_RL_JUMP
5851 Freescale XGATE reloc.
5852 This reloc marks the beginning of a bra/jal instruction.
5854 BFD_RELOC_XGATE_RL_GROUP
5856 Freescale XGATE reloc.
5857 This reloc marks a group of several instructions that gcc generates
5858 and for which the linker relaxation pass can modify and/or remove
5861 BFD_RELOC_XGATE_LO16
5863 Freescale XGATE reloc.
5864 This is the 16-bit lower part of an address. It is used for the '16-bit'
5867 BFD_RELOC_XGATE_GPAGE
5869 Freescale XGATE reloc.
5873 Freescale XGATE reloc.
5875 BFD_RELOC_XGATE_PCREL_9
5877 Freescale XGATE reloc.
5878 This is a 9-bit pc-relative reloc.
5880 BFD_RELOC_XGATE_PCREL_10
5882 Freescale XGATE reloc.
5883 This is a 10-bit pc-relative reloc.
5885 BFD_RELOC_XGATE_IMM8_LO
5887 Freescale XGATE reloc.
5888 This is the 16-bit lower part of an address. It is used for the '16-bit'
5891 BFD_RELOC_XGATE_IMM8_HI
5893 Freescale XGATE reloc.
5894 This is the 16-bit higher part of an address. It is used for the '16-bit'
5897 BFD_RELOC_XGATE_IMM3
5899 Freescale XGATE reloc.
5900 This is a 3-bit pc-relative reloc.
5902 BFD_RELOC_XGATE_IMM4
5904 Freescale XGATE reloc.
5905 This is a 4-bit pc-relative reloc.
5907 BFD_RELOC_XGATE_IMM5
5909 Freescale XGATE reloc.
5910 This is a 5-bit pc-relative reloc.
5912 BFD_RELOC_M68HC12_9B
5914 Motorola 68HC12 reloc.
5915 This is the 9 bits of a value.
5917 BFD_RELOC_M68HC12_16B
5919 Motorola 68HC12 reloc.
5920 This is the 16 bits of a value.
5922 BFD_RELOC_M68HC12_9_PCREL
5924 Motorola 68HC12/XGATE reloc.
5925 This is a PCREL9 branch.
5927 BFD_RELOC_M68HC12_10_PCREL
5929 Motorola 68HC12/XGATE reloc.
5930 This is a PCREL10 branch.
5932 BFD_RELOC_M68HC12_LO8XG
5934 Motorola 68HC12/XGATE reloc.
5935 This is the 8 bit low part of an absolute address and immediately precedes
5936 a matching HI8XG part.
5938 BFD_RELOC_M68HC12_HI8XG
5940 Motorola 68HC12/XGATE reloc.
5941 This is the 8 bit high part of an absolute address and immediately follows
5942 a matching LO8XG part.
5944 BFD_RELOC_S12Z_15_PCREL
5946 Freescale S12Z reloc.
5947 This is a 15 bit relative address. If the most significant bits are all zero
5948 then it may be truncated to 8 bits.
5952 BFD_RELOC_16C_NUM08_C
5956 BFD_RELOC_16C_NUM16_C
5960 BFD_RELOC_16C_NUM32_C
5962 BFD_RELOC_16C_DISP04
5964 BFD_RELOC_16C_DISP04_C
5966 BFD_RELOC_16C_DISP08
5968 BFD_RELOC_16C_DISP08_C
5970 BFD_RELOC_16C_DISP16
5972 BFD_RELOC_16C_DISP16_C
5974 BFD_RELOC_16C_DISP24
5976 BFD_RELOC_16C_DISP24_C
5978 BFD_RELOC_16C_DISP24a
5980 BFD_RELOC_16C_DISP24a_C
5984 BFD_RELOC_16C_REG04_C
5986 BFD_RELOC_16C_REG04a
5988 BFD_RELOC_16C_REG04a_C
5992 BFD_RELOC_16C_REG14_C
5996 BFD_RELOC_16C_REG16_C
6000 BFD_RELOC_16C_REG20_C
6004 BFD_RELOC_16C_ABS20_C
6008 BFD_RELOC_16C_ABS24_C
6012 BFD_RELOC_16C_IMM04_C
6016 BFD_RELOC_16C_IMM16_C
6020 BFD_RELOC_16C_IMM20_C
6024 BFD_RELOC_16C_IMM24_C
6028 BFD_RELOC_16C_IMM32_C
6030 NS CR16C Relocations.
6035 BFD_RELOC_CR16_NUM16
6037 BFD_RELOC_CR16_NUM32
6039 BFD_RELOC_CR16_NUM32a
6041 BFD_RELOC_CR16_REGREL0
6043 BFD_RELOC_CR16_REGREL4
6045 BFD_RELOC_CR16_REGREL4a
6047 BFD_RELOC_CR16_REGREL14
6049 BFD_RELOC_CR16_REGREL14a
6051 BFD_RELOC_CR16_REGREL16
6053 BFD_RELOC_CR16_REGREL20
6055 BFD_RELOC_CR16_REGREL20a
6057 BFD_RELOC_CR16_ABS20
6059 BFD_RELOC_CR16_ABS24
6065 BFD_RELOC_CR16_IMM16
6067 BFD_RELOC_CR16_IMM20
6069 BFD_RELOC_CR16_IMM24
6071 BFD_RELOC_CR16_IMM32
6073 BFD_RELOC_CR16_IMM32a
6075 BFD_RELOC_CR16_DISP4
6077 BFD_RELOC_CR16_DISP8
6079 BFD_RELOC_CR16_DISP16
6081 BFD_RELOC_CR16_DISP20
6083 BFD_RELOC_CR16_DISP24
6085 BFD_RELOC_CR16_DISP24a
6087 BFD_RELOC_CR16_SWITCH8
6089 BFD_RELOC_CR16_SWITCH16
6091 BFD_RELOC_CR16_SWITCH32
6093 BFD_RELOC_CR16_GOT_REGREL20
6095 BFD_RELOC_CR16_GOTC_REGREL20
6097 BFD_RELOC_CR16_GLOB_DAT
6099 NS CR16 Relocations.
6106 BFD_RELOC_CRX_REL8_CMP
6114 BFD_RELOC_CRX_REGREL12
6116 BFD_RELOC_CRX_REGREL22
6118 BFD_RELOC_CRX_REGREL28
6120 BFD_RELOC_CRX_REGREL32
6136 BFD_RELOC_CRX_SWITCH8
6138 BFD_RELOC_CRX_SWITCH16
6140 BFD_RELOC_CRX_SWITCH32
6145 BFD_RELOC_CRIS_BDISP8
6147 BFD_RELOC_CRIS_UNSIGNED_5
6149 BFD_RELOC_CRIS_SIGNED_6
6151 BFD_RELOC_CRIS_UNSIGNED_6
6153 BFD_RELOC_CRIS_SIGNED_8
6155 BFD_RELOC_CRIS_UNSIGNED_8
6157 BFD_RELOC_CRIS_SIGNED_16
6159 BFD_RELOC_CRIS_UNSIGNED_16
6161 BFD_RELOC_CRIS_LAPCQ_OFFSET
6163 BFD_RELOC_CRIS_UNSIGNED_4
6165 These relocs are only used within the CRIS assembler. They are not
6166 (at present) written to any object files.
6170 BFD_RELOC_CRIS_GLOB_DAT
6172 BFD_RELOC_CRIS_JUMP_SLOT
6174 BFD_RELOC_CRIS_RELATIVE
6176 Relocs used in ELF shared libraries for CRIS.
6178 BFD_RELOC_CRIS_32_GOT
6180 32-bit offset to symbol-entry within GOT.
6182 BFD_RELOC_CRIS_16_GOT
6184 16-bit offset to symbol-entry within GOT.
6186 BFD_RELOC_CRIS_32_GOTPLT
6188 32-bit offset to symbol-entry within GOT, with PLT handling.
6190 BFD_RELOC_CRIS_16_GOTPLT
6192 16-bit offset to symbol-entry within GOT, with PLT handling.
6194 BFD_RELOC_CRIS_32_GOTREL
6196 32-bit offset to symbol, relative to GOT.
6198 BFD_RELOC_CRIS_32_PLT_GOTREL
6200 32-bit offset to symbol with PLT entry, relative to GOT.
6202 BFD_RELOC_CRIS_32_PLT_PCREL
6204 32-bit offset to symbol with PLT entry, relative to this relocation.
6207 BFD_RELOC_CRIS_32_GOT_GD
6209 BFD_RELOC_CRIS_16_GOT_GD
6211 BFD_RELOC_CRIS_32_GD
6215 BFD_RELOC_CRIS_32_DTPREL
6217 BFD_RELOC_CRIS_16_DTPREL
6219 BFD_RELOC_CRIS_32_GOT_TPREL
6221 BFD_RELOC_CRIS_16_GOT_TPREL
6223 BFD_RELOC_CRIS_32_TPREL
6225 BFD_RELOC_CRIS_16_TPREL
6227 BFD_RELOC_CRIS_DTPMOD
6229 BFD_RELOC_CRIS_32_IE
6231 Relocs used in TLS code for CRIS.
6234 BFD_RELOC_OR1K_REL_26
6236 BFD_RELOC_OR1K_SLO16
6238 BFD_RELOC_OR1K_PCREL_PG21
6242 BFD_RELOC_OR1K_SLO13
6244 BFD_RELOC_OR1K_GOTPC_HI16
6246 BFD_RELOC_OR1K_GOTPC_LO16
6248 BFD_RELOC_OR1K_GOT16
6250 BFD_RELOC_OR1K_GOT_PG21
6252 BFD_RELOC_OR1K_GOT_LO13
6254 BFD_RELOC_OR1K_PLT26
6256 BFD_RELOC_OR1K_PLTA26
6258 BFD_RELOC_OR1K_GOTOFF_SLO16
6262 BFD_RELOC_OR1K_GLOB_DAT
6264 BFD_RELOC_OR1K_JMP_SLOT
6266 BFD_RELOC_OR1K_RELATIVE
6268 BFD_RELOC_OR1K_TLS_GD_HI16
6270 BFD_RELOC_OR1K_TLS_GD_LO16
6272 BFD_RELOC_OR1K_TLS_GD_PG21
6274 BFD_RELOC_OR1K_TLS_GD_LO13
6276 BFD_RELOC_OR1K_TLS_LDM_HI16
6278 BFD_RELOC_OR1K_TLS_LDM_LO16
6280 BFD_RELOC_OR1K_TLS_LDM_PG21
6282 BFD_RELOC_OR1K_TLS_LDM_LO13
6284 BFD_RELOC_OR1K_TLS_LDO_HI16
6286 BFD_RELOC_OR1K_TLS_LDO_LO16
6288 BFD_RELOC_OR1K_TLS_IE_HI16
6290 BFD_RELOC_OR1K_TLS_IE_AHI16
6292 BFD_RELOC_OR1K_TLS_IE_LO16
6294 BFD_RELOC_OR1K_TLS_IE_PG21
6296 BFD_RELOC_OR1K_TLS_IE_LO13
6298 BFD_RELOC_OR1K_TLS_LE_HI16
6300 BFD_RELOC_OR1K_TLS_LE_AHI16
6302 BFD_RELOC_OR1K_TLS_LE_LO16
6304 BFD_RELOC_OR1K_TLS_LE_SLO16
6306 BFD_RELOC_OR1K_TLS_TPOFF
6308 BFD_RELOC_OR1K_TLS_DTPOFF
6310 BFD_RELOC_OR1K_TLS_DTPMOD
6312 OpenRISC 1000 Relocations.
6315 BFD_RELOC_H8_DIR16A8
6317 BFD_RELOC_H8_DIR16R8
6319 BFD_RELOC_H8_DIR24A8
6321 BFD_RELOC_H8_DIR24R8
6323 BFD_RELOC_H8_DIR32A16
6325 BFD_RELOC_H8_DISP32A16
6330 BFD_RELOC_XSTORMY16_REL_12
6332 BFD_RELOC_XSTORMY16_12
6334 BFD_RELOC_XSTORMY16_24
6336 BFD_RELOC_XSTORMY16_FPTR16
6338 Sony Xstormy16 Relocations.
6343 Self-describing complex relocations.
6355 Infineon Relocations.
6358 BFD_RELOC_VAX_GLOB_DAT
6360 BFD_RELOC_VAX_JMP_SLOT
6362 BFD_RELOC_VAX_RELATIVE
6364 Relocations used by VAX ELF.
6369 Morpho MT - 16 bit immediate relocation.
6373 Morpho MT - Hi 16 bits of an address.
6377 Morpho MT - Low 16 bits of an address.
6379 BFD_RELOC_MT_GNU_VTINHERIT
6381 Morpho MT - Used to tell the linker which vtable entries are used.
6383 BFD_RELOC_MT_GNU_VTENTRY
6385 Morpho MT - Used to tell the linker which vtable entries are used.
6387 BFD_RELOC_MT_PCINSN8
6389 Morpho MT - 8 bit immediate relocation.
6392 BFD_RELOC_MSP430_10_PCREL
6394 BFD_RELOC_MSP430_16_PCREL
6398 BFD_RELOC_MSP430_16_PCREL_BYTE
6400 BFD_RELOC_MSP430_16_BYTE
6402 BFD_RELOC_MSP430_2X_PCREL
6404 BFD_RELOC_MSP430_RL_PCREL
6406 BFD_RELOC_MSP430_ABS8
6408 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6410 BFD_RELOC_MSP430X_PCR20_EXT_DST
6412 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6414 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6416 BFD_RELOC_MSP430X_ABS20_EXT_DST
6418 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6420 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6422 BFD_RELOC_MSP430X_ABS20_ADR_DST
6424 BFD_RELOC_MSP430X_PCR16
6426 BFD_RELOC_MSP430X_PCR20_CALL
6428 BFD_RELOC_MSP430X_ABS16
6430 BFD_RELOC_MSP430_ABS_HI16
6432 BFD_RELOC_MSP430_PREL31
6434 BFD_RELOC_MSP430_SYM_DIFF
6436 msp430 specific relocation codes
6443 BFD_RELOC_NIOS2_CALL26
6445 BFD_RELOC_NIOS2_IMM5
6447 BFD_RELOC_NIOS2_CACHE_OPX
6449 BFD_RELOC_NIOS2_IMM6
6451 BFD_RELOC_NIOS2_IMM8
6453 BFD_RELOC_NIOS2_HI16
6455 BFD_RELOC_NIOS2_LO16
6457 BFD_RELOC_NIOS2_HIADJ16
6459 BFD_RELOC_NIOS2_GPREL
6461 BFD_RELOC_NIOS2_UJMP
6463 BFD_RELOC_NIOS2_CJMP
6465 BFD_RELOC_NIOS2_CALLR
6467 BFD_RELOC_NIOS2_ALIGN
6469 BFD_RELOC_NIOS2_GOT16
6471 BFD_RELOC_NIOS2_CALL16
6473 BFD_RELOC_NIOS2_GOTOFF_LO
6475 BFD_RELOC_NIOS2_GOTOFF_HA
6477 BFD_RELOC_NIOS2_PCREL_LO
6479 BFD_RELOC_NIOS2_PCREL_HA
6481 BFD_RELOC_NIOS2_TLS_GD16
6483 BFD_RELOC_NIOS2_TLS_LDM16
6485 BFD_RELOC_NIOS2_TLS_LDO16
6487 BFD_RELOC_NIOS2_TLS_IE16
6489 BFD_RELOC_NIOS2_TLS_LE16
6491 BFD_RELOC_NIOS2_TLS_DTPMOD
6493 BFD_RELOC_NIOS2_TLS_DTPREL
6495 BFD_RELOC_NIOS2_TLS_TPREL
6497 BFD_RELOC_NIOS2_COPY
6499 BFD_RELOC_NIOS2_GLOB_DAT
6501 BFD_RELOC_NIOS2_JUMP_SLOT
6503 BFD_RELOC_NIOS2_RELATIVE
6505 BFD_RELOC_NIOS2_GOTOFF
6507 BFD_RELOC_NIOS2_CALL26_NOAT
6509 BFD_RELOC_NIOS2_GOT_LO
6511 BFD_RELOC_NIOS2_GOT_HA
6513 BFD_RELOC_NIOS2_CALL_LO
6515 BFD_RELOC_NIOS2_CALL_HA
6517 BFD_RELOC_NIOS2_R2_S12
6519 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6521 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6523 BFD_RELOC_NIOS2_R2_T1I7_2
6525 BFD_RELOC_NIOS2_R2_T2I4
6527 BFD_RELOC_NIOS2_R2_T2I4_1
6529 BFD_RELOC_NIOS2_R2_T2I4_2
6531 BFD_RELOC_NIOS2_R2_X1I7_2
6533 BFD_RELOC_NIOS2_R2_X2L5
6535 BFD_RELOC_NIOS2_R2_F1I5_2
6537 BFD_RELOC_NIOS2_R2_L5I4X1
6539 BFD_RELOC_NIOS2_R2_T1X1I6
6541 BFD_RELOC_NIOS2_R2_T1X1I6_2
6543 Relocations used by the Altera Nios II core.
6548 PRU LDI 16-bit unsigned data-memory relocation.
6550 BFD_RELOC_PRU_U16_PMEMIMM
6552 PRU LDI 16-bit unsigned instruction-memory relocation.
6556 PRU relocation for two consecutive LDI load instructions that load a
6557 32 bit value into a register. If the higher bits are all zero, then
6558 the second instruction may be relaxed.
6560 BFD_RELOC_PRU_S10_PCREL
6562 PRU QBBx 10-bit signed PC-relative relocation.
6564 BFD_RELOC_PRU_U8_PCREL
6566 PRU 8-bit unsigned relocation used for the LOOP instruction.
6568 BFD_RELOC_PRU_32_PMEM
6570 BFD_RELOC_PRU_16_PMEM
6572 PRU Program Memory relocations. Used to convert from byte addressing to
6573 32-bit word addressing.
6575 BFD_RELOC_PRU_GNU_DIFF8
6577 BFD_RELOC_PRU_GNU_DIFF16
6579 BFD_RELOC_PRU_GNU_DIFF32
6581 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6583 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6585 PRU relocations to mark the difference of two local symbols.
6586 These are only needed to support linker relaxation and can be ignored
6587 when not relaxing. The field is set to the value of the difference
6588 assuming no relaxation. The relocation encodes the position of the
6589 second symbol so the linker can determine whether to adjust the field
6590 value. The PMEM variants encode the word difference, instead of byte
6591 difference between symbols.
6594 BFD_RELOC_IQ2000_OFFSET_16
6596 BFD_RELOC_IQ2000_OFFSET_21
6598 BFD_RELOC_IQ2000_UHI16
6603 BFD_RELOC_XTENSA_RTLD
6605 Special Xtensa relocation used only by PLT entries in ELF shared
6606 objects to indicate that the runtime linker should set the value
6607 to one of its own internal functions or data structures.
6609 BFD_RELOC_XTENSA_GLOB_DAT
6611 BFD_RELOC_XTENSA_JMP_SLOT
6613 BFD_RELOC_XTENSA_RELATIVE
6615 Xtensa relocations for ELF shared objects.
6617 BFD_RELOC_XTENSA_PLT
6619 Xtensa relocation used in ELF object files for symbols that may require
6620 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6622 BFD_RELOC_XTENSA_DIFF8
6624 BFD_RELOC_XTENSA_DIFF16
6626 BFD_RELOC_XTENSA_DIFF32
6628 Xtensa relocations to mark the difference of two local symbols.
6629 These are only needed to support linker relaxation and can be ignored
6630 when not relaxing. The field is set to the value of the difference
6631 assuming no relaxation. The relocation encodes the position of the
6632 first symbol so the linker can determine whether to adjust the field
6635 BFD_RELOC_XTENSA_SLOT0_OP
6637 BFD_RELOC_XTENSA_SLOT1_OP
6639 BFD_RELOC_XTENSA_SLOT2_OP
6641 BFD_RELOC_XTENSA_SLOT3_OP
6643 BFD_RELOC_XTENSA_SLOT4_OP
6645 BFD_RELOC_XTENSA_SLOT5_OP
6647 BFD_RELOC_XTENSA_SLOT6_OP
6649 BFD_RELOC_XTENSA_SLOT7_OP
6651 BFD_RELOC_XTENSA_SLOT8_OP
6653 BFD_RELOC_XTENSA_SLOT9_OP
6655 BFD_RELOC_XTENSA_SLOT10_OP
6657 BFD_RELOC_XTENSA_SLOT11_OP
6659 BFD_RELOC_XTENSA_SLOT12_OP
6661 BFD_RELOC_XTENSA_SLOT13_OP
6663 BFD_RELOC_XTENSA_SLOT14_OP
6665 Generic Xtensa relocations for instruction operands. Only the slot
6666 number is encoded in the relocation. The relocation applies to the
6667 last PC-relative immediate operand, or if there are no PC-relative
6668 immediates, to the last immediate operand.
6670 BFD_RELOC_XTENSA_SLOT0_ALT
6672 BFD_RELOC_XTENSA_SLOT1_ALT
6674 BFD_RELOC_XTENSA_SLOT2_ALT
6676 BFD_RELOC_XTENSA_SLOT3_ALT
6678 BFD_RELOC_XTENSA_SLOT4_ALT
6680 BFD_RELOC_XTENSA_SLOT5_ALT
6682 BFD_RELOC_XTENSA_SLOT6_ALT
6684 BFD_RELOC_XTENSA_SLOT7_ALT
6686 BFD_RELOC_XTENSA_SLOT8_ALT
6688 BFD_RELOC_XTENSA_SLOT9_ALT
6690 BFD_RELOC_XTENSA_SLOT10_ALT
6692 BFD_RELOC_XTENSA_SLOT11_ALT
6694 BFD_RELOC_XTENSA_SLOT12_ALT
6696 BFD_RELOC_XTENSA_SLOT13_ALT
6698 BFD_RELOC_XTENSA_SLOT14_ALT
6700 Alternate Xtensa relocations. Only the slot is encoded in the
6701 relocation. The meaning of these relocations is opcode-specific.
6703 BFD_RELOC_XTENSA_OP0
6705 BFD_RELOC_XTENSA_OP1
6707 BFD_RELOC_XTENSA_OP2
6709 Xtensa relocations for backward compatibility. These have all been
6710 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6712 BFD_RELOC_XTENSA_ASM_EXPAND
6714 Xtensa relocation to mark that the assembler expanded the
6715 instructions from an original target. The expansion size is
6716 encoded in the reloc size.
6718 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6720 Xtensa relocation to mark that the linker should simplify
6721 assembler-expanded instructions. This is commonly used
6722 internally by the linker after analysis of a
6723 BFD_RELOC_XTENSA_ASM_EXPAND.
6725 BFD_RELOC_XTENSA_TLSDESC_FN
6727 BFD_RELOC_XTENSA_TLSDESC_ARG
6729 BFD_RELOC_XTENSA_TLS_DTPOFF
6731 BFD_RELOC_XTENSA_TLS_TPOFF
6733 BFD_RELOC_XTENSA_TLS_FUNC
6735 BFD_RELOC_XTENSA_TLS_ARG
6737 BFD_RELOC_XTENSA_TLS_CALL
6739 Xtensa TLS relocations.
6744 8 bit signed offset in (ix+d) or (iy+d).
6762 BFD_RELOC_LM32_BRANCH
6764 BFD_RELOC_LM32_16_GOT
6766 BFD_RELOC_LM32_GOTOFF_HI16
6768 BFD_RELOC_LM32_GOTOFF_LO16
6772 BFD_RELOC_LM32_GLOB_DAT
6774 BFD_RELOC_LM32_JMP_SLOT
6776 BFD_RELOC_LM32_RELATIVE
6778 Lattice Mico32 relocations.
6781 BFD_RELOC_MACH_O_SECTDIFF
6783 Difference between two section addreses. Must be followed by a
6784 BFD_RELOC_MACH_O_PAIR.
6786 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6788 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6790 BFD_RELOC_MACH_O_PAIR
6792 Pair of relocation. Contains the first symbol.
6794 BFD_RELOC_MACH_O_SUBTRACTOR32
6796 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6798 BFD_RELOC_MACH_O_SUBTRACTOR64
6800 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6803 BFD_RELOC_MACH_O_X86_64_BRANCH32
6805 BFD_RELOC_MACH_O_X86_64_BRANCH8
6807 PCREL relocations. They are marked as branch to create PLT entry if
6810 BFD_RELOC_MACH_O_X86_64_GOT
6812 Used when referencing a GOT entry.
6814 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6816 Used when loading a GOT entry with movq. It is specially marked so that
6817 the linker could optimize the movq to a leaq if possible.
6819 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6821 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6823 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6825 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6827 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6829 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6831 BFD_RELOC_MACH_O_X86_64_TLV
6833 Used when referencing a TLV entry.
6837 BFD_RELOC_MACH_O_ARM64_ADDEND
6839 Addend for PAGE or PAGEOFF.
6841 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6843 Relative offset to page of GOT slot.
6845 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6847 Relative offset within page of GOT slot.
6849 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6851 Address of a GOT entry.
6854 BFD_RELOC_MICROBLAZE_32_LO
6856 This is a 32 bit reloc for the microblaze that stores the
6857 low 16 bits of a value
6859 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6861 This is a 32 bit pc-relative reloc for the microblaze that
6862 stores the low 16 bits of a value
6864 BFD_RELOC_MICROBLAZE_32_ROSDA
6866 This is a 32 bit reloc for the microblaze that stores a
6867 value relative to the read-only small data area anchor
6869 BFD_RELOC_MICROBLAZE_32_RWSDA
6871 This is a 32 bit reloc for the microblaze that stores a
6872 value relative to the read-write small data area anchor
6874 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6876 This is a 32 bit reloc for the microblaze to handle
6877 expressions of the form "Symbol Op Symbol"
6879 BFD_RELOC_MICROBLAZE_64_NONE
6881 This is a 64 bit reloc that stores the 32 bit pc relative
6882 value in two words (with an imm instruction). No relocation is
6883 done here - only used for relaxing
6885 BFD_RELOC_MICROBLAZE_64_GOTPC
6887 This is a 64 bit reloc that stores the 32 bit pc relative
6888 value in two words (with an imm instruction). The relocation is
6889 PC-relative GOT offset
6891 BFD_RELOC_MICROBLAZE_64_GOT
6893 This is a 64 bit reloc that stores the 32 bit pc relative
6894 value in two words (with an imm instruction). The relocation is
6897 BFD_RELOC_MICROBLAZE_64_PLT
6899 This is a 64 bit reloc that stores the 32 bit pc relative
6900 value in two words (with an imm instruction). The relocation is
6901 PC-relative offset into PLT
6903 BFD_RELOC_MICROBLAZE_64_GOTOFF
6905 This is a 64 bit reloc that stores the 32 bit GOT relative
6906 value in two words (with an imm instruction). The relocation is
6907 relative offset from _GLOBAL_OFFSET_TABLE_
6909 BFD_RELOC_MICROBLAZE_32_GOTOFF
6911 This is a 32 bit reloc that stores the 32 bit GOT relative
6912 value in a word. The relocation is relative offset from
6913 _GLOBAL_OFFSET_TABLE_
6915 BFD_RELOC_MICROBLAZE_COPY
6917 This is used to tell the dynamic linker to copy the value out of
6918 the dynamic object into the runtime process image.
6920 BFD_RELOC_MICROBLAZE_64_TLS
6924 BFD_RELOC_MICROBLAZE_64_TLSGD
6926 This is a 64 bit reloc that stores the 32 bit GOT relative value
6927 of the GOT TLS GD info entry in two words (with an imm instruction). The
6928 relocation is GOT offset.
6930 BFD_RELOC_MICROBLAZE_64_TLSLD
6932 This is a 64 bit reloc that stores the 32 bit GOT relative value
6933 of the GOT TLS LD info entry in two words (with an imm instruction). The
6934 relocation is GOT offset.
6936 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6938 This is a 32 bit reloc that stores the Module ID to GOT(n).
6940 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6942 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6944 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6946 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6949 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6951 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6952 to two words (uses imm instruction).
6954 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6956 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6957 to two words (uses imm instruction).
6959 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6961 This is a 64 bit reloc that stores the 32 bit pc relative
6962 value in two words (with an imm instruction). The relocation is
6963 PC-relative offset from start of TEXT.
6965 BFD_RELOC_MICROBLAZE_64_TEXTREL
6967 This is a 64 bit reloc that stores the 32 bit offset
6968 value in two words (with an imm instruction). The relocation is
6969 relative offset from start of TEXT.
6972 BFD_RELOC_AARCH64_RELOC_START
6974 AArch64 pseudo relocation code to mark the start of the AArch64
6975 relocation enumerators. N.B. the order of the enumerators is
6976 important as several tables in the AArch64 bfd backend are indexed
6977 by these enumerators; make sure they are all synced.
6979 BFD_RELOC_AARCH64_NULL
6981 Deprecated AArch64 null relocation code.
6983 BFD_RELOC_AARCH64_NONE
6985 AArch64 null relocation code.
6987 BFD_RELOC_AARCH64_64
6989 BFD_RELOC_AARCH64_32
6991 BFD_RELOC_AARCH64_16
6993 Basic absolute relocations of N bits. These are equivalent to
6994 BFD_RELOC_N and they were added to assist the indexing of the howto
6997 BFD_RELOC_AARCH64_64_PCREL
6999 BFD_RELOC_AARCH64_32_PCREL
7001 BFD_RELOC_AARCH64_16_PCREL
7003 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
7004 and they were added to assist the indexing of the howto table.
7006 BFD_RELOC_AARCH64_MOVW_G0
7008 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7009 of an unsigned address/value.
7011 BFD_RELOC_AARCH64_MOVW_G0_NC
7013 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7014 an address/value. No overflow checking.
7016 BFD_RELOC_AARCH64_MOVW_G1
7018 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7019 of an unsigned address/value.
7021 BFD_RELOC_AARCH64_MOVW_G1_NC
7023 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7024 of an address/value. No overflow checking.
7026 BFD_RELOC_AARCH64_MOVW_G2
7028 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7029 of an unsigned address/value.
7031 BFD_RELOC_AARCH64_MOVW_G2_NC
7033 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7034 of an address/value. No overflow checking.
7036 BFD_RELOC_AARCH64_MOVW_G3
7038 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7039 of a signed or unsigned address/value.
7041 BFD_RELOC_AARCH64_MOVW_G0_S
7043 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7044 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7047 BFD_RELOC_AARCH64_MOVW_G1_S
7049 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7050 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7053 BFD_RELOC_AARCH64_MOVW_G2_S
7055 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7056 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7059 BFD_RELOC_AARCH64_MOVW_PREL_G0
7061 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7062 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7065 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7067 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7068 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7071 BFD_RELOC_AARCH64_MOVW_PREL_G1
7073 AArch64 MOVK instruction with most significant bits 16 to 31
7076 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7078 AArch64 MOVK instruction with most significant bits 16 to 31
7081 BFD_RELOC_AARCH64_MOVW_PREL_G2
7083 AArch64 MOVK instruction with most significant bits 32 to 47
7086 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7088 AArch64 MOVK instruction with most significant bits 32 to 47
7091 BFD_RELOC_AARCH64_MOVW_PREL_G3
7093 AArch64 MOVK instruction with most significant bits 47 to 63
7096 BFD_RELOC_AARCH64_LD_LO19_PCREL
7098 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7099 offset. The lowest two bits must be zero and are not stored in the
7100 instruction, giving a 21 bit signed byte offset.
7102 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7104 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7106 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7108 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7109 offset, giving a 4KB aligned page base address.
7111 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7113 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7114 offset, giving a 4KB aligned page base address, but with no overflow
7117 BFD_RELOC_AARCH64_ADD_LO12
7119 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7120 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7122 BFD_RELOC_AARCH64_LDST8_LO12
7124 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7125 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7127 BFD_RELOC_AARCH64_TSTBR14
7129 AArch64 14 bit pc-relative test bit and branch.
7130 The lowest two bits must be zero and are not stored in the instruction,
7131 giving a 16 bit signed byte offset.
7133 BFD_RELOC_AARCH64_BRANCH19
7135 AArch64 19 bit pc-relative conditional branch and compare & branch.
7136 The lowest two bits must be zero and are not stored in the instruction,
7137 giving a 21 bit signed byte offset.
7139 BFD_RELOC_AARCH64_JUMP26
7141 AArch64 26 bit pc-relative unconditional branch.
7142 The lowest two bits must be zero and are not stored in the instruction,
7143 giving a 28 bit signed byte offset.
7145 BFD_RELOC_AARCH64_CALL26
7147 AArch64 26 bit pc-relative unconditional branch and link.
7148 The lowest two bits must be zero and are not stored in the instruction,
7149 giving a 28 bit signed byte offset.
7151 BFD_RELOC_AARCH64_LDST16_LO12
7153 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7154 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7156 BFD_RELOC_AARCH64_LDST32_LO12
7158 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7159 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7161 BFD_RELOC_AARCH64_LDST64_LO12
7163 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7164 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7166 BFD_RELOC_AARCH64_LDST128_LO12
7168 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7169 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7171 BFD_RELOC_AARCH64_GOT_LD_PREL19
7173 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7174 offset of the global offset table entry for a symbol. The lowest two
7175 bits must be zero and are not stored in the instruction, giving a 21
7176 bit signed byte offset. This relocation type requires signed overflow
7179 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7181 Get to the page base of the global offset table entry for a symbol as
7182 part of an ADRP instruction using a 21 bit PC relative value.Used in
7183 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7185 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7187 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7188 the GOT entry for this symbol. Used in conjunction with
7189 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7191 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7193 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7194 the GOT entry for this symbol. Used in conjunction with
7195 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7197 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7199 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7200 for this symbol. Valid in LP64 ABI only.
7202 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7204 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7205 for this symbol. Valid in LP64 ABI only.
7207 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7209 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7210 the GOT entry for this symbol. Valid in LP64 ABI only.
7212 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7214 Scaled 14 bit byte offset to the page base of the global offset table.
7216 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7218 Scaled 15 bit byte offset to the page base of the global offset table.
7220 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7222 Get to the page base of the global offset table entry for a symbols
7223 tls_index structure as part of an adrp instruction using a 21 bit PC
7224 relative value. Used in conjunction with
7225 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7227 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7229 AArch64 TLS General Dynamic
7231 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7233 Unsigned 12 bit byte offset to global offset table entry for a symbols
7234 tls_index structure. Used in conjunction with
7235 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7237 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7239 AArch64 TLS General Dynamic relocation.
7241 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7243 AArch64 TLS General Dynamic relocation.
7245 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7247 AArch64 TLS INITIAL EXEC relocation.
7249 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7251 AArch64 TLS INITIAL EXEC relocation.
7253 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7255 AArch64 TLS INITIAL EXEC relocation.
7257 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7259 AArch64 TLS INITIAL EXEC relocation.
7261 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7263 AArch64 TLS INITIAL EXEC relocation.
7265 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7267 AArch64 TLS INITIAL EXEC relocation.
7269 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7271 bit[23:12] of byte offset to module TLS base address.
7273 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7275 Unsigned 12 bit byte offset to module TLS base address.
7277 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7279 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7281 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7283 Unsigned 12 bit byte offset to global offset table entry for a symbols
7284 tls_index structure. Used in conjunction with
7285 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7287 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7289 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7292 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7294 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7296 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7298 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7301 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7303 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7305 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7307 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7310 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7312 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7314 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7316 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7319 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7321 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7323 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7325 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7328 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7330 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7332 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7334 bit[15:0] of byte offset to module TLS base address.
7336 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7338 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7340 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7342 bit[31:16] of byte offset to module TLS base address.
7344 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7346 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7348 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7350 bit[47:32] of byte offset to module TLS base address.
7352 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7354 AArch64 TLS LOCAL EXEC relocation.
7356 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7358 AArch64 TLS LOCAL EXEC relocation.
7360 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7362 AArch64 TLS LOCAL EXEC relocation.
7364 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7366 AArch64 TLS LOCAL EXEC relocation.
7368 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7370 AArch64 TLS LOCAL EXEC relocation.
7372 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7374 AArch64 TLS LOCAL EXEC relocation.
7376 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7378 AArch64 TLS LOCAL EXEC relocation.
7380 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7382 AArch64 TLS LOCAL EXEC relocation.
7384 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7386 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7389 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7391 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7393 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7395 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7398 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7400 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7402 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7404 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7407 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7409 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7411 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7413 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7416 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7418 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7420 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7422 AArch64 TLS DESC relocation.
7424 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7426 AArch64 TLS DESC relocation.
7428 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7430 AArch64 TLS DESC relocation.
7432 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7434 AArch64 TLS DESC relocation.
7436 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7438 AArch64 TLS DESC relocation.
7440 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7442 AArch64 TLS DESC relocation.
7444 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7446 AArch64 TLS DESC relocation.
7448 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7450 AArch64 TLS DESC relocation.
7452 BFD_RELOC_AARCH64_TLSDESC_LDR
7454 AArch64 TLS DESC relocation.
7456 BFD_RELOC_AARCH64_TLSDESC_ADD
7458 AArch64 TLS DESC relocation.
7460 BFD_RELOC_AARCH64_TLSDESC_CALL
7462 AArch64 TLS DESC relocation.
7464 BFD_RELOC_AARCH64_COPY
7466 AArch64 TLS relocation.
7468 BFD_RELOC_AARCH64_GLOB_DAT
7470 AArch64 TLS relocation.
7472 BFD_RELOC_AARCH64_JUMP_SLOT
7474 AArch64 TLS relocation.
7476 BFD_RELOC_AARCH64_RELATIVE
7478 AArch64 TLS relocation.
7480 BFD_RELOC_AARCH64_TLS_DTPMOD
7482 AArch64 TLS relocation.
7484 BFD_RELOC_AARCH64_TLS_DTPREL
7486 AArch64 TLS relocation.
7488 BFD_RELOC_AARCH64_TLS_TPREL
7490 AArch64 TLS relocation.
7492 BFD_RELOC_AARCH64_TLSDESC
7494 AArch64 TLS relocation.
7496 BFD_RELOC_AARCH64_IRELATIVE
7498 AArch64 support for STT_GNU_IFUNC.
7500 BFD_RELOC_AARCH64_RELOC_END
7502 AArch64 pseudo relocation code to mark the end of the AArch64
7503 relocation enumerators that have direct mapping to ELF reloc codes.
7504 There are a few more enumerators after this one; those are mainly
7505 used by the AArch64 assembler for the internal fixup or to select
7506 one of the above enumerators.
7508 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7510 AArch64 pseudo relocation code to be used internally by the AArch64
7511 assembler and not (currently) written to any object files.
7513 BFD_RELOC_AARCH64_LDST_LO12
7515 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7516 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7518 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7520 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7521 used internally by the AArch64 assembler and not (currently) written to
7524 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7526 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7528 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7530 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7531 used internally by the AArch64 assembler and not (currently) written to
7534 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7536 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7538 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7540 AArch64 pseudo relocation code to be used internally by the AArch64
7541 assembler and not (currently) written to any object files.
7543 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7545 AArch64 pseudo relocation code to be used internally by the AArch64
7546 assembler and not (currently) written to any object files.
7548 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7550 AArch64 pseudo relocation code to be used internally by the AArch64
7551 assembler and not (currently) written to any object files.
7553 BFD_RELOC_TILEPRO_COPY
7555 BFD_RELOC_TILEPRO_GLOB_DAT
7557 BFD_RELOC_TILEPRO_JMP_SLOT
7559 BFD_RELOC_TILEPRO_RELATIVE
7561 BFD_RELOC_TILEPRO_BROFF_X1
7563 BFD_RELOC_TILEPRO_JOFFLONG_X1
7565 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7567 BFD_RELOC_TILEPRO_IMM8_X0
7569 BFD_RELOC_TILEPRO_IMM8_Y0
7571 BFD_RELOC_TILEPRO_IMM8_X1
7573 BFD_RELOC_TILEPRO_IMM8_Y1
7575 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7577 BFD_RELOC_TILEPRO_MT_IMM15_X1
7579 BFD_RELOC_TILEPRO_MF_IMM15_X1
7581 BFD_RELOC_TILEPRO_IMM16_X0
7583 BFD_RELOC_TILEPRO_IMM16_X1
7585 BFD_RELOC_TILEPRO_IMM16_X0_LO
7587 BFD_RELOC_TILEPRO_IMM16_X1_LO
7589 BFD_RELOC_TILEPRO_IMM16_X0_HI
7591 BFD_RELOC_TILEPRO_IMM16_X1_HI
7593 BFD_RELOC_TILEPRO_IMM16_X0_HA
7595 BFD_RELOC_TILEPRO_IMM16_X1_HA
7597 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7599 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7601 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7603 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7605 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7607 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7609 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7611 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7613 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7615 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7617 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7619 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7621 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7623 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7625 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7627 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7629 BFD_RELOC_TILEPRO_MMSTART_X0
7631 BFD_RELOC_TILEPRO_MMEND_X0
7633 BFD_RELOC_TILEPRO_MMSTART_X1
7635 BFD_RELOC_TILEPRO_MMEND_X1
7637 BFD_RELOC_TILEPRO_SHAMT_X0
7639 BFD_RELOC_TILEPRO_SHAMT_X1
7641 BFD_RELOC_TILEPRO_SHAMT_Y0
7643 BFD_RELOC_TILEPRO_SHAMT_Y1
7645 BFD_RELOC_TILEPRO_TLS_GD_CALL
7647 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7649 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7651 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7653 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7655 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7657 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7659 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7661 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7663 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7665 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7667 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7669 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7671 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7673 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7675 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7677 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7679 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7681 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7683 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7685 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7687 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7689 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7691 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7693 BFD_RELOC_TILEPRO_TLS_TPOFF32
7695 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7697 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7699 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7701 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7703 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7705 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7707 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7709 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7711 Tilera TILEPro Relocations.
7713 BFD_RELOC_TILEGX_HW0
7715 BFD_RELOC_TILEGX_HW1
7717 BFD_RELOC_TILEGX_HW2
7719 BFD_RELOC_TILEGX_HW3
7721 BFD_RELOC_TILEGX_HW0_LAST
7723 BFD_RELOC_TILEGX_HW1_LAST
7725 BFD_RELOC_TILEGX_HW2_LAST
7727 BFD_RELOC_TILEGX_COPY
7729 BFD_RELOC_TILEGX_GLOB_DAT
7731 BFD_RELOC_TILEGX_JMP_SLOT
7733 BFD_RELOC_TILEGX_RELATIVE
7735 BFD_RELOC_TILEGX_BROFF_X1
7737 BFD_RELOC_TILEGX_JUMPOFF_X1
7739 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7741 BFD_RELOC_TILEGX_IMM8_X0
7743 BFD_RELOC_TILEGX_IMM8_Y0
7745 BFD_RELOC_TILEGX_IMM8_X1
7747 BFD_RELOC_TILEGX_IMM8_Y1
7749 BFD_RELOC_TILEGX_DEST_IMM8_X1
7751 BFD_RELOC_TILEGX_MT_IMM14_X1
7753 BFD_RELOC_TILEGX_MF_IMM14_X1
7755 BFD_RELOC_TILEGX_MMSTART_X0
7757 BFD_RELOC_TILEGX_MMEND_X0
7759 BFD_RELOC_TILEGX_SHAMT_X0
7761 BFD_RELOC_TILEGX_SHAMT_X1
7763 BFD_RELOC_TILEGX_SHAMT_Y0
7765 BFD_RELOC_TILEGX_SHAMT_Y1
7767 BFD_RELOC_TILEGX_IMM16_X0_HW0
7769 BFD_RELOC_TILEGX_IMM16_X1_HW0
7771 BFD_RELOC_TILEGX_IMM16_X0_HW1
7773 BFD_RELOC_TILEGX_IMM16_X1_HW1
7775 BFD_RELOC_TILEGX_IMM16_X0_HW2
7777 BFD_RELOC_TILEGX_IMM16_X1_HW2
7779 BFD_RELOC_TILEGX_IMM16_X0_HW3
7781 BFD_RELOC_TILEGX_IMM16_X1_HW3
7783 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7785 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7787 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7789 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7791 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7793 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7795 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7797 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7799 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7801 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7803 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7805 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7817 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7819 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7821 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7823 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7825 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7827 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7829 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7831 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7833 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7835 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7837 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7839 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7841 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7843 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7845 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7847 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7849 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7851 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7853 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7855 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7857 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7859 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7861 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7863 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7865 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7867 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7869 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7871 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7873 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7875 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7877 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7879 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7881 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7883 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7885 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7887 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7889 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7891 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7893 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7895 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7897 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7899 BFD_RELOC_TILEGX_TLS_DTPMOD64
7901 BFD_RELOC_TILEGX_TLS_DTPOFF64
7903 BFD_RELOC_TILEGX_TLS_TPOFF64
7905 BFD_RELOC_TILEGX_TLS_DTPMOD32
7907 BFD_RELOC_TILEGX_TLS_DTPOFF32
7909 BFD_RELOC_TILEGX_TLS_TPOFF32
7911 BFD_RELOC_TILEGX_TLS_GD_CALL
7913 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7915 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7917 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7919 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7921 BFD_RELOC_TILEGX_TLS_IE_LOAD
7923 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7925 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7927 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7929 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7931 Tilera TILE-Gx Relocations.
7940 BFD_RELOC_BPF_DISP16
7942 BFD_RELOC_BPF_DISP32
7944 Linux eBPF relocations.
7947 BFD_RELOC_EPIPHANY_SIMM8
7949 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7951 BFD_RELOC_EPIPHANY_SIMM24
7953 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7955 BFD_RELOC_EPIPHANY_HIGH
7957 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7959 BFD_RELOC_EPIPHANY_LOW
7961 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7963 BFD_RELOC_EPIPHANY_SIMM11
7965 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7967 BFD_RELOC_EPIPHANY_IMM11
7969 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7971 BFD_RELOC_EPIPHANY_IMM8
7973 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7976 BFD_RELOC_VISIUM_HI16
7978 BFD_RELOC_VISIUM_LO16
7980 BFD_RELOC_VISIUM_IM16
7982 BFD_RELOC_VISIUM_REL16
7984 BFD_RELOC_VISIUM_HI16_PCREL
7986 BFD_RELOC_VISIUM_LO16_PCREL
7988 BFD_RELOC_VISIUM_IM16_PCREL
7993 BFD_RELOC_WASM32_LEB128
7995 BFD_RELOC_WASM32_LEB128_GOT
7997 BFD_RELOC_WASM32_LEB128_GOT_CODE
7999 BFD_RELOC_WASM32_LEB128_PLT
8001 BFD_RELOC_WASM32_PLT_INDEX
8003 BFD_RELOC_WASM32_ABS32_CODE
8005 BFD_RELOC_WASM32_COPY
8007 BFD_RELOC_WASM32_CODE_POINTER
8009 BFD_RELOC_WASM32_INDEX
8011 BFD_RELOC_WASM32_PLT_SIG
8013 WebAssembly relocations.
8016 BFD_RELOC_CKCORE_NONE
8018 BFD_RELOC_CKCORE_ADDR32
8020 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8022 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8024 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8026 BFD_RELOC_CKCORE_PCREL32
8028 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8030 BFD_RELOC_CKCORE_GNU_VTINHERIT
8032 BFD_RELOC_CKCORE_GNU_VTENTRY
8034 BFD_RELOC_CKCORE_RELATIVE
8036 BFD_RELOC_CKCORE_COPY
8038 BFD_RELOC_CKCORE_GLOB_DAT
8040 BFD_RELOC_CKCORE_JUMP_SLOT
8042 BFD_RELOC_CKCORE_GOTOFF
8044 BFD_RELOC_CKCORE_GOTPC
8046 BFD_RELOC_CKCORE_GOT32
8048 BFD_RELOC_CKCORE_PLT32
8050 BFD_RELOC_CKCORE_ADDRGOT
8052 BFD_RELOC_CKCORE_ADDRPLT
8054 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8056 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8058 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8060 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8062 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8064 BFD_RELOC_CKCORE_ADDR_HI16
8066 BFD_RELOC_CKCORE_ADDR_LO16
8068 BFD_RELOC_CKCORE_GOTPC_HI16
8070 BFD_RELOC_CKCORE_GOTPC_LO16
8072 BFD_RELOC_CKCORE_GOTOFF_HI16
8074 BFD_RELOC_CKCORE_GOTOFF_LO16
8076 BFD_RELOC_CKCORE_GOT12
8078 BFD_RELOC_CKCORE_GOT_HI16
8080 BFD_RELOC_CKCORE_GOT_LO16
8082 BFD_RELOC_CKCORE_PLT12
8084 BFD_RELOC_CKCORE_PLT_HI16
8086 BFD_RELOC_CKCORE_PLT_LO16
8088 BFD_RELOC_CKCORE_ADDRGOT_HI16
8090 BFD_RELOC_CKCORE_ADDRGOT_LO16
8092 BFD_RELOC_CKCORE_ADDRPLT_HI16
8094 BFD_RELOC_CKCORE_ADDRPLT_LO16
8096 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8098 BFD_RELOC_CKCORE_TOFFSET_LO16
8100 BFD_RELOC_CKCORE_DOFFSET_LO16
8102 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8104 BFD_RELOC_CKCORE_DOFFSET_IMM18
8106 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8108 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8110 BFD_RELOC_CKCORE_GOTOFF_IMM18
8112 BFD_RELOC_CKCORE_GOT_IMM18BY4
8114 BFD_RELOC_CKCORE_PLT_IMM18BY4
8116 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8118 BFD_RELOC_CKCORE_TLS_LE32
8120 BFD_RELOC_CKCORE_TLS_IE32
8122 BFD_RELOC_CKCORE_TLS_GD32
8124 BFD_RELOC_CKCORE_TLS_LDM32
8126 BFD_RELOC_CKCORE_TLS_LDO32
8128 BFD_RELOC_CKCORE_TLS_DTPMOD32
8130 BFD_RELOC_CKCORE_TLS_DTPOFF32
8132 BFD_RELOC_CKCORE_TLS_TPOFF32
8134 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8136 BFD_RELOC_CKCORE_NOJSRI
8138 BFD_RELOC_CKCORE_CALLGRAPH
8140 BFD_RELOC_CKCORE_IRELATIVE
8142 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8144 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8157 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8162 bfd_reloc_type_lookup
8163 bfd_reloc_name_lookup
8166 reloc_howto_type *bfd_reloc_type_lookup
8167 (bfd *abfd, bfd_reloc_code_real_type code);
8168 reloc_howto_type *bfd_reloc_name_lookup
8169 (bfd *abfd, const char *reloc_name);
8172 Return a pointer to a howto structure which, when
8173 invoked, will perform the relocation @var{code} on data from the
8179 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8181 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8185 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8187 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8190 static reloc_howto_type bfd_howto_32
=
8191 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8195 bfd_default_reloc_type_lookup
8198 reloc_howto_type *bfd_default_reloc_type_lookup
8199 (bfd *abfd, bfd_reloc_code_real_type code);
8202 Provides a default relocation lookup routine for any architecture.
8207 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8211 case BFD_RELOC_CTOR
:
8212 /* The type of reloc used in a ctor, which will be as wide as the
8213 address - so either a 64, 32, or 16 bitter. */
8214 switch (bfd_arch_bits_per_address (abfd
))
8220 return &bfd_howto_32
;
8236 bfd_get_reloc_code_name
8239 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8242 Provides a printable name for the supplied relocation code.
8243 Useful mainly for printing error messages.
8247 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8249 if (code
> BFD_RELOC_UNUSED
)
8251 return bfd_reloc_code_real_names
[code
];
8256 bfd_generic_relax_section
8259 bfd_boolean bfd_generic_relax_section
8262 struct bfd_link_info *,
8266 Provides default handling for relaxing for back ends which
8271 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8272 asection
*section ATTRIBUTE_UNUSED
,
8273 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8276 if (bfd_link_relocatable (link_info
))
8277 (*link_info
->callbacks
->einfo
)
8278 (_("%P%F: --relax and -r may not be used together\n"));
8286 bfd_generic_gc_sections
8289 bfd_boolean bfd_generic_gc_sections
8290 (bfd *, struct bfd_link_info *);
8293 Provides default handling for relaxing for back ends which
8294 don't do section gc -- i.e., does nothing.
8298 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8299 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8306 bfd_generic_lookup_section_flags
8309 bfd_boolean bfd_generic_lookup_section_flags
8310 (struct bfd_link_info *, struct flag_info *, asection *);
8313 Provides default handling for section flags lookup
8314 -- i.e., does nothing.
8315 Returns FALSE if the section should be omitted, otherwise TRUE.
8319 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8320 struct flag_info
*flaginfo
,
8321 asection
*section ATTRIBUTE_UNUSED
)
8323 if (flaginfo
!= NULL
)
8325 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8333 bfd_generic_merge_sections
8336 bfd_boolean bfd_generic_merge_sections
8337 (bfd *, struct bfd_link_info *);
8340 Provides default handling for SEC_MERGE section merging for back ends
8341 which don't have SEC_MERGE support -- i.e., does nothing.
8345 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8346 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8353 bfd_generic_get_relocated_section_contents
8356 bfd_byte *bfd_generic_get_relocated_section_contents
8358 struct bfd_link_info *link_info,
8359 struct bfd_link_order *link_order,
8361 bfd_boolean relocatable,
8365 Provides default handling of relocation effort for back ends
8366 which can't be bothered to do it efficiently.
8371 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8372 struct bfd_link_info
*link_info
,
8373 struct bfd_link_order
*link_order
,
8375 bfd_boolean relocatable
,
8378 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8379 asection
*input_section
= link_order
->u
.indirect
.section
;
8381 arelent
**reloc_vector
;
8384 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8388 /* Read in the section. */
8389 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8395 if (reloc_size
== 0)
8398 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8399 if (reloc_vector
== NULL
)
8402 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8406 if (reloc_count
< 0)
8409 if (reloc_count
> 0)
8413 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8415 char *error_message
= NULL
;
8417 bfd_reloc_status_type r
;
8419 symbol
= *(*parent
)->sym_ptr_ptr
;
8420 /* PR ld/19628: A specially crafted input file
8421 can result in a NULL symbol pointer here. */
8424 link_info
->callbacks
->einfo
8425 /* xgettext:c-format */
8426 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8427 abfd
, input_section
, (* parent
)->address
);
8431 /* Zap reloc field when the symbol is from a discarded
8432 section, ignoring any addend. Do the same when called
8433 from bfd_simple_get_relocated_section_contents for
8434 undefined symbols in debug sections. This is to keep
8435 debug info reasonably sane, in particular so that
8436 DW_FORM_ref_addr to another file's .debug_info isn't
8437 confused with an offset into the current file's
8439 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8440 || (symbol
->section
== bfd_und_section_ptr
8441 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8442 && link_info
->input_bfds
== link_info
->output_bfd
))
8445 static reloc_howto_type none_howto
8446 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8447 "unused", FALSE
, 0, 0, FALSE
);
8449 off
= (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
8450 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8451 input_section
, data
, off
);
8452 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8453 (*parent
)->addend
= 0;
8454 (*parent
)->howto
= &none_howto
;
8458 r
= bfd_perform_relocation (input_bfd
,
8462 relocatable
? abfd
: NULL
,
8467 asection
*os
= input_section
->output_section
;
8469 /* A partial link, so keep the relocs. */
8470 os
->orelocation
[os
->reloc_count
] = *parent
;
8474 if (r
!= bfd_reloc_ok
)
8478 case bfd_reloc_undefined
:
8479 (*link_info
->callbacks
->undefined_symbol
)
8480 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8481 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8483 case bfd_reloc_dangerous
:
8484 BFD_ASSERT (error_message
!= NULL
);
8485 (*link_info
->callbacks
->reloc_dangerous
)
8486 (link_info
, error_message
,
8487 input_bfd
, input_section
, (*parent
)->address
);
8489 case bfd_reloc_overflow
:
8490 (*link_info
->callbacks
->reloc_overflow
)
8492 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8493 (*parent
)->howto
->name
, (*parent
)->addend
,
8494 input_bfd
, input_section
, (*parent
)->address
);
8496 case bfd_reloc_outofrange
:
8498 This error can result when processing some partially
8499 complete binaries. Do not abort, but issue an error
8501 link_info
->callbacks
->einfo
8502 /* xgettext:c-format */
8503 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8504 abfd
, input_section
, * parent
);
8507 case bfd_reloc_notsupported
:
8509 This error can result when processing a corrupt binary.
8510 Do not abort. Issue an error message instead. */
8511 link_info
->callbacks
->einfo
8512 /* xgettext:c-format */
8513 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8514 abfd
, input_section
, * parent
);
8518 /* PR 17512; file: 90c2a92e.
8519 Report unexpected results, without aborting. */
8520 link_info
->callbacks
->einfo
8521 /* xgettext:c-format */
8522 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8523 abfd
, input_section
, * parent
, r
);
8531 free (reloc_vector
);
8535 free (reloc_vector
);
8541 _bfd_generic_set_reloc
8544 void _bfd_generic_set_reloc
8548 unsigned int count);
8551 Installs a new set of internal relocations in SECTION.
8555 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8560 section
->orelocation
= relptr
;
8561 section
->reloc_count
= count
;
8566 _bfd_unrecognized_reloc
8569 bfd_boolean _bfd_unrecognized_reloc
8572 unsigned int r_type);
8575 Reports an unrecognized reloc.
8576 Written as a function in order to reduce code duplication.
8577 Returns FALSE so that it can be called from a return statement.
8581 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8583 /* xgettext:c-format */
8584 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8585 abfd
, r_type
, section
);
8587 /* PR 21803: Suggest the most likely cause of this error. */
8588 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8589 BFD_VERSION_STRING
);
8591 bfd_set_error (bfd_error_bad_value
);
8596 _bfd_norelocs_bfd_reloc_type_lookup
8598 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8600 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8604 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8605 const char *reloc_name ATTRIBUTE_UNUSED
)
8607 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8611 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8612 arelent
**relp ATTRIBUTE_UNUSED
,
8613 asymbol
**symp ATTRIBUTE_UNUSED
)
8615 return _bfd_long_bfd_n1_error (abfd
);