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1 /*
2 * (C) Copyright 2009-2012
3 * Jens Scharsig <esw@bus-elekronik.de>
4 * BuS Elektronik GmbH & Co. KG
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <linux/sizes.h>
12 #include <asm/io.h>
13 #include <asm/gpio.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/at91_matrix.h>
17 #include <asm/arch/at91sam9_smc.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_pio.h>
20 #include <asm/arch/at91sam9263.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/at91_common.h>
23 #include <lcd.h>
24 #include <i2c.h>
25 #include <atmel_lcdc.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
27 #include <net.h>
28 #endif
29 #include <netdev.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #ifdef CONFIG_CMD_NAND
34 static void vl_ma2sc_nand_hw_init(void)
35 {
36 unsigned long csa;
37 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
38 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
39 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
40
41 at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
42 at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
43 at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
44
45 /* Enable CS3 */
46 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
47 writel(csa, &matrix->csa[0]);
48
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
52 &smc->cs[3].setup);
53
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
56 &smc->cs[3].pulse);
57
58 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
59 &smc->cs[3].cycle);
60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
61 AT91_SMC_MODE_DBW_8 |
62 AT91_SMC_MODE_TDF_CYCLE(2),
63 &smc->cs[3].mode);
64 writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
65 &pmc->pcer);
66
67 /* Configure RDY/BSY */
68 #ifdef CONFIG_SYS_NAND_READY_PIN
69 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
70 #endif
71 /* Enable NandFlash */
72 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
73 }
74 #endif
75
76 #ifdef CONFIG_MACB
77 static void vl_ma2sc_macb_hw_init(void)
78 {
79 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
80
81 /* Enable clock */
82 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
83
84 at91_phy_reset();
85
86 at91_macb_hw_init();
87 }
88 #endif
89
90 #ifdef CONFIG_LCD
91 vidinfo_t panel_info = {
92 .vl_col = 320,
93 .vl_row = 240,
94 .vl_clk = 6500000,
95 .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
96 ATMEL_LCDC_INVLINE_INVERTED |
97 ATMEL_LCDC_INVVD_INVERTED |
98 ATMEL_LCDC_INVFRAME_INVERTED,
99 .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
100 .vl_tft = 1,
101 .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
102 .vl_left_margin = 68, /* horiz back porch */
103 .vl_right_margin = 20, /* horiz front porch */
104 .vl_vsync_len = 2, /* vert Sync Pulse Width */
105 .vl_upper_margin = 18, /* vert back porch */
106 .vl_lower_margin = 4, /* vert front porch */
107 .mmio = ATMEL_BASE_LCDC,
108 };
109
110 void lcd_enable(void)
111 {
112 }
113
114 void lcd_disable(void)
115 {
116 }
117
118 static void vl_ma2sc_lcd_hw_init(void)
119 {
120 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
121
122 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
123 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
124 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
125 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
126 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
127
128 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
129 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
130 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
131 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
132 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
133 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
134 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
135 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
136
137 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
138 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
139 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
140 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
141 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
142 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
143 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
144
145 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
146 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
147 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
148 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
149 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
150 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
151 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
152 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
153
154 at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
155
156 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
157 at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
158 at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
159 at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
160 at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
161 at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
162
163 at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
164
165 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
166 gd->fb_base = ATMEL_BASE_SRAM0;
167 }
168 #endif /* Config LCD */
169
170 #ifdef CONFIG_BOARD_EARLY_INIT_F
171 int board_early_init_f(void)
172 {
173 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
174
175 /* Enable clocks for all PIOs */
176 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
177 (1 << ATMEL_ID_PIOCDE),
178 &pmc->pcer);
179
180 at91_seriald_hw_init();
181
182 return 0;
183 }
184 #endif
185
186 int board_init(void)
187 {
188 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
189 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
190 u32 pin;
191
192 pin = 0x1F000001;
193 writel(pin, &pio->pioa.idr);
194 writel(pin, &pio->pioa.pudr);
195 writel(pin, &pio->pioa.per);
196 writel(pin, &pio->pioa.oer);
197 writel(pin, &pio->pioa.sodr);
198 writel((1 << 25), &pio->pioa.codr);
199
200 pin = 0x1F000100;
201 writel(pin, &pio->piob.idr);
202 writel(pin, &pio->piob.pudr);
203 writel(pin, &pio->piob.per);
204 writel(pin, &pio->piob.oer);
205 writel(pin, &pio->piob.codr);
206 writel((1 << 24), &pio->piob.sodr);
207
208 pin = 0x40000000; /* Pullup DRxD enbable */
209 writel(pin, &pio->pioc.puer);
210
211 pin = 0x0000000F; /* HWversion als Input */
212 writel(pin, &pio->piod.idr);
213 writel(pin, &pio->piod.puer);
214 writel(pin, &pio->piod.per);
215 writel(pin, &pio->piod.odr);
216 writel(pin, &pio->piod.owdr);
217
218 gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
219 /* adress of boot parameters */
220 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
221
222 writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
223 writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
224 writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
225 writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
226
227 #ifdef CONFIG_CMD_NAND
228 vl_ma2sc_nand_hw_init();
229 #endif
230 #ifdef CONFIG_MACB
231 vl_ma2sc_macb_hw_init();
232 #endif
233 #ifdef CONFIG_USB_OHCI_NEW
234 at91_uhp_hw_init();
235 #endif
236 #ifdef CONFIG_LCD
237 vl_ma2sc_lcd_hw_init();
238 #endif
239 return 0;
240 }
241
242 #ifdef CONFIG_MISC_INIT_R
243 int misc_init_r(void)
244 {
245 uchar buffer[8];
246 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
247 u32 pin;
248
249 buffer[0] = 0x04;
250 buffer[1] = 0x00;
251 if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
252 puts("error reseting rtc clock\n\0");
253
254 /* read hardware version */
255
256 pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
257 printf("Board: revision %c\n", pin);
258 buffer[0] = pin;
259 buffer[1] = 0;
260 setenv("revision", (char *) buffer);
261
262 pin = 0x40000000; /* Pullup DRxD enbable */
263 writel(pin, &pio->pioc.puer);
264 return 0;
265 }
266 #endif
267
268 int dram_init(void)
269 {
270 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
271 CONFIG_SYS_SDRAM_SIZE);
272 return 0;
273 }
274
275 #ifdef CONFIG_RESET_PHY_R
276 void reset_phy(void)
277 {
278 #ifdef CONFIG_MACB
279 /*
280 * Initialize ethernet HW addr prior to starting Linux,
281 * needed for nfsroot
282 */
283 eth_init();
284 #endif
285 }
286 #endif
287
288 int board_eth_init(bd_t *bis)
289 {
290 int rc = 0;
291 #ifdef CONFIG_MACB
292 rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
293 #endif
294 return rc;
295 }
296
297 #ifdef CONFIG_SYS_I2C_SOFT
298 void i2c_init_board(void)
299 {
300 u32 pin;
301
302 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
303 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
304 u8 sda = (1<<4);
305 u8 scl = (1<<5);
306
307 writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
308 pin = sda | scl;
309 writel(pin, &pio->piob.idr); /* Disable Interupt */
310 writel(pin, &pio->piob.pudr);
311 writel(pin, &pio->piob.per);
312 writel(pin, &pio->piob.oer);
313 writel(pin, &pio->piob.sodr);
314 }
315 #endif
316
317 void watchdog_reset(void)
318 {
319 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
320 u32 pin = 0x1; /* PA0 */
321
322 if ((readl(&pio->pioa.odsr) & pin) > 0)
323 writel(pin, &pio->pioa.codr);
324 else
325 writel(pin, &pio->pioa.sodr);
326 }
327
328 void enable_caches(void)
329 {
330 #ifndef CONFIG_SYS_DCACHE_OFF
331 dcache_enable();
332 #endif
333 }
334
335 /*---------------------------------------------------------------------------*/
336
337 int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
338 {
339 int rcode = 1;
340 int row;
341 int col;
342 u32 pinz;
343 u32 pins;
344 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
345
346 at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
347
348 pins = 0x1F000000;
349 writel(pins, &pio->pioa.idr);
350 writel(pins, &pio->pioa.pudr);
351 writel(pins, &pio->pioa.per);
352 writel(pins, &pio->pioa.oer);
353 writel(pins, &pio->pioa.sodr);
354
355 pinz = 0x1F000000;
356 writel(pinz, &pio->piob.idr);
357 writel(pinz, &pio->piob.pudr);
358 writel(pinz, &pio->piob.per);
359 writel(pinz, &pio->piob.oer);
360 writel(pinz, &pio->piob.sodr);
361
362 for (row = 0; row < 5; row++) {
363 for (col = 0; col < 5; col++) {
364 writel((0x01000000 << col), &pio->piob.sodr);
365 writel((0x01000000 << row), &pio->pioa.codr);
366 printf("LED Test %d x %d\n", row, col);
367 udelay(1000000);
368 writel(pinz, &pio->piob.codr);
369 writel(pins, &pio->pioa.sodr);
370 }
371 }
372 return rcode;
373 }
374
375 void poweroff(void)
376 {
377 watchdog_reset();
378 at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
379 udelay(100);
380 at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
381 udelay(100);
382 at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
383 udelay(100);
384 while (1)
385 watchdog_reset();
386 }
387
388 int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
389 {
390 int rcode = 1;
391 poweroff();
392 return rcode;
393 }
394
395 int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
396 {
397 int i;
398 u32 freq;
399 u32 durate;
400 int rcode = 1;
401
402 freq = 1000;
403 durate = 2;
404 switch (argc) {
405 case 3:
406 durate = simple_strtoul(argv[2], NULL, 10);
407 case 2:
408 freq = simple_strtoul(argv[1], NULL, 10);
409 case 1:
410 break;
411 default:
412 cmd_usage(cmdtp);
413 rcode = 1;
414 break;
415 }
416 durate = durate * freq;
417 freq = 500000 / freq;
418 for (i = 0; i < durate; i++) {
419 at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
420 udelay(freq);
421 at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
422 udelay(freq);
423 }
424 at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
425 return rcode;
426 }
427
428 int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
429 {
430 int rcode = 1;
431 int row;
432 u32 col;
433 u32 pinz;
434 u32 pins;
435 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
436 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
437
438 writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
439
440 pins = 0x001F0000;
441 writel(pins, &pio->pioa.idr);
442 writel(pins, &pio->pioa.pudr);
443 writel(pins, &pio->pioa.per);
444 writel(pins, &pio->pioa.odr);
445
446 pinz = 0x000F0000;
447 writel(pinz, &pio->piob.idr);
448 writel(pinz, &pio->piob.pudr);
449 writel(pinz, &pio->piob.per);
450 writel(pinz, &pio->piob.oer);
451 writel(pinz, &pio->piob.codr);
452
453 while (1) {
454 col = 0;
455 for (row = 0; row < 4; row++) {
456 writel((0x00010000 << row), &pio->piob.sodr);
457 udelay(10000);
458 col <<= 4;
459 col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
460 writel(pinz, &pio->piob.codr);
461 }
462 printf("Matix: ");
463 for (row = 0; row < 16; row++) {
464 printf("%1.1d", col & 1);
465 col >>= 1;
466 }
467 printf(" SP %d\r ",
468 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
469 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
470 /* SHUTDOWN */
471 row = 0;
472 while (row < 1000) {
473 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
474 row++;
475 udelay(100);
476 }
477 udelay(100000);
478 row = 0;
479 while (row < 1000) {
480 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
481 row++;
482 udelay(1000);
483 }
484 }
485 poweroff();
486 while (1)
487 ;
488 }
489 }
490 return rcode;
491 }
492
493 /*****************************************************************************/
494
495 U_BOOT_CMD(
496 ledtest, 1, 0, do_ledtest,
497 "test ledmatrix",
498 "\n"
499 );
500
501 U_BOOT_CMD(
502 keytest, 1, 0, do_keytest,
503 "test keymatix and special keys, poweroff on pressing ON key",
504 "\n"
505 );
506
507 U_BOOT_CMD(
508 poweroff, 1, 0, do_poweroff,
509 "power off",
510 "\n"
511 );
512
513 U_BOOT_CMD(
514 beep, 3, 0, do_beep,
515 "[freq [duration]]",
516 "freq frequence of beep\nduration duration of beep\n"
517 );
518
519 /*****************************************************************************/