board/CZ.NIC/turris_omnia/turris_omnia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Marek Behún <kabel@kernel.org>
   4  * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
   5  *
   6  * Derived from the code for
   7  *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <i2c.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <miiphy.h>
  16 #include <mtd.h>
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/soc.h>
  21 #include <dm/uclass.h>
  22 #include <fdt_support.h>
  23 #include <time.h>
  24 #include <linux/bitops.h>
  25 #include <u-boot/crc.h>
  26
  27 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  28 #include <../serdes/a38x/high_speed_env_spec.h>
  29 #include "../turris_atsha_otp.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define OMNIA_SPI_NOR_PATH              "/soc/spi@10600/spi-nor@0"
  34
  35 #define OMNIA_I2C_BUS_NAME              "i2c@11000->i2cmux@70->i2c@0"
  36
  37 #define OMNIA_I2C_MCU_CHIP_ADDR         0x2a
  38 #define OMNIA_I2C_MCU_CHIP_LEN          1
  39
  40 #define OMNIA_I2C_EEPROM_CHIP_ADDR      0x54
  41 #define OMNIA_I2C_EEPROM_CHIP_LEN       2
  42 #define OMNIA_I2C_EEPROM_MAGIC          0x0341a034
  43
  44 #define A385_SYS_RSTOUT_MASK            MVEBU_REGISTER(0x18260)
  45 #define   A385_SYS_RSTOUT_MASK_WD       BIT(10)
  46
  47 #define A385_WDT_GLOBAL_CTRL            MVEBU_REGISTER(0x20300)
  48 #define   A385_WDT_GLOBAL_RATIO_MASK    GENMASK(18, 16)
  49 #define   A385_WDT_GLOBAL_RATIO_SHIFT   16
  50 #define   A385_WDT_GLOBAL_25MHZ         BIT(10)
  51 #define   A385_WDT_GLOBAL_ENABLE        BIT(8)
  52
  53 #define A385_WDT_GLOBAL_STATUS          MVEBU_REGISTER(0x20304)
  54 #define   A385_WDT_GLOBAL_EXPIRED       BIT(31)
  55
  56 #define A385_WDT_DURATION               MVEBU_REGISTER(0x20334)
  57
  58 #define A385_WD_RSTOUT_UNMASK           MVEBU_REGISTER(0x20704)
  59 #define   A385_WD_RSTOUT_UNMASK_GLOBAL  BIT(8)
  60
  61 enum mcu_commands {
  62         CMD_GET_STATUS_WORD     = 0x01,
  63         CMD_GET_RESET           = 0x09,
  64         CMD_WATCHDOG_STATE      = 0x0b,
  65 };
  66
  67 enum status_word_bits {
  68         CARD_DET_STSBIT         = 0x0010,
  69         MSATA_IND_STSBIT        = 0x0020,
  70 };
  71
  72 /*
  73  * Those values and defines are taken from the Marvell U-Boot version
  74  * "u-boot-2013.01-2014_T3.0"
  75  */
  76 #define OMNIA_GPP_OUT_ENA_LOW                                   \
  77         (~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |  \
  78            BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |  \
  79            BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  80 #define OMNIA_GPP_OUT_ENA_MID                                   \
  81         (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |       \
  82            BIT(16) | BIT(17) | BIT(18)))
  83
  84 #define OMNIA_GPP_OUT_VAL_LOW   0x0
  85 #define OMNIA_GPP_OUT_VAL_MID   0x0
  86 #define OMNIA_GPP_POL_LOW       0x0
  87 #define OMNIA_GPP_POL_MID       0x0
  88
  89 static struct serdes_map board_serdes_map[] = {
  90         {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  91         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  92         {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  93         {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  94         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  95         {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  96 };
  97
  98 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  99                                           uint offset_len)
 100 {
 101         struct udevice *bus, *dev;
 102         int ret;
 103
 104         ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
 105         if (ret) {
 106                 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
 107                        OMNIA_I2C_BUS_NAME, ret);
 108                 return NULL;
 109         }
 110
 111         ret = i2c_get_chip(bus, addr, offset_len, &dev);
 112         if (ret) {
 113                 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
 114                        name, ret);
 115                 return NULL;
 116         }
 117
 118         return dev;
 119 }
 120
 121 static int omnia_mcu_read(u8 cmd, void *buf, int len)
 122 {
 123         struct udevice *chip;
 124
 125         chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
 126                                   OMNIA_I2C_MCU_CHIP_LEN);
 127         if (!chip)
 128                 return -ENODEV;
 129
 130         return dm_i2c_read(chip, cmd, buf, len);
 131 }
 132
 133 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
 134 {
 135         struct udevice *chip;
 136
 137         chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
 138                                   OMNIA_I2C_MCU_CHIP_LEN);
 139         if (!chip)
 140                 return -ENODEV;
 141
 142         return dm_i2c_write(chip, cmd, buf, len);
 143 }
 144
 145 static void enable_a385_watchdog(unsigned int timeout_minutes)
 146 {
 147         struct sar_freq_modes sar_freq;
 148         u32 watchdog_freq;
 149
 150         printf("Enabling A385 watchdog with %u minutes timeout...\n",
 151                timeout_minutes);
 152
 153         /*
 154          * Use NBCLK clock (a.k.a. L2 clock) as watchdog input clock with
 155          * its maximal ratio 7 instead of default fixed 25 MHz clock.
 156          * It allows to set watchdog duration up to the 22 minutes.
 157          */
 158         clrsetbits_32(A385_WDT_GLOBAL_CTRL,
 159                       A385_WDT_GLOBAL_25MHZ | A385_WDT_GLOBAL_RATIO_MASK,
 160                       7 << A385_WDT_GLOBAL_RATIO_SHIFT);
 161
 162         /*
 163          * Calculate watchdog clock frequency. It is defined by formula:
 164          *   freq = NBCLK / 2 / (2 ^ ratio)
 165          * We set ratio to the maximal possible value 7.
 166          */
 167         get_sar_freq(&sar_freq);
 168         watchdog_freq = sar_freq.nb_clk * 1000000 / 2 / (1 << 7);
 169
 170         /* Set watchdog duration */
 171         writel(timeout_minutes * 60 * watchdog_freq, A385_WDT_DURATION);
 172
 173         /* Clear the watchdog expiration bit */
 174         clrbits_32(A385_WDT_GLOBAL_STATUS, A385_WDT_GLOBAL_EXPIRED);
 175
 176         /* Enable watchdog timer */
 177         setbits_32(A385_WDT_GLOBAL_CTRL, A385_WDT_GLOBAL_ENABLE);
 178
 179         /* Enable reset on watchdog */
 180         setbits_32(A385_WD_RSTOUT_UNMASK, A385_WD_RSTOUT_UNMASK_GLOBAL);
 181
 182         /* Unmask reset for watchdog */
 183         clrbits_32(A385_SYS_RSTOUT_MASK, A385_SYS_RSTOUT_MASK_WD);
 184 }
 185
 186 static bool disable_mcu_watchdog(void)
 187 {
 188         int ret;
 189
 190         puts("Disabling MCU watchdog... ");
 191
 192         ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
 193         if (ret) {
 194                 printf("omnia_mcu_write failed: %i\n", ret);
 195                 return false;
 196         }
 197
 198         puts("disabled\n");
 199
 200         return true;
 201 }
 202
 203 static bool omnia_detect_sata(const char *msata_slot)
 204 {
 205         int ret;
 206         u16 stsword;
 207
 208         puts("MiniPCIe/mSATA card detection... ");
 209
 210         if (msata_slot) {
 211                 if (strcmp(msata_slot, "pcie") == 0) {
 212                         puts("forced to MiniPCIe via env\n");
 213                         return false;
 214                 } else if (strcmp(msata_slot, "sata") == 0) {
 215                         puts("forced to mSATA via env\n");
 216                         return true;
 217                 } else if (strcmp(msata_slot, "auto") != 0) {
 218                         printf("unsupported env value '%s', fallback to... ", msata_slot);
 219                 }
 220         }
 221
 222         ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
 223         if (ret) {
 224                 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
 225                        ret);
 226                 return false;
 227         }
 228
 229         if (!(stsword & CARD_DET_STSBIT)) {
 230                 puts("none\n");
 231                 return false;
 232         }
 233
 234         if (stsword & MSATA_IND_STSBIT)
 235                 puts("mSATA\n");
 236         else
 237                 puts("MiniPCIe\n");
 238
 239         return stsword & MSATA_IND_STSBIT ? true : false;
 240 }
 241
 242 static bool omnia_detect_wwan_usb3(const char *wwan_slot)
 243 {
 244         puts("WWAN slot configuration... ");
 245
 246         if (wwan_slot && strcmp(wwan_slot, "usb3") == 0) {
 247                 puts("USB3.0\n");
 248                 return true;
 249         }
 250
 251         if (wwan_slot && strcmp(wwan_slot, "pcie") != 0)
 252                 printf("unsupported env value '%s', fallback to... ", wwan_slot);
 253
 254         puts("PCIe+USB2.0\n");
 255         return false;
 256 }
 257
 258 void *env_sf_get_env_addr(void)
 259 {
 260         /* SPI Flash is mapped to address 0xD4000000 only in SPL */
 261 #ifdef CONFIG_SPL_BUILD
 262         return (void *)0xD4000000 + CONFIG_ENV_OFFSET;
 263 #else
 264         return NULL;
 265 #endif
 266 }
 267
 268 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
 269 {
 270 #ifdef CONFIG_SPL_ENV_SUPPORT
 271         /* Do not use env_load() as malloc() pool is too small at this stage */
 272         bool has_env = (env_init() == 0);
 273 #endif
 274         const char *env_value = NULL;
 275
 276 #ifdef CONFIG_SPL_ENV_SUPPORT
 277         /* beware that env_get() returns static allocated memory */
 278         env_value = has_env ? env_get("omnia_msata_slot") : NULL;
 279 #endif
 280
 281         if (omnia_detect_sata(env_value)) {
 282                 /* Change SerDes for first mPCIe port (mSATA) from PCIe to SATA */
 283                 board_serdes_map[0].serdes_type = SATA0;
 284                 board_serdes_map[0].serdes_speed = SERDES_SPEED_6_GBPS;
 285                 board_serdes_map[0].serdes_mode = SERDES_DEFAULT_MODE;
 286         }
 287
 288 #ifdef CONFIG_SPL_ENV_SUPPORT
 289         /* beware that env_get() returns static allocated memory */
 290         env_value = has_env ? env_get("omnia_wwan_slot") : NULL;
 291 #endif
 292
 293         if (omnia_detect_wwan_usb3(env_value)) {
 294                 /* Disable SerDes for USB 3.0 pins on the front USB-A port */
 295                 board_serdes_map[1].serdes_type = DEFAULT_SERDES;
 296                 /* Change SerDes for third mPCIe port (WWAN) from PCIe to USB 3.0 */
 297                 board_serdes_map[4].serdes_type = USB3_HOST0;
 298                 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
 299                 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
 300         }
 301
 302         *serdes_map_array = board_serdes_map;
 303         *count = ARRAY_SIZE(board_serdes_map);
 304
 305         return 0;
 306 }
 307
 308 struct omnia_eeprom {
 309         u32 magic;
 310         u32 ramsize;
 311         char region[4];
 312         u32 crc;
 313 };
 314
 315 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
 316 {
 317         struct udevice *chip;
 318         u32 crc;
 319         int ret;
 320
 321         chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
 322                                   OMNIA_I2C_EEPROM_CHIP_LEN);
 323
 324         if (!chip)
 325                 return false;
 326
 327         ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
 328         if (ret) {
 329                 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
 330                 return false;
 331         }
 332
 333         if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
 334                 printf("bad EEPROM magic number (%08x, should be %08x)\n",
 335                        oep->magic, OMNIA_I2C_EEPROM_MAGIC);
 336                 return false;
 337         }
 338
 339         crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
 340         if (crc != oep->crc) {
 341                 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
 342                        oep->crc, crc);
 343                 return false;
 344         }
 345
 346         return true;
 347 }
 348
 349 static int omnia_get_ram_size_gb(void)
 350 {
 351         static int ram_size;
 352         struct omnia_eeprom oep;
 353
 354         if (!ram_size) {
 355                 /* Get the board config from EEPROM */
 356                 if (omnia_read_eeprom(&oep)) {
 357                         debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
 358
 359                         if (oep.ramsize == 0x2)
 360                                 ram_size = 2;
 361                         else
 362                                 ram_size = 1;
 363                 } else {
 364                         /* Hardcoded fallback */
 365                         puts("Memory config from EEPROM read failed!\n");
 366                         puts("Falling back to default 1 GiB!\n");
 367                         ram_size = 1;
 368                 }
 369         }
 370
 371         return ram_size;
 372 }
 373
 374 /*
 375  * Define the DDR layout / topology here in the board file. This will
 376  * be used by the DDR3 init code in the SPL U-Boot version to configure
 377  * the DDR3 controller.
 378  */
 379 static struct mv_ddr_topology_map board_topology_map_1g = {
 380         DEBUG_LEVEL_ERROR,
 381         0x1, /* active interfaces */
 382         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
 383         { { { {0x1, 0, 0, 0},
 384               {0x1, 0, 0, 0},
 385               {0x1, 0, 0, 0},
 386               {0x1, 0, 0, 0},
 387               {0x1, 0, 0, 0} },
 388             SPEED_BIN_DDR_1600K,        /* speed_bin */
 389             MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
 390             MV_DDR_DIE_CAP_4GBIT,                       /* mem_size */
 391             MV_DDR_FREQ_800,            /* frequency */
 392             0, 0,                       /* cas_wl cas_l */
 393             MV_DDR_TEMP_NORMAL,         /* temperature */
 394             MV_DDR_TIM_2T} },           /* timing */
 395         BUS_MASK_32BIT,                 /* Busses mask */
 396         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
 397         NOT_COMBINED,                   /* ddr twin-die combined */
 398         { {0} },                        /* raw spd data */
 399         {0}                             /* timing parameters */
 400 };
 401
 402 static struct mv_ddr_topology_map board_topology_map_2g = {
 403         DEBUG_LEVEL_ERROR,
 404         0x1, /* active interfaces */
 405         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
 406         { { { {0x1, 0, 0, 0},
 407               {0x1, 0, 0, 0},
 408               {0x1, 0, 0, 0},
 409               {0x1, 0, 0, 0},
 410               {0x1, 0, 0, 0} },
 411             SPEED_BIN_DDR_1600K,        /* speed_bin */
 412             MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
 413             MV_DDR_DIE_CAP_8GBIT,                       /* mem_size */
 414             MV_DDR_FREQ_800,            /* frequency */
 415             0, 0,                       /* cas_wl cas_l */
 416             MV_DDR_TEMP_NORMAL,         /* temperature */
 417             MV_DDR_TIM_2T} },           /* timing */
 418         BUS_MASK_32BIT,                 /* Busses mask */
 419         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
 420         NOT_COMBINED,                   /* ddr twin-die combined */
 421         { {0} },                        /* raw spd data */
 422         {0}                             /* timing parameters */
 423 };
 424
 425 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 426 {
 427         if (omnia_get_ram_size_gb() == 2)
 428                 return &board_topology_map_2g;
 429         else
 430                 return &board_topology_map_1g;
 431 }
 432
 433 static int set_regdomain(void)
 434 {
 435         struct omnia_eeprom oep;
 436         char rd[3] = {' ', ' ', 0};
 437
 438         if (omnia_read_eeprom(&oep))
 439                 memcpy(rd, &oep.region, 2);
 440         else
 441                 puts("EEPROM regdomain read failed.\n");
 442
 443         printf("Regdomain set to %s\n", rd);
 444         return env_set("regdomain", rd);
 445 }
 446
 447 static void handle_reset_button(void)
 448 {
 449         const char * const vars[1] = { "bootcmd_rescue", };
 450         int ret;
 451         u8 reset_status;
 452
 453         /*
 454          * Ensure that bootcmd_rescue has always stock value, so that running
 455          *   run bootcmd_rescue
 456          * always works correctly.
 457          */
 458         env_set_default_vars(1, (char * const *)vars, 0);
 459
 460         ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
 461         if (ret) {
 462                 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
 463                        ret);
 464                 return;
 465         }
 466
 467         env_set_ulong("omnia_reset", reset_status);
 468
 469         if (reset_status) {
 470                 const char * const vars[2] = {
 471                         "bootcmd",
 472                         "distro_bootcmd",
 473                 };
 474
 475                 /*
 476                  * Set the above envs to their default values, in case the user
 477                  * managed to break them.
 478                  */
 479                 env_set_default_vars(2, (char * const *)vars, 0);
 480
 481                 /* Ensure bootcmd_rescue is used by distroboot */
 482                 env_set("boot_targets", "rescue");
 483
 484                 printf("RESET button was pressed, overwriting boot_targets!\n");
 485         } else {
 486                 /*
 487                  * In case the user somehow managed to save environment with
 488                  * boot_targets=rescue, reset boot_targets to default value.
 489                  * This could happen in subsequent commands if bootcmd_rescue
 490                  * failed.
 491                  */
 492                 if (!strcmp(env_get("boot_targets"), "rescue")) {
 493                         const char * const vars[1] = {
 494                                 "boot_targets",
 495                         };
 496
 497                         env_set_default_vars(1, (char * const *)vars, 0);
 498                 }
 499         }
 500 }
 501
 502 int board_early_init_f(void)
 503 {
 504         /* Configure MPP */
 505         writel(0x11111111, MVEBU_MPP_BASE + 0x00);
 506         writel(0x11111111, MVEBU_MPP_BASE + 0x04);
 507         writel(0x11244011, MVEBU_MPP_BASE + 0x08);
 508         writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
 509         writel(0x22200002, MVEBU_MPP_BASE + 0x10);
 510         writel(0x30042022, MVEBU_MPP_BASE + 0x14);
 511         writel(0x55550555, MVEBU_MPP_BASE + 0x18);
 512         writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
 513
 514         /* Set GPP Out value */
 515         writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 516         writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 517
 518         /* Set GPP Polarity */
 519         writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 520         writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 521
 522         /* Set GPP Out Enable */
 523         writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 524         writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 525
 526         return 0;
 527 }
 528
 529 void spl_board_init(void)
 530 {
 531         /*
 532          * If booting from UART, disable MCU watchdog in SPL, since uploading
 533          * U-Boot proper can take too much time and trigger it. Instead enable
 534          * A385 watchdog with very high timeout (10 minutes) to prevent hangup.
 535          */
 536         if (get_boot_device() == BOOT_DEVICE_UART) {
 537                 enable_a385_watchdog(10);
 538                 disable_mcu_watchdog();
 539         }
 540 }
 541
 542 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP)
 543
 544 static void disable_sata_node(void *blob)
 545 {
 546         int node;
 547
 548         fdt_for_each_node_by_compatible(node, blob, -1, "marvell,armada-380-ahci") {
 549                 if (!fdtdec_get_is_enabled(blob, node))
 550                         continue;
 551
 552                 if (fdt_status_disabled(blob, node) < 0)
 553                         printf("Cannot disable SATA DT node!\n");
 554                 else
 555                         debug("Disabled SATA DT node\n");
 556
 557                 return;
 558         }
 559
 560         printf("Cannot find SATA DT node!\n");
 561 }
 562
 563 static void disable_pcie_node(void *blob, int port)
 564 {
 565         int node;
 566
 567         fdt_for_each_node_by_compatible(node, blob, -1, "marvell,armada-370-pcie") {
 568                 int port_node;
 569
 570                 if (!fdtdec_get_is_enabled(blob, node))
 571                         continue;
 572
 573                 fdt_for_each_subnode (port_node, blob, node) {
 574                         if (!fdtdec_get_is_enabled(blob, port_node))
 575                                 continue;
 576
 577                         if (fdtdec_get_int(blob, port_node, "marvell,pcie-port", -1) != port)
 578                                 continue;
 579
 580                         if (fdt_status_disabled(blob, port_node) < 0)
 581                                 printf("Cannot disable PCIe port %d DT node!\n", port);
 582                         else
 583                                 debug("Disabled PCIe port %d DT node\n", port);
 584
 585                         return;
 586                 }
 587         }
 588
 589         printf("Cannot find PCIe port %d DT node!\n", port);
 590 }
 591
 592 static void fixup_msata_port_nodes(void *blob)
 593 {
 594         bool mode_sata;
 595
 596         /*
 597          * Determine if SerDes 0 is configured to SATA mode.
 598          * We do this instead of calling omnia_detect_sata() to avoid another
 599          * call to the MCU. By this time the common PHYs are initialized (it is
 600          * done in SPL), so we can read this common PHY register.
 601          */
 602         mode_sata = (readl(MVEBU_REGISTER(0x183fc)) & GENMASK(3, 0)) == 2;
 603
 604         /*
 605          * We're either adding status = "disabled" property, or changing
 606          * status = "okay" to status = "disabled". In both cases we'll need more
 607          * space. Increase the size a little.
 608          */
 609         if (fdt_increase_size(blob, 32) < 0) {
 610                 printf("Cannot increase FDT size!\n");
 611                 return;
 612         }
 613
 614         if (!mode_sata) {
 615                 /* If mSATA card is not present, disable SATA DT node */
 616                 disable_sata_node(blob);
 617         } else {
 618                 /* Otherwise disable PCIe port 0 DT node (MiniPCIe / mSATA port) */
 619                 disable_pcie_node(blob, 0);
 620         }
 621 }
 622
 623 static void fixup_wwan_port_nodes(void *blob)
 624 {
 625         bool mode_usb3;
 626
 627         /* Determine if SerDes 4 is configured to USB3 mode */
 628         mode_usb3 = ((readl(MVEBU_REGISTER(0x183fc)) & GENMASK(19, 16)) >> 16) == 4;
 629
 630         /* If SerDes 4 is not configured to USB3 mode then nothing is needed to fixup */
 631         if (!mode_usb3)
 632                 return;
 633
 634         /*
 635          * We're either adding status = "disabled" property, or changing
 636          * status = "okay" to status = "disabled". In both cases we'll need more
 637          * space. Increase the size a little.
 638          */
 639         if (fdt_increase_size(blob, 32) < 0) {
 640                 printf("Cannot increase FDT size!\n");
 641                 return;
 642         }
 643
 644         /* Disable PCIe port 2 DT node (WWAN) */
 645         disable_pcie_node(blob, 2);
 646 }
 647
 648 #endif
 649
 650 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
 651 int board_fix_fdt(void *blob)
 652 {
 653         fixup_msata_port_nodes(blob);
 654         fixup_wwan_port_nodes(blob);
 655
 656         return 0;
 657 }
 658 #endif
 659
 660 int board_init(void)
 661 {
 662         /* address of boot parameters */
 663         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 664
 665         return 0;
 666 }
 667
 668 int board_late_init(void)
 669 {
 670         /*
 671          * If not booting from UART, MCU watchdog was not disabled in SPL,
 672          * disable it now.
 673          */
 674         if (get_boot_device() != BOOT_DEVICE_UART)
 675                 disable_mcu_watchdog();
 676
 677         set_regdomain();
 678         handle_reset_button();
 679         pci_init();
 680
 681         return 0;
 682 }
 683
 684 int show_board_info(void)
 685 {
 686         u32 version_num, serial_num;
 687         int err;
 688
 689         err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
 690         printf("Model: Turris Omnia\n");
 691         printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
 692         if (err)
 693                 printf("  Serial Number: unknown\n");
 694         else
 695                 printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
 696                        be32_to_cpu(serial_num));
 697
 698         return 0;
 699 }
 700
 701 int misc_init_r(void)
 702 {
 703         turris_atsha_otp_init_mac_addresses(1);
 704         return 0;
 705 }
 706
 707 #if defined(CONFIG_OF_BOARD_SETUP)
 708 /*
 709  * I plan to generalize this function and move it to common/fdt_support.c.
 710  * This will require some more work on multiple boards, though, so for now leave
 711  * it here.
 712  */
 713 static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd)
 714 {
 715         struct mtd_info *slave;
 716         int parts;
 717
 718         parts = fdt_subnode_offset(blob, offset, "partitions");
 719         if (parts < 0)
 720                 return false;
 721
 722         if (fdt_del_node(blob, parts) < 0)
 723                 return false;
 724
 725         parts = fdt_add_subnode(blob, offset, "partitions");
 726         if (parts < 0)
 727                 return false;
 728
 729         if (fdt_setprop_u32(blob, parts, "#address-cells", 1) < 0)
 730                 return false;
 731
 732         if (fdt_setprop_u32(blob, parts, "#size-cells", 1) < 0)
 733                 return false;
 734
 735         if (fdt_setprop_string(blob, parts, "compatible",
 736                                "fixed-partitions") < 0)
 737                 return false;
 738
 739         mtd_probe_devices();
 740
 741         list_for_each_entry_reverse(slave, &mtd->partitions, node) {
 742                 char name[32];
 743                 int part;
 744
 745                 snprintf(name, sizeof(name), "partition@%llx", slave->offset);
 746                 part = fdt_add_subnode(blob, parts, name);
 747                 if (part < 0)
 748                         return false;
 749
 750                 if (fdt_setprop_u32(blob, part, "reg", slave->offset) < 0)
 751                         return false;
 752
 753                 if (fdt_appendprop_u32(blob, part, "reg", slave->size) < 0)
 754                         return false;
 755
 756                 if (fdt_setprop_string(blob, part, "label", slave->name) < 0)
 757                         return false;
 758
 759                 if (!(slave->flags & MTD_WRITEABLE))
 760                         if (fdt_setprop_empty(blob, part, "read-only") < 0)
 761                                 return false;
 762
 763                 if (slave->flags & MTD_POWERUP_LOCK)
 764                         if (fdt_setprop_empty(blob, part, "lock") < 0)
 765                                 return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 static void fixup_spi_nor_partitions(void *blob)
 772 {
 773         struct mtd_info *mtd;
 774         int node;
 775
 776         mtd = get_mtd_device_nm(OMNIA_SPI_NOR_PATH);
 777         if (IS_ERR_OR_NULL(mtd))
 778                 goto fail;
 779
 780         node = fdt_path_offset(blob, OMNIA_SPI_NOR_PATH);
 781         if (node < 0)
 782                 goto fail;
 783
 784         if (!fixup_mtd_partitions(blob, node, mtd))
 785                 goto fail;
 786
 787         put_mtd_device(mtd);
 788         return;
 789
 790 fail:
 791         printf("Failed fixing SPI NOR partitions!\n");
 792         if (!IS_ERR_OR_NULL(mtd))
 793                 put_mtd_device(mtd);
 794 }
 795
 796 int ft_board_setup(void *blob, struct bd_info *bd)
 797 {
 798         fixup_spi_nor_partitions(blob);
 799         fixup_msata_port_nodes(blob);
 800         fixup_wwan_port_nodes(blob);
 801
 802         return 0;
 803 }
 804 #endif