board/LEOX/elpt860/elpt860.c

   1 /*
   2 **=====================================================================
   3 **
   4 ** Copyright (C) 2000, 2001, 2002, 2003
   5 ** The LEOX team <team@leox.org>, http://www.leox.org
   6 **
   7 ** LEOX.org is about the development of free hardware and software resources
   8 **   for system on chip.
   9 **
  10 ** Description: U-Boot port on the LEOX's ELPT860 CPU board
  11 ** ~~~~~~~~~~~
  12 **
  13 **=====================================================================
  14 **
  15 ** This program is free software; you can redistribute it and/or
  16 ** modify it under the terms of the GNU General Public License as
  17 ** published by the Free Software Foundation; either version 2 of
  18 ** the License, or (at your option) any later version.
  19 **
  20 ** This program is distributed in the hope that it will be useful,
  21 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 ** GNU General Public License for more details.
  24 **
  25 ** You should have received a copy of the GNU General Public License
  26 ** along with this program; if not, write to the Free Software
  27 ** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 ** MA 02111-1307 USA
  29 **
  30 **=====================================================================
  31 */
  32
  33 /*
  34 ** Note 1: In this file, you have to provide the following functions:
  35 ** ------
  36 **              int             board_early_init_f(void)
  37 **              int             checkboard(void)
  38 **              phys_size_t     initdram(int board_type)
  39 ** called from 'board_init_f()' into 'common/board.c'
  40 **
  41 **              void            reset_phy(void)
  42 ** called from 'board_init_r()' into 'common/board.c'
  43 */
  44
  45 #include <common.h>
  46 #include <mpc8xx.h>
  47
  48 /* ------------------------------------------------------------------------- */
  49
  50 static long int dram_size (long int, long int *, long int);
  51
  52 /* ------------------------------------------------------------------------- */
  53
  54 #define _NOT_USED_      0xFFFFFFFF
  55
  56 const uint init_sdram_table[] = {
  57         /*
  58          * Single Read. (Offset 0 in UPMA RAM)
  59          */
  60         0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
  61         0xFFFFFC04,             /* last */
  62         /*
  63          * SDRAM Initialization (offset 5 in UPMA RAM)
  64          *
  65          * This is no UPM entry point. The following definition uses
  66          * the remaining space to establish an initialization
  67          * sequence, which is executed by a RUN command.
  68          *
  69          */
  70         0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,     /* last */
  71         /*
  72          * Burst Read. (Offset 8 in UPMA RAM)
  73          */
  74         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  75         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  76         0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  77         0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
  78         /*
  79          * Single Write. (Offset 18 in UPMA RAM)
  80          */
  81         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
  82         0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
  83         /*
  84          * Burst Write. (Offset 20 in UPMA RAM)
  85          */
  86         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  87         0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  88         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
  89         0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
  90 };
  91
  92 const uint sdram_table[] = {
  93         /*
  94          * Single Read. (Offset 0 in UPMA RAM)
  95          */
  96         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
  97         0xFF0FFC00,             /* last */
  98         /*
  99          * SDRAM Initialization (offset 5 in UPMA RAM)
 100          *
 101          * This is no UPM entry point. The following definition uses
 102          * the remaining space to establish an initialization
 103          * sequence, which is executed by a RUN command.
 104          *
 105          */
 106         0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,     /* last */
 107         /*
 108          * Burst Read. (Offset 8 in UPMA RAM)
 109          */
 110         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
 111         0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
 112         0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
 113         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 114         /*
 115          * Single Write. (Offset 18 in UPMA RAM)
 116          */
 117         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
 118         0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,     /* last */
 119         _NOT_USED_,
 120         /*
 121          * Burst Write. (Offset 20 in UPMA RAM)
 122          */
 123         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
 124         0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
 125         0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
 126         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 127         /*
 128          * Refresh  (Offset 30 in UPMA RAM)
 129          */
 130         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
 131         0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
 132         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 133         /*
 134          * Exception. (Offset 3c in UPMA RAM)
 135          */
 136         0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
 137 };
 138
 139 /* ------------------------------------------------------------------------- */
 140
 141 #define CONFIG_SYS_PC4    0x0800
 142
 143 #define CONFIG_SYS_DS1    CONFIG_SYS_PC4
 144
 145 /*
 146  * Very early board init code (fpga boot, etc.)
 147  */
 148 int board_early_init_f (void)
 149 {
 150         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 151
 152         /*
 153          * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
 154          */
 155         immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;   /* PCDAT (DS1 = 0)                */
 156         immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;   /* PCPAR (0=general purpose I/O)  */
 157         immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;    /* PCDIR (I/O: 0=input, 1=output) */
 158
 159         return (0);             /* success */
 160 }
 161
 162 /*
 163  * Check Board Identity:
 164  *
 165  * Test ELPT860 ID string
 166  *
 167  * Return 1 if no second DRAM bank, otherwise returns 0
 168  */
 169
 170 int checkboard (void)
 171 {
 172         char buf[64];
 173         int i = getenv_f("serial#", buf, sizeof(buf));
 174
 175         if ((i < 0) || strncmp(buf, "ELPT860", 7))
 176                 printf ("### No HW ID - assuming ELPT860\n");
 177
 178         return (0);             /* success */
 179 }
 180
 181 /* ------------------------------------------------------------------------- */
 182
 183 phys_size_t initdram (int board_type)
 184 {
 185         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 186         volatile memctl8xx_t *memctl = &immap->im_memctl;
 187         long int size8, size9;
 188         long int size_b0 = 0;
 189
 190         /*
 191          * This sequence initializes SDRAM chips on ELPT860 board
 192          */
 193         upmconfig (UPMA, (uint *) init_sdram_table,
 194                    sizeof (init_sdram_table) / sizeof (uint));
 195
 196         memctl->memc_mptpr = 0x0200;
 197         memctl->memc_mamr = 0x18002111;
 198
 199         memctl->memc_mar = 0x00000088;
 200         memctl->memc_mcr = 0x80002000;  /* CS1: SDRAM bank 0 */
 201
 202         upmconfig (UPMA, (uint *) sdram_table,
 203                    sizeof (sdram_table) / sizeof (uint));
 204
 205         /*
 206          * Preliminary prescaler for refresh (depends on number of
 207          * banks): This value is selected for four cycles every 62.4 us
 208          * with two SDRAM banks or four cycles every 31.2 us with one
 209          * bank. It will be adjusted after memory sizing.
 210          */
 211         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 212
 213         /*
 214          * The following value is used as an address (i.e. opcode) for
 215          * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
 216          * the port size is 32bit the SDRAM does NOT "see" the lower two
 217          * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
 218          * MICRON SDRAMs:
 219          * ->    0 00 010 0 010
 220          *       |  |   | |   +- Burst Length = 4
 221          *       |  |   | +----- Burst Type   = Sequential
 222          *       |  |   +------- CAS Latency  = 2
 223          *       |  +----------- Operating Mode = Standard
 224          *       +-------------- Write Burst Mode = Programmed Burst Length
 225          */
 226         memctl->memc_mar = 0x00000088;
 227
 228         /*
 229          * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 230          * preliminary addresses - these have to be modified after the
 231          * SDRAM size has been determined.
 232          */
 233         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 234         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 235
 236         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 237
 238         udelay (200);
 239
 240         /* perform SDRAM initializsation sequence */
 241
 242         memctl->memc_mcr = 0x80002105;  /* CS1: SDRAM bank 0 */
 243         udelay (1);
 244         memctl->memc_mcr = 0x80002230;  /* CS1: SDRAM bank 0 - execute twice */
 245         udelay (1);
 246
 247         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 248
 249         udelay (1000);
 250
 251         /*
 252          * Check Bank 0 Memory Size for re-configuration
 253          *
 254          * try 8 column mode
 255          */
 256         size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 257                            SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 258
 259         udelay (1000);
 260
 261         /*
 262          * try 9 column mode
 263          */
 264         size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 265                            SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 266
 267         if (size8 < size9) {    /* leave configuration at 9 columns       */
 268                 size_b0 = size9;
 269                 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
 270         } else {                /* back to 8 columns                      */
 271
 272                 size_b0 = size8;
 273                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 274                 udelay (500);
 275                 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
 276         }
 277
 278         udelay (1000);
 279
 280         /*
 281          * Adjust refresh rate depending on SDRAM type, both banks
 282          * For types > 128 MBit leave it at the current (fast) rate
 283          */
 284         if (size_b0 < 0x02000000) {
 285                 /* reduce to 15.6 us (62.4 us / quad) */
 286                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 287                 udelay (1000);
 288         }
 289
 290         /*
 291          * Final mapping: map bigger bank first
 292          */
 293         memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 294         memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 295
 296         {
 297                 unsigned long reg;
 298
 299                 /* adjust refresh rate depending on SDRAM type, one bank */
 300                 reg = memctl->memc_mptpr;
 301                 reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 302                 memctl->memc_mptpr = reg;
 303         }
 304
 305         udelay (10000);
 306
 307         return (size_b0);
 308 }
 309
 310 /* ------------------------------------------------------------------------- */
 311
 312 /*
 313  * Check memory range for valid RAM. A simple memory test determines
 314  * the actually available RAM size between addresses `base' and
 315  * `base + maxsize'. Some (not all) hardware errors are detected:
 316  * - short between address lines
 317  * - short between data lines
 318  */
 319
 320 static long int
 321 dram_size (long int mamr_value, long int *base, long int maxsize)
 322 {
 323         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 324         volatile memctl8xx_t *memctl = &immap->im_memctl;
 325
 326         memctl->memc_mamr = mamr_value;
 327
 328         return (get_ram_size (base, maxsize));
 329 }
 330
 331 /* ------------------------------------------------------------------------- */
 332
 333 #define CONFIG_SYS_PA1     0x4000
 334 #define CONFIG_SYS_PA2     0x2000
 335
 336 #define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
 337
 338 void reset_phy (void)
 339 {
 340         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 341
 342         /*
 343          * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
 344          *                                          and no AUI loopback
 345          */
 346         immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
 347         immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;  /* PAPAR (0=general purpose I/O)  */
 348         immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;   /* PADIR (I/O: 0=input, 1=output) */
 349 }