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Get rid of bogus CONFIG_SYS_BUS_HZ and CONFIG_SYS_CONFIG_BUS_CLK definitions
[people/ms/u-boot.git] / board / MAI / AmigaOneG3SE / articiaS.c
1 /*
2 * (C) Copyright 2002
3 * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <pci.h>
26 #include <asm/processor.h>
27 #include "memio.h"
28 #include "articiaS.h"
29 #include "smbus.h"
30 #include "via686.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #undef DEBUG
35
36 struct dimm_bank {
37 uint8 used; /* Bank is populated */
38 uint32 rows; /* Number of row addresses */
39 uint32 columns; /* Number of column addresses */
40 uint8 registered; /* SIMM is registered */
41 uint8 ecc; /* SIMM has ecc */
42 uint8 burst_len; /* Supported burst lengths */
43 uint32 cas_lat; /* Supported CAS latencies */
44 uint32 cas_used; /* CAS to use (not set by user) */
45 uint32 trcd; /* RAS to CAS latency */
46 uint32 trp; /* Precharge latency */
47 uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */
48 uint32 tclk_2hi; /* SDRAM second highest CAS latency */
49 uint32 size; /* Size of bank in bytes */
50 uint8 auto_refresh; /* Module supports auto refresh */
51 uint32 refresh_time; /* Refresh time (in ns) */
52 };
53
54
55 /*
56 ** Based in part on the evb64260 code
57 */
58
59 /*
60 * translate ns.ns/10 coding of SPD timing values
61 * into 10 ps unit values
62 */
63 static inline unsigned short NS10to10PS (unsigned char spd_byte)
64 {
65 unsigned short ns, ns10;
66
67 /* isolate upper nibble */
68 ns = (spd_byte >> 4) & 0x0F;
69 /* isolate lower nibble */
70 ns10 = (spd_byte & 0x0F);
71
72 return (ns * 100 + ns10 * 10);
73 }
74
75 /*
76 * translate ns coding of SPD timing values
77 * into 10 ps unit values
78 */
79 static inline unsigned short NSto10PS (unsigned char spd_byte)
80 {
81 return (spd_byte * 100);
82 }
83
84
85 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
86 {
87 int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
88 uint32 busclock = gd->bus_clk;
89 uint32 memclock = busclock;
90 uint32 tmemclock = 1000000000 / (memclock / 100);
91 uint32 datawidth;
92
93 if (sm_get_data (rom, dimm_address) == 0) {
94 /* Nothing in slot, make both banks empty */
95 debug ("Slot %d: vacant\n", dimmNum);
96 banks[0].used = 0;
97 banks[1].used = 0;
98 return 0;
99 }
100
101 if (rom[2] != 0x04) {
102 debug ("Slot %d: No SDRAM\n", dimmNum);
103 banks[0].used = 0;
104 banks[1].used = 0;
105 return 0;
106 }
107
108 /* Determine number of banks/rows */
109 if (rom[5] == 1) {
110 banks[0].used = 1;
111 banks[1].used = 0;
112 } else {
113 banks[0].used = 1;
114 banks[1].used = 1;
115 }
116
117 /* Determine number of row addresses */
118 if (rom[3] & 0xf0) {
119 /* Different banks sizes */
120 banks[0].rows = rom[3] & 0x0f;
121 banks[1].rows = (rom[3] & 0xf0) >> 4;
122 } else {
123 /* Equal sized banks */
124 banks[0].rows = rom[3] & 0x0f;
125 banks[1].rows = banks[0].rows;
126 }
127
128 /* Determine number of column addresses */
129 if (rom[4] & 0xf0) {
130 /* Different bank sizes */
131 banks[0].columns = rom[4] & 0x0f;
132 banks[1].columns = (rom[4] & 0xf0) >> 4;
133 } else {
134 banks[0].columns = rom[4] & 0x0f;
135 banks[1].columns = banks[0].columns;
136 }
137
138 /* Check Jedec revision, and modify row/column accordingly */
139 if (rom[62] > 0x10) {
140 if (banks[0].rows <= 3)
141 banks[0].rows += 15;
142 if (banks[1].rows <= 3)
143 banks[1].rows += 15;
144 if (banks[0].columns <= 3)
145 banks[0].columns += 15;
146 if (banks[0].columns <= 3)
147 banks[0].columns += 15;
148 }
149
150 /* Check registered/unregisterd */
151 if (rom[21] & 0x12) {
152 banks[0].registered = 1;
153 banks[1].registered = 1;
154 } else {
155 banks[0].registered = 0;
156 banks[1].registered = 0;
157 }
158
159 #ifdef CONFIG_ECC
160 /* Check parity/ECC */
161 banks[0].ecc = (rom[11] == 0x02);
162 banks[1].ecc = (rom[11] == 0x02);
163 #endif
164
165 /* Find burst lengths supported */
166 banks[0].burst_len = rom[16] & 0x8f;
167 banks[1].burst_len = rom[16] & 0x8f;
168
169 /* Find possible cas latencies */
170 banks[0].cas_lat = rom[18] & 0x7F;
171 banks[1].cas_lat = rom[18] & 0x7F;
172
173 /* RAS/CAS latency */
174 banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
175 banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
176
177 /* Precharge latency */
178 banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
179 banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
180
181 /* highest CAS latency */
182 banks[0].tclk_hi = NS10to10PS (rom[9]);
183 banks[1].tclk_hi = NS10to10PS (rom[9]);
184
185 /* second highest CAS latency */
186 banks[0].tclk_2hi = NS10to10PS (rom[23]);
187 banks[1].tclk_2hi = NS10to10PS (rom[23]);
188
189 /* bank sizes */
190 datawidth = rom[13] & 0x7f;
191 banks[0].size =
192 (1L << (banks[0].rows + banks[0].columns)) *
193 /* FIXME datawidth */ 8 * rom[17];
194 if (rom[13] & 0x80)
195 banks[1].size = 2 * banks[0].size;
196 else
197 banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
198 /* FIXME datawidth */ 8 * rom[17];
199
200 /* Refresh */
201 if (rom[12] & 0x80) {
202 banks[0].auto_refresh = 1;
203 banks[1].auto_refresh = 1;
204 } else {
205 banks[0].auto_refresh = 0;
206 banks[1].auto_refresh = 0;
207 }
208
209 switch (rom[12] & 0x7f) {
210 case 0:
211 banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
212 banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
213 break;
214 case 1:
215 banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
216 banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
217 break;
218 case 2:
219 banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
220 banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
221 break;
222 case 3:
223 banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
224 banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
225 break;
226 case 4:
227 banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
228 banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
229 break;
230 case 5:
231 banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
232 banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
233 break;
234 default:
235 banks[0].refresh_time = 0x100; /* Default of Articia S */
236 banks[1].refresh_time = 0x100;
237 break;
238 }
239
240 #ifdef DEBUG
241 printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
242 printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
243 printf ("Number of row addresses: %ld\n", banks[0].rows);
244 printf ("Number of coumns addresses: %ld\n", banks[0].columns);
245 printf ("SIMM is %sregistered\n",
246 banks[0].registered == 0 ? "not " : "");
247 #ifdef CONFIG_ECC
248 printf ("SIMM %s ECC\n",
249 banks[0].ecc == 1 ? "supports" : "doesn't support");
250 #endif
251 printf ("Supported burst lenghts: %s %s %s %s %s\n",
252 banks[0].burst_len & 0x08 ? "8" : " ",
253 banks[0].burst_len & 0x04 ? "4" : " ",
254 banks[0].burst_len & 0x02 ? "2" : " ",
255 banks[0].burst_len & 0x01 ? "1" : " ",
256 banks[0].burst_len & 0x80 ? "PAGE" : " ");
257 printf ("Supported CAS latencies: %s %s %s\n",
258 banks[0].cas_lat & 0x04 ? "CAS 3" : " ",
259 banks[0].cas_lat & 0x02 ? "CAS 2" : " ",
260 banks[0].cas_lat & 0x01 ? "CAS 1" : " ");
261 printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
262 printf ("Precharge latency: %ld\n", banks[0].trp);
263 printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
264 printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
265 printf ("SDRAM data width: %ld\n", datawidth);
266 printf ("Auto Refresh %ssupported\n",
267 banks[0].auto_refresh ? "" : "not ");
268 printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
269 if (banks[0].used)
270 printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
271 if (banks[1].used)
272 printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
273
274 printf ("\n");
275 #endif
276
277 sm_term ();
278 return 1;
279 }
280
281 void select_cas (struct dimm_bank *banks, uint8 fast)
282 {
283 if (!banks[0].used) {
284 banks[0].cas_used = 0;
285 banks[0].cas_used = 0;
286 return;
287 }
288
289 if (fast) {
290 /* Search for fast CAS */
291 uint32 i;
292 uint32 c = 0x01;
293
294 for (i = 1; i < 5; i++) {
295 if (banks[0].cas_lat & c) {
296 banks[0].cas_used = i;
297 banks[1].cas_used = i;
298 debug ("Using CAS %d (fast)\n", i);
299 return;
300 }
301 c <<= 1;
302 }
303
304 /* Default to CAS 3 */
305 banks[0].cas_used = 3;
306 banks[1].cas_used = 3;
307 debug ("Using CAS 3 (fast)\n");
308
309 return;
310 } else {
311 /* Search for slow cas */
312 uint32 i;
313 uint32 c = 0x08;
314
315 for (i = 4; i > 1; i--) {
316 if (banks[0].cas_lat & c) {
317 banks[0].cas_used = i;
318 banks[1].cas_used = i;
319 debug ("Using CAS %d (slow)\n", i);
320 return;
321 }
322 c >>= 1;
323 }
324
325 /* Default to CAS 3 */
326 banks[0].cas_used = 3;
327 banks[1].cas_used = 3;
328 debug ("Using CAS 3 (slow)\n");
329
330 return;
331 }
332
333 banks[0].cas_used = 3;
334 banks[1].cas_used = 3;
335 debug ("Using CAS 3\n");
336
337 return;
338 }
339
340 uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
341 {
342 uint32 i;
343
344 struct RowColumnSize {
345 uint32 banks;
346 uint32 rows;
347 uint32 columns;
348 uint32 size;
349 uint32 register_value;
350 };
351
352 struct RowColumnSize rcs_map[] = {
353 /* Sbk Radr Cadr MB Value */
354 {1, 11, 8, 8, 0x00840f00},
355 {1, 11, 9, 16, 0x00925f00},
356 {1, 11, 10, 32, 0x00a64f00},
357 {2, 12, 8, 32, 0x00c55f00},
358 {2, 12, 9, 64, 0x00d66f00},
359 {2, 12, 10, 128, 0x00e77f00},
360 {2, 12, 11, 256, 0x00ff8f00},
361 {2, 13, 11, 512, 0x00ff9f00},
362 {0, 0, 0, 0, 0x00000000}
363 };
364
365
366 i = 0;
367
368 while (rcs_map[i].banks != 0) {
369 if (rows == rcs_map[i].rows
370 && columns == rcs_map[i].columns
371 && (size / 1024 / 1024) == rcs_map[i].size)
372 return rcs_map[i].register_value;
373
374 i++;
375 }
376
377 return 0;
378 }
379
380 uint32 burst_to_len (uint32 support)
381 {
382 if (support & 0x80)
383 return 0x7;
384 else if (support & 0x8)
385 return 0x3;
386 else if (support & 0x4)
387 return 0x2;
388 else if (support & 0x2)
389 return 0x1;
390 else if (support & 0x1)
391 return 0x0;
392
393 return 0;
394 }
395
396 long articiaS_ram_init (void)
397 {
398 register uint32 i;
399 register uint32 value1;
400 register uint32 value2;
401 uint8 rom[128];
402 uint32 burst_len;
403 uint32 burst_support;
404 uint32 total_ram = 0;
405
406 struct dimm_bank banks[4]; /* FIXME: Move to initram */
407 uint32 busclock = gd->bus_clk;
408 uint32 memclock = busclock;
409 uint32 reg32;
410 uint32 refresh_clocks;
411 uint8 auto_refresh;
412
413 memset (banks, 0, sizeof (struct dimm_bank) * 4);
414
415 detect_sdram (rom, 0, &banks[0]);
416 detect_sdram (rom, 1, &banks[2]);
417
418 for (i = 0; i < 4; i++) {
419 total_ram = total_ram + (banks[i].used * banks[i].size);
420 }
421
422 pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
423 pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
424 pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */
425 pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
426 pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */
427 pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */
428
429 /* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
430 if (banks[0].used) {
431 value1 = get_reg_setting (banks[0].used + banks[1].used,
432 banks[0].rows, banks[0].columns,
433 banks[0].size);
434 } else {
435 value1 = 0;
436 }
437
438 if (banks[1].used) {
439 value2 = get_reg_setting (banks[0].used + banks[1].used,
440 banks[1].rows, banks[1].columns,
441 banks[1].size);
442 } else {
443 value2 = 0;
444 }
445
446 pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
447 pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
448
449 debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
450 debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
451
452 if (banks[2].used) {
453 value1 = get_reg_setting (banks[2].used + banks[3].used,
454 banks[2].rows, banks[2].columns,
455 banks[2].size);
456 } else {
457 value1 = 0;
458 }
459
460 if (banks[3].used) {
461 value2 = get_reg_setting (banks[2].used + banks[3].used,
462 banks[3].rows, banks[3].columns,
463 banks[3].size);
464 } else {
465 value2 = 0;
466 }
467
468 pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
469 pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
470
471 debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
472 debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
473
474 pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
475 pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
476 pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
477 pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
478
479 /* Determine timing */
480 select_cas (&banks[0], 0);
481 select_cas (&banks[2], 0);
482
483 /* FIXME: What about write recovery */
484 /* Auto refresh Precharge */
485 #if 0
486 reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
487 /* Write recovery CAS Latency */
488 (0x1 << 6) | (banks[0].cas_used << 4) |
489 /* RAS/CAS latency */
490 ((banks[0].trcd - 1) << 0);
491
492 reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
493 (0x1 << 6) | (banks[2].cas_used << 4) |
494 ((banks[2].trcd - 1) << 0)) << 16;
495 #else
496 if (100000000 == gd->bus_clk)
497 reg32 = 0x71737173;
498 else
499 reg32 = 0x69736973;
500 #endif
501 pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
502 debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
503
504 /* Write default in DIMM2/3 (not used on A1) */
505 pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
506
507
508 /* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
509 reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
510 reg32 &= 0xFF00FFFF;
511
512 #if 0
513 if (banks[0].used && banks[0].registered)
514 reg32 |= 0x1 << 16;
515
516 if (banks[2].used && banks[2].registered)
517 reg32 |= 0x1 << 18;
518 #else
519 if (banks[0].registered || banks[2].registered)
520 reg32 |= 0x55 << 16;
521 #endif
522 pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
523 debug ("DRAM_GCR0 = 0x%08x\n", reg32);
524
525 /* Determine refresh */
526 refresh_clocks = 0xffffffff;
527 auto_refresh = 1;
528
529 for (i = 0; i < 4; i++) {
530 if (banks[i].used) {
531 if (banks[i].auto_refresh == 0)
532 auto_refresh = 0;
533 if (banks[i].refresh_time < refresh_clocks)
534 refresh_clocks = banks[i].refresh_time;
535 }
536 }
537
538
539 #if 1
540 /* It seems this is suggested by the ArticiaS data book */
541 if (100000000 == gd->bus_clk)
542 refresh_clocks = 1561;
543 else
544 refresh_clocks = 2083;
545 #endif
546
547
548 debug ("Refresh set to %ld clocks, auto refresh %s\n",
549 refresh_clocks, auto_refresh ? "on" : "off");
550
551 pci_write_cfg_long (0, 0, DRAM_REFRESH0,
552 (1 << 16) | (1 << 15) | (auto_refresh << 12) |
553 (refresh_clocks));
554 debug ("DRAM_REFRESH0 = 0x%08x\n",
555 (1 << 16) | (1 << 15) | (auto_refresh << 12) |
556 (refresh_clocks));
557
558 /* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */
559
560 /* Set mode registers */
561 /* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
562 /* Find a common burst len */
563 burst_support = 0xff;
564
565 if (banks[0].used)
566 burst_support = banks[0].burst_len;
567 if (banks[1].used)
568 burst_support = banks[1].burst_len;
569 if (banks[2].used)
570 burst_support = banks[2].burst_len;
571 if (banks[3].used)
572 burst_support = banks[3].burst_len;
573
574 /*
575 ** Mode register:
576 ** Bits Use
577 ** 0-2 Burst len
578 ** 3 Burst type (0 = sequential, 1 = interleave)
579 ** 4-6 CAS latency
580 ** 7-8 Operation mode (0 = default, all others invalid)
581 ** 9 Write burst
582 ** 10-11 Reserved
583 **
584 ** Mode register burst table:
585 ** A2 A1 A0 lenght
586 ** 0 0 0 1
587 ** 0 0 1 2
588 ** 0 1 0 4
589 ** 0 1 1 8
590 ** 1 0 0 invalid
591 ** 1 0 1 invalid
592 ** 1 1 0 invalid
593 ** 1 1 1 page (only valid for non-interleaved)
594 */
595
596 burst_len = burst_to_len (burst_support);
597 burst_len = 2; /* FIXME */
598
599 if (banks[0].used) {
600 pci_write_cfg_word (0, 0, DRAM_PCR0,
601 0x8000 | burst_len | (banks[0].cas_used << 4));
602 debug ("Mode bank 0: 0x%08x\n",
603 0x8000 | burst_len | (banks[0].cas_used << 4));
604 } else {
605 /* Seems to be needed to disable the bank */
606 pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
607 }
608
609 if (banks[1].used) {
610 pci_write_cfg_word (0, 0, DRAM_PCR0,
611 0x9000 | burst_len | (banks[1].cas_used << 4));
612 debug ("Mode bank 1: 0x%08x\n",
613 0x8000 | burst_len | (banks[1].cas_used << 4));
614 } else {
615 /* Seems to be needed to disable the bank */
616 pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
617 }
618
619
620 if (banks[2].used) {
621 pci_write_cfg_word (0, 0, DRAM_PCR0,
622 0xa000 | burst_len | (banks[2].cas_used << 4));
623 debug ("Mode bank 2: 0x%08x\n",
624 0x8000 | burst_len | (banks[2].cas_used << 4));
625 } else {
626 /* Seems to be needed to disable the bank */
627 pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
628 }
629
630
631 if (banks[3].used) {
632 pci_write_cfg_word (0, 0, DRAM_PCR0,
633 0xb000 | burst_len | (banks[3].cas_used << 4));
634 debug ("Mode bank 3: 0x%08x\n",
635 0x8000 | burst_len | (banks[3].cas_used << 4));
636 } else {
637 /* Seems to be needed to disable the bank */
638 pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
639 }
640
641
642 pci_write_cfg_word (0, 0, 0xba, 0x00);
643
644 return total_ram;
645 }
646
647 extern int drv_isa_kbd_init (void);
648
649 int last_stage_init (void)
650 {
651 drv_isa_kbd_init ();
652 return 0;
653 }
654
655 int overwrite_console (void)
656 {
657 return (0);
658 }
659
660 #define in_8 read_byte
661 #define out_8 write_byte
662
663 static __inline__ unsigned long get_msr (void)
664 {
665 unsigned long msr;
666
667 asm volatile ("mfmsr %0":"=r" (msr):);
668
669 return msr;
670 }
671
672 static __inline__ void set_msr (unsigned long msr)
673 {
674 asm volatile ("mtmsr %0"::"r" (msr));
675 }
676
677 int board_early_init_f (void)
678 {
679 unsigned char c_value = 0;
680 unsigned long msr;
681
682 /* Basic init of PS/2 keyboard (needed for some reason)... */
683 /* Ripped from John's code */
684 while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
685 out_8 ((unsigned char *) 0xfe000064, 0xaa);
686 while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
687 c_value = in_8 ((unsigned char *) 0xfe000060);
688 while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
689 out_8 ((unsigned char *) 0xfe000064, 0xab);
690 while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
691 c_value = in_8 ((unsigned char *) 0xfe000060);
692 while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
693 out_8 ((unsigned char *) 0xfe000064, 0xae);
694 /* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
695 /* c_value = in_8((unsigned char *)0xfe000060); */
696
697 /* Enable FPU */
698 msr = get_msr ();
699 set_msr (msr | MSR_FP);
700
701 via_calibrate_bus_freq ();
702
703 return 0;
704 }
"Das U-Boot" Source Tree