board/MAI/AmigaOneG3SE/board_asm_init.S

   1         #include        "macros.h"
   2
   3
   4
   5 #define GLOBALINFO0           0x50
   6 #define GLOBALINFO0_BO        (1<<7)
   7 #define GLOBALINFO2_B1ARBITER (1<<6)
   8 #define HBUSACR0              0x5c
   9 #define HBUSACR2_BURST        (1<<0)
  10 #define HBUSACR2_LAT          (1<<1)
  11
  12 #define RECEIVER_HOLDING 0
  13 #define TRANSMITTER_HOLDING 0
  14 #define INTERRUPT_ENABLE 1
  15 #define INTERRUPT_STATUS 2
  16 #define FIFO_CONTROL 2
  17 #define LINE_CONTROL 3
  18 #define MODEM_CONTROL 4
  19 #define LINE_STATUS 5
  20 #define MODEM_STATUS 6
  21 #define SCRATCH_PAD 7
  22
  23 #define DIVISOR_LATCH_LSB 0
  24 #define DIVISOR_LATCH_MSB 1
  25 #define PRESCALER_DIVISION 5
  26
  27 #define UART(x) (0x3f8+(x))
  28
  29 #define GLOBALINFO0           0x50
  30 #define GLOBALINFO0_BO        (1<<7)
  31 #define GLOBALINFO2_B1ARBITER (1<<6)
  32 #define HBUSACR0              0x5c
  33 #define HBUSACR2_BURST        (1<<0)
  34 #define HBUSACR2_LAT          (1<<1)
  35
  36 #define SUPERIO_1               ((7 << 3) | (0))
  37 #define SUPERIO_2               ((7 << 3) | (1))
  38
  39         .globl  board_asm_init
  40
  41 board_asm_init:
  42         mflr    r29
  43         /* Set 'Must-set' register */
  44         li      r3, 0
  45         li      r4, 0
  46         li      r5, 0x5e
  47         bl      pci_read_cfg_byte
  48         ori     r3, r3, (1<<1)
  49         xori    r6, r3, (1<<1)
  50         li      r3, 0
  51         bl      pci_write_cfg_byte
  52
  53         li      r3, 0
  54         li      r5, 0x52
  55         bl      pci_read_cfg_byte
  56         ori     r6, r3, (1<<6)
  57         li      r3, 0
  58         bl      pci_write_cfg_byte
  59
  60         li      r3, 0
  61         li      r4, 0x08
  62         li      r5, 0xd2
  63         bl      pci_read_cfg_byte
  64         ori     r6, r3, (1<<2)
  65         li      r3, 0
  66         bl      pci_write_cfg_byte
  67
  68
  69         /* Do PCI reset */
  70 /*      li      r3, 0
  71         li      r4, 0x38
  72         li      r5, 0x47
  73         bl      pci_read_cfg_byte
  74         ori     r6, r3, 0x01
  75         li      r3, 0
  76         li      r4, 0x38
  77         li      r5, 0x47
  78         bl      pci_write_cfg_byte*/
  79
  80
  81         /* Enable NVRAM for environment */
  82         li      r3, 0
  83         li      r4, 0
  84         li      r5, 0x56
  85         li      r6, 0x0B
  86         bl      pci_write_cfg_byte
  87
  88
  89         /* Init Super-I/O chips */
  90
  91         siowb   0x40, 0x08
  92         siowb   0x41, 0x01
  93         siowb   0x45, 0x80
  94         siowb   0x46, 0x60
  95         siowb   0x47, 0x20
  96         siowb   0x48, 0x01
  97         siowb   0x4a, 0xc4
  98         siowb   0x50, 0x0e
  99         siowb   0x51, 0x76
 100         siowb   0x52, 0x34
 101         siowb   0x54, 0x00
 102         siowb   0x55, 0x90
 103         siowb   0x56, 0x99
 104         siowb   0x57, 0x90
 105         siowb   0x85, 0x01
 106
 107         /* Enable configuration mode for SuperIO */
 108         li      r3, 0
 109         li      r4, (7<<3)
 110         li      r5, 0x85
 111         bl      pci_read_cfg_byte
 112         ori     r6, r3, 0x02
 113         mr      r31, r6
 114         li      r3,0
 115         bl      pci_write_cfg_byte
 116
 117         /* COM1 as 3f8 */
 118         outb    0x3f0, 0xe7
 119         outb    0x3f1, 0xfe
 120
 121         /* COM2 as 2f8 */
 122         outb    0x3f0, 0xe8
 123         outb    0x3f1, 0xeb
 124
 125         /* Enable */
 126         outb    0x3f0, 0xe2
 127         inb     r3, 0x3f1
 128         ori     r3, r3, 0x0c
 129         outb    0x3f0, 0xe2
 130         outbr   0x3f1, r3
 131
 132         /* Disable configuration mode */
 133         li      r3, 0
 134         li      r4, (7<<3)
 135         li      r5, 0x85
 136         mr      r6, r31
 137         bl      pci_write_cfg_byte
 138
 139         /* Set line control */
 140         outb    UART(LINE_CONTROL), 0x83
 141         outb    UART(DIVISOR_LATCH_LSB), 0x0c
 142         outb    UART(DIVISOR_LATCH_MSB), 0x00
 143         outb    UART(LINE_CONTROL), 0x3
 144
 145         mtlr    r29
 146         blr
 147
 148
 149         .globl  new_reset
 150         .globl  new_reset_end
 151 new_reset:
 152         li      r0, 0x100
 153         oris    r0, r0, 0xFFF0
 154         mtlr    r0
 155         blr
 156
 157 new_reset_end: