board/Marvell/common/intel_flash.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Hacked for the marvell db64360 eval board by
   8  * Ingo Assmus <ingo.assmus@keymile.com>
   9  */
  10
  11 /*************** DEFINES for Intel StrataFlash FLASH chip ********************/
  12
  13 /*
  14  * acceptable chips types are:
  15  *
  16  *      28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
  17  */
  18
  19 /* register addresses, valid only following an CHIP_CMD_RD_ID command */
  20 #define CHIP_ADDR_REG_MAN       0x000000        /* manufacturer's id */
  21 #define CHIP_ADDR_REG_DEV       0x000001        /* device id */
  22 #define CHIP_ADDR_REG_CFGM      0x000003        /* master lock config */
  23 #define CHIP_ADDR_REG_CFG(b)    (((b)<<16)|2)   /* lock config for block b */
  24
  25 /* Commands */
  26 #define CHIP_CMD_RST            0xFF            /* reset flash */
  27 #define CHIP_CMD_RD_ID          0x90            /* read the id and lock bits */
  28 #define CHIP_CMD_RD_QUERY       0x98            /* read device capabilities */
  29 #define CHIP_CMD_RD_STAT        0x70            /* read the status register */
  30 #define CHIP_CMD_CLR_STAT       0x50            /* clear the staus register */
  31 #define CHIP_CMD_WR_BUF         0xE8            /* clear the staus register */
  32 #define CHIP_CMD_PROG           0x40            /* program word command */
  33 #define CHIP_CMD_ERASE1         0x20            /* 1st word for block erase */
  34 #define CHIP_CMD_ERASE2         0xD0            /* 2nd word for block erase */
  35 #define CHIP_CMD_ERASE_SUSP     0xB0            /* suspend block erase */
  36 #define CHIP_CMD_LOCK           0x60            /* 1st word for all lock cmds */
  37 #define CHIP_CMD_SET_LOCK_BLK   0x01            /* 2nd wrd set block lock bit */
  38 #define CHIP_CMD_SET_LOCK_MSTR  0xF1            /* 2nd wrd set master lck bit */
  39 #define CHIP_CMD_CLR_LOCK_BLK   0xD0            /* 2nd wrd clear blk lck bit */
  40
  41 /* status register bits */
  42 #define CHIP_STAT_DPS           0x02            /* Device Protect Status */
  43 #define CHIP_STAT_VPPS          0x08            /* VPP Status */
  44 #define CHIP_STAT_PSLBS         0x10            /* Program+Set Lock Bit Stat */
  45 #define CHIP_STAT_ECLBS         0x20            /* Erase+Clr Lock Bit Stat */
  46 #define CHIP_STAT_ESS           0x40            /* Erase Suspend Status */
  47 #define CHIP_STAT_RDY           0x80            /* WSM Mach Status, 1=rdy */
  48
  49 #define CHIP_STAT_ERR           (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
  50                                     CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
  51
  52 /* ID and Lock Configuration */
  53 #define CHIP_RD_ID_LOCK         0x01            /* Bit 0 of each byte */
  54 #define CHIP_RD_ID_MAN          0x89            /* Manufacturer code = 0x89 */
  55 #define CHIP_RD_ID_DEV          CONFIG_SYS_FLASH_ID
  56
  57 /* dimensions */
  58 #define CHIP_WIDTH              2               /* chips are in 16 bit mode */
  59 #define CHIP_WSHIFT             1               /* (log2 of CHIP_WIDTH) */
  60 #define CHIP_NBLOCKS            128
  61 #define CHIP_BLKSZ              (128 * 1024)    /* of 128Kbytes each */
  62 #define CHIP_SIZE               (CHIP_BLKSZ * CHIP_NBLOCKS)
  63
  64 /********************** DEFINES for Hymod Flash ******************************/
  65
  66 /*
  67  * The hymod board has 2 x 28F320J5 chips running in
  68  * 16 bit mode, for a 32 bit wide bank.
  69  */
  70
  71 typedef unsigned short bank_word_t;             /* 8/16/32/64bit unsigned int */
  72 typedef volatile bank_word_t *bank_addr_t;
  73 typedef unsigned long bank_size_t;              /* want this big - >= 32 bit */
  74
  75 #define BANK_CHIP_WIDTH         1               /* each bank is 1 chip wide */
  76 #define BANK_CHIP_WSHIFT        0               /* (log2 of BANK_CHIP_WIDTH) */
  77
  78 #define BANK_WIDTH              (CHIP_WIDTH * BANK_CHIP_WIDTH)
  79 #define BANK_WSHIFT             (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
  80 #define BANK_NBLOCKS            CHIP_NBLOCKS
  81 #define BANK_BLKSZ              (CHIP_BLKSZ * BANK_CHIP_WIDTH)
  82 #define BANK_SIZE               (CHIP_SIZE * BANK_CHIP_WIDTH)
  83
  84 #define MAX_BANKS               1               /* only one bank possible */
  85
  86 /* align bank addresses and sizes to bank word boundaries */
  87 #define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  88                                     & ~(BANK_WIDTH - 1)))
  89 #define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
  90                                     (bank_size_t)(s) + (BANK_WIDTH - 1)))
  91
  92 /* align bank addresses and sizes to bank block boundaries */
  93 #define BANK_ADDR_BLK_ALIGN(a)  ((bank_addr_t)((bank_size_t)(a) \
  94                                     & ~(BANK_BLKSZ - 1)))
  95 #define BANK_SIZE_BLK_ALIGN(s)  ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
  96                                     (bank_size_t)(s) + (BANK_BLKSZ - 1)))
  97
  98 /* align bank addresses and sizes to bank boundaries */
  99 #define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
 100                                     & ~(BANK_SIZE - 1)))
 101 #define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
 102                                     (bank_size_t)(s) + (BANK_SIZE - 1)))
 103
 104 /* add an offset to a bank address */
 105 #define BANK_ADDR_OFFSET(a, o)  (bank_addr_t)((bank_size_t)(a) + \
 106                                     (bank_size_t)(o))
 107
 108 /* get base address of bank b, given flash base address a */
 109 #define BANK_ADDR_BASE(a, b)    BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 110                                     (bank_size_t)(b) * BANK_SIZE)
 111
 112 /* adjust a bank address to start of next word, block or bank */
 113 #define BANK_ADDR_NEXT_WORD(a)  BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
 114                                     BANK_WIDTH)
 115 #define BANK_ADDR_NEXT_BLK(a)   BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
 116                                     BANK_BLKSZ)
 117 #define BANK_ADDR_NEXT_BANK(a)  BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 118                                     BANK_SIZE)
 119
 120 /* get bank address of chip register r given a bank base address a */
 121 #define BANK_ADDR_REG(a, r)     BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 122                                     ((bank_size_t)(r) << BANK_WSHIFT))
 123
 124 /* make a bank address for each chip register address */
 125
 126 #define BANK_ADDR_REG_MAN(a)    BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
 127 #define BANK_ADDR_REG_DEV(a)    BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
 128 #define BANK_ADDR_REG_CFGM(a)   BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
 129 #define BANK_ADDR_REG_CFG(b,a)  BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
 130
 131 /*
 132  * replicate a chip cmd/stat/rd value into each byte position within a word
 133  * so that multiple chips are accessed in a single word i/o operation
 134  *
 135  * this must be as wide as the bank_word_t type, and take into account the
 136  * chip width and bank layout
 137  */
 138
 139 #define BANK_FILL_WORD(o)       ((bank_word_t)(o))
 140
 141 /* make a bank word value for each chip cmd/stat/rd value */
 142
 143 /* Commands */
 144 #define BANK_CMD_RST            BANK_FILL_WORD(CHIP_CMD_RST)
 145 #define BANK_CMD_RD_ID          BANK_FILL_WORD(CHIP_CMD_RD_ID)
 146 #define BANK_CMD_RD_STAT        BANK_FILL_WORD(CHIP_CMD_RD_STAT)
 147 #define BANK_CMD_CLR_STAT       BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
 148 #define BANK_CMD_ERASE1         BANK_FILL_WORD(CHIP_CMD_ERASE1)
 149 #define BANK_CMD_ERASE2         BANK_FILL_WORD(CHIP_CMD_ERASE2)
 150 #define BANK_CMD_PROG           BANK_FILL_WORD(CHIP_CMD_PROG)
 151 #define BANK_CMD_LOCK           BANK_FILL_WORD(CHIP_CMD_LOCK)
 152 #define BANK_CMD_SET_LOCK_BLK   BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
 153 #define BANK_CMD_SET_LOCK_MSTR  BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
 154 #define BANK_CMD_CLR_LOCK_BLK   BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
 155
 156 /* status register bits */
 157 #define BANK_STAT_DPS           BANK_FILL_WORD(CHIP_STAT_DPS)
 158 #define BANK_STAT_PSS           BANK_FILL_WORD(CHIP_STAT_PSS)
 159 #define BANK_STAT_VPPS          BANK_FILL_WORD(CHIP_STAT_VPPS)
 160 #define BANK_STAT_PSLBS         BANK_FILL_WORD(CHIP_STAT_PSLBS)
 161 #define BANK_STAT_ECLBS         BANK_FILL_WORD(CHIP_STAT_ECLBS)
 162 #define BANK_STAT_ESS           BANK_FILL_WORD(CHIP_STAT_ESS)
 163 #define BANK_STAT_RDY           BANK_FILL_WORD(CHIP_STAT_RDY)
 164
 165 #define BANK_STAT_ERR           BANK_FILL_WORD(CHIP_STAT_ERR)
 166
 167 /* ID and Lock Configuration */
 168 #define BANK_RD_ID_LOCK         BANK_FILL_WORD(CHIP_RD_ID_LOCK)
 169 #define BANK_RD_ID_MAN          BANK_FILL_WORD(CHIP_RD_ID_MAN)
 170 #define BANK_RD_ID_DEV          BANK_FILL_WORD(CHIP_RD_ID_DEV)