board/Marvell/db-88f6720/db-88f6720.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <miiphy.h>
   8 #include <net.h>
   9 #include <netdev.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 /*
  17  * Those values and defines are taken from the Marvell U-Boot version
  18  * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
  19  */
  20 #define DB_88F6720_MPP0_7               0x00020020 /* SPI */
  21 #define DB_88F6720_MPP8_15              0x22000022 /* SPI , I2C */
  22 #define DB_88F6720_MPP16_23             0x22222222 /* UART, TDM*/
  23 #define DB_88F6720_MPP24_31             0x33333333 /* SDIO, SPI1*/
  24 #define DB_88F6720_MPP32_39             0x04403330 /* SPI1, External SMI */
  25 #define DB_88F6720_MPP40_47             0x22002044 /* UART1, GE0, SATA0 LED */
  26 #define DB_88F6720_MPP48_55             0x22222222 /* GE0 */
  27 #define DB_88F6720_MPP56_63             0x04444422 /* GE0 , LED_MATRIX, GPIO */
  28 #define DB_88F6720_MPP64_67             0x014   /* LED_MATRIX, SATA1 LED*/
  29
  30 #define DB_88F6720_GPP_OUT_ENA_LOW      0xFFFFFFFF
  31 #define DB_88F6720_GPP_OUT_ENA_MID      0x7FFFFFFF
  32 #define DB_88F6720_GPP_OUT_ENA_HIGH     0xFFFFFFFF
  33 #define DB_88F6720_GPP_OUT_VAL_LOW      0x0
  34 #define DB_88F6720_GPP_OUT_VAL_MID      BIT(31) /* SATA Power output enable */
  35 #define DB_88F6720_GPP_OUT_VAL_HIGH     0x0
  36 #define DB_88F6720_GPP_POL_LOW          0x0
  37 #define DB_88F6720_GPP_POL_MID          0x0
  38 #define DB_88F6720_GPP_POL_HIGH         0x0
  39
  40 int board_early_init_f(void)
  41 {
  42         /* Configure MPP */
  43         writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
  44         writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
  45         writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
  46         writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
  47         writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
  48         writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
  49         writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
  50         writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
  51         writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
  52
  53         /* Configure GPIO */
  54         /* Set GPP Out value */
  55         writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  56         writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  57         writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
  58
  59         /* Set GPP Polarity */
  60         writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  61         writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  62         writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
  63
  64         /* Set GPP Out Enable */
  65         writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  66         writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  67         writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
  68
  69         return 0;
  70 }
  71
  72 int board_init(void)
  73 {
  74         /* adress of boot parameters */
  75         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  76
  77         return 0;
  78 }
  79
  80 int checkboard(void)
  81 {
  82         puts("Board: Marvell DB-88F6720\n");
  83
  84         return 0;
  85 }
  86
  87 int board_eth_init(bd_t *bis)
  88 {
  89         cpu_eth_init(bis); /* Built in controller(s) come first */
  90         return pci_eth_init(bis);
  91 }