board/Marvell/db-88f6820-gp/db-88f6820-gp.c

   1 /*
   2  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <miiphy.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/soc.h>
  13
  14 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define BIT(nr)                         (1UL << (nr))
  19
  20 #define ETH_PHY_CTRL_REG                0
  21 #define ETH_PHY_CTRL_POWER_DOWN_BIT     11
  22 #define ETH_PHY_CTRL_POWER_DOWN_MASK    (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
  23
  24 /*
  25  * Those values and defines are taken from the Marvell U-Boot version
  26  * "u-boot-2013.01-2014_T3.0"
  27  */
  28 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW                                   \
  29         (~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |  \
  30            BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |  \
  31            BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  32 #define DB_GP_88F68XX_GPP_OUT_ENA_MID                                   \
  33         (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |       \
  34            BIT(16) | BIT(17) | BIT(18)))
  35
  36 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW   0x0
  37 #define DB_GP_88F68XX_GPP_OUT_VAL_MID   0x0
  38 #define DB_GP_88F68XX_GPP_POL_LOW       0x0
  39 #define DB_GP_88F68XX_GPP_POL_MID       0x0
  40
  41 /* IO expander on Marvell GP board includes e.g. fan enabling */
  42 struct marvell_io_exp {
  43         u8 chip;
  44         u8 addr;
  45         u8 val;
  46 };
  47
  48 static struct marvell_io_exp io_exp[] = {
  49         { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  50         { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  51         { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  52         { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  53         { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
  54         { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
  55         { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  56         { 0x21, 3, 0xC0 }  /* Output Data, register#1 */
  57 };
  58
  59 /*
  60  * Define the DDR layout / topology here in the board file. This will
  61  * be used by the DDR3 init code in the SPL U-Boot version to configure
  62  * the DDR3 controller.
  63  */
  64 static struct hws_topology_map board_topology_map = {
  65         0x1, /* active interfaces */
  66         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  67         { { { {0x1, 0, 0, 0},
  68               {0x1, 0, 0, 0},
  69               {0x1, 0, 0, 0},
  70               {0x1, 0, 0, 0},
  71               {0x1, 0, 0, 0} },
  72             SPEED_BIN_DDR_1866L,        /* speed_bin */
  73             BUS_WIDTH_8,                /* memory_width */
  74             MEM_4G,                     /* mem_size */
  75             DDR_FREQ_800,               /* frequency */
  76             0, 0,                       /* cas_l cas_wl */
  77             HWS_TEMP_LOW} },            /* temperature */
  78         5,                              /* Num Of Bus Per Interface*/
  79         BUS_MASK_32BIT                  /* Busses mask */
  80 };
  81
  82 struct hws_topology_map *ddr3_get_topology_map(void)
  83 {
  84         /* Return the board topology as defined in the board code */
  85         return &board_topology_map;
  86 }
  87
  88 int board_early_init_f(void)
  89 {
  90         /* Configure MPP */
  91         writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  92         writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  93         writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  94         writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  95         writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  96         writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  97         writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  98         writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  99
 100         /* Set GPP Out value */
 101         writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 102         writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 103
 104         /* Set GPP Polarity */
 105         writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 106         writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 107
 108         /* Set GPP Out Enable */
 109         writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 110         writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 111
 112         return 0;
 113 }
 114
 115 int board_init(void)
 116 {
 117         int i;
 118
 119         /* adress of boot parameters */
 120         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 121
 122         /* Init I2C IO expanders */
 123         for (i = 0; i < ARRAY_SIZE(io_exp); i++)
 124                 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
 125
 126         return 0;
 127 }
 128
 129 int checkboard(void)
 130 {
 131         puts("Board: Marvell DB-88F6820-GP\n");
 132
 133         return 0;
 134 }