board/RPXlite/RPXlite.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  10  * U-Boot port on RPXlite board
  11  *
  12  * DRAM related UPMA register values are modified.
  13  * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
  14  */
  15
  16 #include <common.h>
  17 #include <mpc8xx.h>
  18
  19 /* ------------------------------------------------------------------------- */
  20
  21 static long int dram_size (long int, long int *, long int);
  22
  23 /* ------------------------------------------------------------------------- */
  24
  25 #define _NOT_USED_      0xFFFFCC25
  26
  27 const uint sdram_table[] = {
  28         /*
  29          * Single Read. (Offset 00h in UPMA RAM)
  30          */
  31         0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
  32         0x3FBFCC27,             /* last */
  33         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  34
  35         /*
  36          * Burst Read. (Offset 08h in UPMA RAM)
  37          */
  38         0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
  39         0x3FBFCC27,             /* last */
  40         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  41         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  42         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  43
  44         /*
  45          * Single Write. (Offset 18h in UPMA RAM)
  46          */
  47         0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
  48         0x3FFFCC27,             /* last */
  49         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50
  51         /*
  52          * Burst Write. (Offset 20h in UPMA RAM)
  53          */
  54         0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
  55         0x0CFFCC00, 0x33FFCC27, /* last */
  56         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58         _NOT_USED_, _NOT_USED_,
  59
  60         /*
  61          * Refresh. (Offset 30h in UPMA RAM)
  62          */
  63         0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
  64         0x3FFFCC27,             /* last */
  65         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  67
  68         /*
  69          * Exception. (Offset 3Ch in UPMA RAM)
  70          */
  71         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
  72 };
  73
  74 /* ------------------------------------------------------------------------- */
  75
  76
  77 /*
  78  * Check Board Identity:
  79  */
  80
  81 int checkboard (void)
  82 {
  83         puts ("Board: RPXlite\n");
  84         return (0);
  85 }
  86
  87 /* ------------------------------------------------------------------------- */
  88
  89 phys_size_t initdram (int board_type)
  90 {
  91         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  92         volatile memctl8xx_t *memctl = &immap->im_memctl;
  93         long int size10;
  94
  95         upmconfig (UPMA, (uint *) sdram_table,
  96                    sizeof (sdram_table) / sizeof (uint));
  97
  98         /* Refresh clock prescalar */
  99         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 100
 101         memctl->memc_mar = 0x00000000;
 102
 103         /* Map controller banks 1 to the SDRAM bank */
 104         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 105         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 106
 107         memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));     /* no refresh yet */
 108
 109         udelay (200);
 110
 111         /* perform SDRAM initializsation sequence */
 112
 113         memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - refresh twice */
 114         udelay (1);
 115
 116         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 117
 118         udelay (1000);
 119
 120         /* Check Bank 0 Memory Size
 121          * try 10 column mode
 122          */
 123
 124         size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 125                             SDRAM_MAX_SIZE);
 126
 127         return (size10);
 128 }
 129
 130 /* ------------------------------------------------------------------------- */
 131
 132 /*
 133  * Check memory range for valid RAM. A simple memory test determines
 134  * the actually available RAM size between addresses `base' and
 135  * `base + maxsize'. Some (not all) hardware errors are detected:
 136  * - short between address lines
 137  * - short between data lines
 138  */
 139
 140 static long int dram_size (long int mamr_value, long int *base,
 141                            long int maxsize)
 142 {
 143         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 144         volatile memctl8xx_t *memctl = &immap->im_memctl;
 145
 146         memctl->memc_mamr = mamr_value;
 147
 148         return (get_ram_size (base, maxsize));
 149 }