board/RPXlite_dw/RPXlite_dw.c

   1 /*
   2  * (C) Copyright 2004
   3  * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Sam Song
  10  * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
  11  * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
  12  * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
  13  */
  14
  15 #include <common.h>
  16 #include <mpc8xx.h>
  17
  18 /* ------------------------------------------------------------------------- */
  19 static long int dram_size (long int, long int *, long int);
  20 /* ------------------------------------------------------------------------- */
  21
  22 #define _NOT_USED_      0xFFFFCC25
  23
  24 const uint sdram_table[] =
  25 {
  26         /*
  27          * Single Read. (Offset 00h in UPMA RAM)
  28          */
  29         0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
  30         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  31         _NOT_USED_,
  32
  33         /*
  34          * Burst Read. (Offset 08h in UPMA RAM)
  35          */
  36         0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
  37         0x01FFCC20, 0x1FF74C20, /* last */
  38         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  39         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  40         _NOT_USED_, _NOT_USED_,
  41
  42         /*
  43          * Single Write. (Offset 18h in UPMA RAM)
  44          */
  45         0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
  46         _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
  47         _NOT_USED_,
  48
  49         /*
  50          * Burst Write. (Offset 20h in UPMA RAM)
  51          */
  52         0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
  53         0x01FFFC24, 0x1FF74C25, /* last */
  54         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56         _NOT_USED_, _NOT_USED_,
  57
  58         /*
  59          * Refresh. (Offset 30h in UPMA RAM)
  60          */
  61         0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
  62         _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
  63         0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
  64         /* INIT sequence RAM WORDS
  65          * SDRAM Initialization (offset 0x36 in UPMA RAM)
  66          * The above definition uses the remaining space
  67          * to establish an initialization sequence,
  68          * which is executed by a RUN command.
  69          * The sequence is COMMAND INHIBIT(NOP),Precharge,
  70          * Load Mode Register,NOP,Auto Refresh.
  71          */
  72
  73         /*
  74          * Exception. (Offset 3Ch in UPMA RAM)
  75          */
  76         0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
  77 };
  78
  79 /*
  80  * Check Board Identity:
  81  */
  82
  83 int checkboard (void)
  84 {
  85         puts ("Board: RPXlite_DW\n") ;
  86         return (0) ;
  87 }
  88
  89 /* ------------------------------------------------------------------------- */
  90
  91 phys_size_t initdram (int board_type)
  92 {
  93         volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
  94         volatile memctl8xx_t *memctl = &immap->im_memctl;
  95         long int size9;
  96
  97         upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
  98
  99         /* Refresh clock prescalar */
 100         memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
 101
 102         memctl->memc_mar  = 0x00000088;
 103
 104         /* Map controller banks 1 to the SDRAM bank */
 105         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 106         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 107
 108         memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 109         /*Disable Periodic timer A. */
 110
 111         udelay(200);
 112
 113         /* perform SDRAM initializsation sequence */
 114
 115         memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
 116
 117         udelay(1);
 118
 119         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 120
 121         /*Enable Periodic timer A */
 122
 123         udelay (1000);
 124
 125          /* Check Bank 0 Memory Size
 126           * try 9 column mode
 127           */
 128
 129         size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
 130
 131         /*
 132          * Final mapping:
 133          */
 134
 135         memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 136
 137         udelay (1000);
 138
 139         return (size9);
 140 }
 141
 142 void rpxlite_init (void)
 143 {
 144         /* Enable NVRAM */
 145         *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
 146 }
 147
 148 /*
 149  * Check memory range for valid RAM. A simple memory test determines
 150  * the actually available RAM size between addresses `base' and
 151  * `base + maxsize'. Some (not all) hardware errors are detected:
 152  * - short between address lines
 153  * - short between data lines
 154  */
 155 static long int dram_size (long int mamr_value, long int *base,
 156                            long int maxsize)
 157 {
 158         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 159         volatile memctl8xx_t *memctl = &immap->im_memctl;
 160
 161         memctl->memc_mamr = mamr_value;
 162
 163         return (get_ram_size (base, maxsize));
 164 }