board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c

   1 /*
   2  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3  * Copyright (C) 2012 Renesas Solutions Corp.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <asm/io.h>
  22 #include <asm/processor.h>
  23 #include <netdev.h>
  24 #include <i2c.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define MODEMR                  (0xFFCC0020)
  29 #define MODEMR_MASK             (0x6)
  30 #define MODEMR_533MHZ   (0x2)
  31
  32 int checkboard(void)
  33 {
  34         u32 r = readl(MODEMR);
  35         if ((r & MODEMR_MASK) & MODEMR_533MHZ)
  36                 puts("CPU Clock: 533MHz\n");
  37         else
  38                 puts("CPU Clock: 400MHz\n");
  39
  40         puts("BOARD: Alpha Project. AP-SH4A-4A\n");
  41         return 0;
  42 }
  43
  44 #define MSTPSR1                 (0xFFC80044)
  45 #define MSTPCR1                 (0xFFC80034)
  46 #define MSTPSR1_GETHER  (1 << 14)
  47
  48 /* IPSR3 */
  49 #define ET0_ETXD0 (0x4 << 3)
  50 #define ET0_GTX_CLK_A (0x4 << 6)
  51 #define ET0_ETXD1_A (0x4 << 9)
  52 #define ET0_ETXD2_A (0x4 << 12)
  53 #define ET0_ETXD3_A (0x4 << 15)
  54 #define ET0_ETXD4 (0x3 << 18)
  55 #define ET0_ETXD5_A (0x5 << 21)
  56 #define ET0_ETXD6_A (0x5 << 24)
  57 #define ET0_ETXD7 (0x4 << 27)
  58 #define IPSR3_ETH_ENABLE \
  59         (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
  60         ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
  61
  62 /* IPSR4 */
  63 #define ET0_ERXD7       (0x4)
  64 #define ET0_RX_DV       (0x4 << 3)
  65 #define ET0_RX_ER       (0x4 << 6)
  66 #define ET0_CRS         (0x4 << 9)
  67 #define ET0_COL         (0x4 << 12)
  68 #define ET0_MDC         (0x4 << 15)
  69 #define ET0_MDIO_A      (0x3 << 18)
  70 #define ET0_LINK_A      (0x3 << 20)
  71 #define ET0_PHY_INT_A (0x3 << 24)
  72
  73 #define IPSR4_ETH_ENABLE \
  74         (ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
  75         ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
  76
  77 /* IPSR8 */
  78 #define ET0_ERXD0       (0x4 << 20)
  79 #define ET0_ERXD1       (0x4 << 23)
  80 #define ET0_ERXD2_A (0x3 << 26)
  81 #define ET0_ERXD3_A (0x3 << 28)
  82 #define IPSR8_ETH_ENABLE \
  83         (ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
  84
  85 /* IPSR10 */
  86 #define RX4_D   (0x1 << 22)
  87 #define TX4_D   (0x1 << 23)
  88 #define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
  89
  90 /* IPSR11 */
  91 #define ET0_ERXD4       (0x4 <<  4)
  92 #define ET0_ERXD5       (0x4 <<  7)
  93 #define ET0_ERXD6       (0x3 << 10)
  94 #define ET0_TX_EN       (0x2 << 19)
  95 #define ET0_TX_ER       (0x2 << 21)
  96 #define ET0_TX_CLK_A (0x4 << 23)
  97 #define ET0_RX_CLK_A (0x3 << 26)
  98 #define IPSR11_ETH_ENABLE \
  99         (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
 100         ET0_TX_CLK_A | ET0_RX_CLK_A)
 101
 102 #define GPSR1_INIT (0xFFFF7FFF)
 103 #define GPSR2_INIT (0x4005FEFF)
 104 #define GPSR3_INIT (0x2EFFFFFF)
 105 #define GPSR4_INIT (0xC7000000)
 106
 107 int board_init(void)
 108 {
 109         u32 data;
 110
 111         /* Set IPSR register */
 112         data = readl(IPSR3);
 113         data |= IPSR3_ETH_ENABLE;
 114         writel(~data, PMMR);
 115         writel(data, IPSR3);
 116
 117         data = readl(IPSR4);
 118         data |= IPSR4_ETH_ENABLE;
 119         writel(~data, PMMR);
 120         writel(data, IPSR4);
 121
 122         data = readl(IPSR8);
 123         data |= IPSR8_ETH_ENABLE;
 124         writel(~data, PMMR);
 125         writel(data, IPSR8);
 126
 127         data = readl(IPSR10);
 128         data |= IPSR10_SCIF_ENABLE;
 129         writel(~data, PMMR);
 130         writel(data, IPSR10);
 131
 132         data = readl(IPSR11);
 133         data |= IPSR11_ETH_ENABLE;
 134         writel(~data, PMMR);
 135         writel(data, IPSR11);
 136
 137         /* GPIO select */
 138         data = GPSR1_INIT;
 139         writel(~data, PMMR);
 140         writel(data, GPSR1);
 141
 142         data = GPSR2_INIT;
 143         writel(~data, PMMR);
 144         writel(data, GPSR2);
 145
 146         data = GPSR3_INIT;
 147         writel(~data, PMMR);
 148         writel(data, GPSR3);
 149
 150         data = GPSR4_INIT;
 151         writel(~data, PMMR);
 152         writel(data, GPSR4);
 153
 154         data = 0x0;
 155         writel(~data, PMMR);
 156         writel(data, GPSR5);
 157
 158         /* mode select */
 159         data = MODESEL2_INIT;
 160         writel(~data, PMMR);
 161         writel(data, MODESEL2);
 162
 163 #if defined(CONFIG_SH_ETHER)
 164         u32 r = readl(MSTPSR1);
 165         if (r & MSTPSR1_GETHER)
 166                 writel((r & ~MSTPSR1_GETHER), MSTPCR1);
 167 #endif
 168         return 0;
 169 }
 170
 171 int board_late_init(void)
 172 {
 173         u8 mac[6];
 174
 175         /* Read Mac Address and set*/
 176         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 177         i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
 178
 179         /* Read MAC address */
 180         i2c_read(0x50, 0x0, 0, mac, 6);
 181
 182         if (is_valid_ether_addr(mac))
 183                 eth_setenv_enetaddr("ethaddr", mac);
 184
 185         return 0;
 186 }
 187
 188 int dram_init(void)
 189 {
 190         gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 191         gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 192         printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 193
 194         return 0;
 195 }