board/amcc/acadia/memory.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* define DEBUG for debugging output (obviously ;-)) */
   9 #if 0
  10 #define DEBUG
  11 #endif
  12
  13 #include <common.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <asm/ppc4xx-gpio.h>
  17
  18 extern void board_pll_init_f(void);
  19
  20 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  21 static void cram_bcr_write(u32 wr_val)
  22 {
  23         wr_val <<= 2;
  24
  25         /* set CRAM_CRE to 1 */
  26         gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
  27
  28         /* Write BCR to CRAM on CS1 */
  29         out32(wr_val + 0x00200000, 0);
  30         debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
  31
  32         /* Write BCR to CRAM on CS2 */
  33         out32(wr_val + 0x02200000, 0);
  34         debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
  35
  36         sync();
  37         eieio();
  38
  39         /* set CRAM_CRE back to 0 (normal operation) */
  40         gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
  41
  42         return;
  43 }
  44 #endif
  45
  46 phys_size_t initdram(int board_type)
  47 {
  48 #if defined(CONFIG_NAND_SPL)
  49         u32 reg;
  50
  51         /* don't reinit PLL when booting via I2C bootstrap option */
  52         mfsdr(SDR0_PINSTP, reg);
  53         if (reg != 0xf0000000)
  54                 board_pll_init_f();
  55 #endif
  56
  57 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  58         int i;
  59         u32 val;
  60
  61         /* 1. EBC need to program READY, CLK, ADV for ASync mode */
  62         gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  63         gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  64         gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  65         gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
  66
  67         /* 2. EBC in Async mode */
  68         mtebc(PB1AP, 0x078F1EC0);
  69         mtebc(PB2AP, 0x078F1EC0);
  70         mtebc(PB1CR, 0x000BC000);
  71         mtebc(PB2CR, 0x020BC000);
  72
  73         /* 3. Set CRAM in Sync mode */
  74         cram_bcr_write(0x7012);         /* CRAM burst setting */
  75
  76         /* 4. EBC in Sync mode */
  77         mtebc(PB1AP, 0x9C0201C0);
  78         mtebc(PB2AP, 0x9C0201C0);
  79
  80         /* Set GPIO pins back to alternate function */
  81         gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  82         gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  83
  84         /* Config EBC to use RDY */
  85         mfsdr(SDR0_ULTRA0, val);
  86         mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
  87
  88         /* Wait a short while, since for NAND booting this is too fast */
  89         for (i=0; i<200000; i++)
  90                 ;
  91 #endif
  92
  93         return (CONFIG_SYS_MBYTES_RAM << 20);
  94 }