3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/ppc440.h>
11 #include <fdt_support.h>
13 #include <asm/processor.h>
16 #include <asm/4xx_pcie.h>
17 #include <asm/ppc4xx-gpio.h>
18 #include <asm/errno.h>
21 extern flash_info_t flash_info
[CONFIG_SYS_MAX_FLASH_BANKS
]; /* info for FLASH chips */
23 DECLARE_GLOBAL_DATA_PTR
;
37 #define BOARD_CANYONLANDS_PCIE 1
38 #define BOARD_CANYONLANDS_SATA 2
39 #define BOARD_GLACIER 3
40 #define BOARD_ARCHES 4
43 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
44 * board specific values.
46 #if defined(CONFIG_ARCHES)
47 u32
ddr_wrdtr(u32 default_val
) {
48 return (SDRAM_WRDTR_LLWP_1_CYC
| SDRAM_WRDTR_WTR_0_DEG
| 0x823);
51 u32
ddr_wrdtr(u32 default_val
) {
52 return (SDRAM_WRDTR_LLWP_1_CYC
| SDRAM_WRDTR_WTR_180_DEG_ADV
| 0x823);
55 u32
ddr_clktr(u32 default_val
) {
56 return (SDRAM_CLKTR_CLKP_90_DEG_ADV
);
60 #if defined(CONFIG_ARCHES)
62 * FPGA read/write helper macros
64 static inline int board_fpga_read(int offset
)
68 data
= in_8((void *)(CONFIG_SYS_FPGA_BASE
+ offset
));
73 static inline void board_fpga_write(int offset
, int data
)
75 out_8((void *)(CONFIG_SYS_FPGA_BASE
+ offset
), data
);
79 * CPLD read/write helper macros
81 static inline int board_cpld_read(int offset
)
85 out_8((void *)(CONFIG_SYS_CPLD_ADDR
), offset
);
86 data
= in_8((void *)(CONFIG_SYS_CPLD_DATA
));
91 static inline void board_cpld_write(int offset
, int data
)
93 out_8((void *)(CONFIG_SYS_CPLD_ADDR
), offset
);
94 out_8((void *)(CONFIG_SYS_CPLD_DATA
), data
);
97 static int pvr_460ex(void)
101 if ((pvr
== PVR_460EX_RA
) || (pvr
== PVR_460EX_SE_RA
) ||
102 (pvr
== PVR_460EX_RB
))
107 #endif /* defined(CONFIG_ARCHES) */
109 int board_early_init_f(void)
111 #if !defined(CONFIG_ARCHES)
113 struct board_bcsr
*bcsr_data
=
114 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
119 * Setup the interrupt controller polarities, triggers, etc.
121 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
122 mtdcr(UIC0ER
, 0x00000000); /* disable all */
123 mtdcr(UIC0CR
, 0x00000005); /* ATI & UIC1 crit are critical */
124 mtdcr(UIC0PR
, 0xffffffff); /* per ref-board manual */
125 mtdcr(UIC0TR
, 0x00000000); /* per ref-board manual */
126 mtdcr(UIC0VR
, 0x00000000); /* int31 highest, base=0x000 */
127 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
129 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
130 mtdcr(UIC1ER
, 0x00000000); /* disable all */
131 mtdcr(UIC1CR
, 0x00000000); /* all non-critical */
132 mtdcr(UIC1PR
, 0xffffffff); /* per ref-board manual */
133 mtdcr(UIC1TR
, 0x00000000); /* per ref-board manual */
134 mtdcr(UIC1VR
, 0x00000000); /* int31 highest, base=0x000 */
135 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
137 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
138 mtdcr(UIC2ER
, 0x00000000); /* disable all */
139 mtdcr(UIC2CR
, 0x00000000); /* all non-critical */
140 mtdcr(UIC2PR
, 0xffffffff); /* per ref-board manual */
141 mtdcr(UIC2TR
, 0x00000000); /* per ref-board manual */
142 mtdcr(UIC2VR
, 0x00000000); /* int31 highest, base=0x000 */
143 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
145 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
146 mtdcr(UIC3ER
, 0x00000000); /* disable all */
147 mtdcr(UIC3CR
, 0x00000000); /* all non-critical */
148 mtdcr(UIC3PR
, 0xffffffff); /* per ref-board manual */
149 mtdcr(UIC3TR
, 0x00000000); /* per ref-board manual */
150 mtdcr(UIC3VR
, 0x00000000); /* int31 highest, base=0x000 */
151 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
153 #if !defined(CONFIG_ARCHES)
154 /* SDR Setting - enable NDFC */
155 mfsdr(SDR0_CUST0
, sdr0_cust0
);
156 sdr0_cust0
= SDR0_CUST0_MUX_NDFC_SEL
|
157 SDR0_CUST0_NDFC_ENABLE
|
158 SDR0_CUST0_NDFC_BW_8_BIT
|
159 SDR0_CUST0_NDFC_ARE_MASK
|
160 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
161 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS
));
162 mtsdr(SDR0_CUST0
, sdr0_cust0
);
166 * Configure PFC (Pin Function Control) registers
169 mtsdr(SDR0_PFC1
, 0x00040000);
171 /* Enable PCI host functionality in SDR0_PCI0 */
172 mtsdr(SDR0_PCI0
, 0xe0000000);
174 #if !defined(CONFIG_ARCHES)
175 /* Enable ethernet and take out of reset */
176 out_8(&bcsr_data
->eth_ctrl
, 0) ;
178 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
179 out_8(&bcsr_data
->flash_ctrl
, 0) ;
180 mtsdr(SDR0_SRST1
, 0); /* Pull AHB out of reset default=1 */
182 /* Setup PLB4-AHB bridge based on the system address map */
183 mtdcr(AHB_TOP
, 0x8000004B);
184 mtdcr(AHB_BOT
, 0x8000004B);
191 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
192 int board_usb_init(int index
, enum usb_init_type init
)
194 struct board_bcsr
*bcsr_data
=
195 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
198 /* Enable USB host & USB-OTG */
199 val
= in_8(&bcsr_data
->usb_ctrl
);
200 val
&= ~(BCSR_USBCTRL_OTG_RST
| BCSR_USBCTRL_HOST_RST
);
201 out_8(&bcsr_data
->usb_ctrl
, val
);
204 * Configure USB-STP pins as alternate and not GPIO
205 * It seems to be neccessary to configure the STP pins as GPIO
206 * input at powerup (perhaps while USB reset is asserted). So
207 * we configure those pins to their "real" function now.
209 gpio_config(16, GPIO_OUT
, GPIO_ALT1
, GPIO_OUT_1
);
210 gpio_config(19, GPIO_OUT
, GPIO_ALT1
, GPIO_OUT_1
);
215 int usb_board_stop(void)
217 struct board_bcsr
*bcsr_data
=
218 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
221 /* Disable USB host & USB-OTG */
222 val
= in_8(&bcsr_data
->usb_ctrl
);
223 val
|= (BCSR_USBCTRL_OTG_RST
| BCSR_USBCTRL_HOST_RST
);
224 out_8(&bcsr_data
->usb_ctrl
, val
);
226 /* Reconfigure USB-STP pins as input */
227 gpio_config(16, GPIO_IN
, GPIO_SEL
, GPIO_OUT_0
);
228 gpio_config(19, GPIO_IN
, GPIO_SEL
, GPIO_OUT_0
);
233 int board_usb_cleanup(int index
, enum usb_init_type init
)
235 return usb_board_stop();
237 #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
239 #if !defined(CONFIG_ARCHES)
240 static void canyonlands_sata_init(int board_type
)
244 if (board_type
== BOARD_CANYONLANDS_SATA
) {
245 /* Put SATA in reset */
246 SDR_WRITE(SDR0_SRST1
, 0x00020001);
248 /* Set the phy for SATA, not PCI-E port 0 */
249 reg
= SDR_READ(PESDR0_PHY_CTL_RST
);
250 SDR_WRITE(PESDR0_PHY_CTL_RST
, (reg
& 0xeffffffc) | 0x00000001);
251 reg
= SDR_READ(PESDR0_L0CLK
);
252 SDR_WRITE(PESDR0_L0CLK
, (reg
& 0xfffffff8) | 0x00000007);
253 SDR_WRITE(PESDR0_L0CDRCTL
, 0x00003111);
254 SDR_WRITE(PESDR0_L0DRV
, 0x00000104);
256 /* Bring SATA out of reset */
257 SDR_WRITE(SDR0_SRST1
, 0x00000000);
260 #endif /* !defined(CONFIG_ARCHES) */
262 int get_cpu_num(void)
264 int cpu
= NA_OR_UNKNOWN_CPU
;
266 #if defined(CONFIG_ARCHES)
269 cpu_num
= board_fpga_read(0x3);
271 /* sanity check; assume cpu numbering starts and increments from 0 */
272 if ((cpu_num
>= 0) && (cpu_num
< CONFIG_BD_NUM_CPUS
))
279 #if !defined(CONFIG_ARCHES)
282 struct board_bcsr
*bcsr_data
=
283 (struct board_bcsr
*)CONFIG_SYS_BCSR_BASE
;
285 int i
= getenv_f("serial#", buf
, sizeof(buf
));
288 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
289 if (in_8(&bcsr_data
->board_status
) & BCSR_SELECT_PCIE
)
290 gd
->board_type
= BOARD_CANYONLANDS_PCIE
;
292 gd
->board_type
= BOARD_CANYONLANDS_SATA
;
294 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
295 gd
->board_type
= BOARD_GLACIER
;
298 switch (gd
->board_type
) {
299 case BOARD_CANYONLANDS_PCIE
:
304 case BOARD_CANYONLANDS_SATA
:
305 puts(", 1*PCIe/1*SATA");
309 printf(", Rev. %X", in_8(&bcsr_data
->cpld_rev
));
317 canyonlands_sata_init(gd
->board_type
);
322 #else /* defined(CONFIG_ARCHES) */
326 char *s
= getenv("serial#");
328 printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
329 printf(" Revision %02x.%02x ",
330 board_fpga_read(0x0), board_fpga_read(0x1));
332 gd
->board_type
= BOARD_ARCHES
;
334 /* Only CPU0 has access to CPLD registers */
335 if (get_cpu_num() == 0) {
336 u8 cfg_sw
= board_cpld_read(0x1);
337 printf("(FPGA=%02x, CPLD=%02x)\n",
338 board_fpga_read(0x2), board_cpld_read(0x0));
339 printf(" Configuration Switch %d%d%d%d\n",
340 ((cfg_sw
>> 3) & 0x01),
341 ((cfg_sw
>> 2) & 0x01),
342 ((cfg_sw
>> 1) & 0x01),
343 ((cfg_sw
>> 0) & 0x01));
345 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
349 printf(" Serial# %s\n", s
);
353 #endif /* !defined(CONFIG_ARCHES) */
355 #if defined(CONFIG_PCI)
356 int board_pcie_first(void)
359 * Canyonlands with SATA enabled has only one PCIe slot
362 if (gd
->board_type
== BOARD_CANYONLANDS_SATA
)
367 #endif /* CONFIG_PCI */
369 int board_early_init_r (void)
372 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
373 * boot EBC mapping only supports a maximum of 16MBytes
374 * (4.ff00.0000 - 4.ffff.ffff).
375 * To solve this problem, the FLASH has to get remapped to another
376 * EBC address which accepts bigger regions:
378 * 0xfc00.0000 -> 4.cc00.0000
381 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
382 mtebc(PB0CR
, CONFIG_SYS_FLASH_BASE_PHYS_L
| 0xda000);
384 /* Remove TLB entry of boot EBC mapping */
385 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR
, 16 << 20);
387 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
388 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS
, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_SIZE
,
392 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
393 * 0xfc00.0000 is possible
397 * Clear potential errors resulting from auto-calibration.
398 * If not done, then we could get an interrupt later on when
399 * exceptions are enabled.
401 set_mcsr(get_mcsr());
406 #if !defined(CONFIG_ARCHES)
407 int misc_init_r(void)
414 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
415 * This is board specific, so let's do it here.
417 mfsdr(SDR0_ETH_CFG
, eth_cfg
);
418 /* disable SGMII mode */
419 eth_cfg
&= ~(SDR0_ETH_CFG_SGMII2_ENABLE
|
420 SDR0_ETH_CFG_SGMII1_ENABLE
|
421 SDR0_ETH_CFG_SGMII0_ENABLE
);
422 /* Set the for 2 RGMII mode */
423 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
424 eth_cfg
&= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL
;
426 eth_cfg
|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL
;
428 eth_cfg
&= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL
;
429 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
432 * The AHB Bridge core is held in reset after power-on or reset
435 mfsdr(SDR0_SRST1
, sdr0_srst1
);
436 sdr0_srst1
&= ~SDR0_SRST1_AHB
;
437 mtsdr(SDR0_SRST1
, sdr0_srst1
);
441 * Disable square wave output: Batterie will be drained
442 * quickly, when this output is not disabled
444 val
= i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR
, 0xa);
446 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR
, 0xa, val
);
451 #else /* defined(CONFIG_ARCHES) */
453 int misc_init_r(void)
460 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
461 * This is board specific, so let's do it here.
464 /* enable SGMII mode */
465 eth_cfg
|= (SDR0_ETH_CFG_SGMII0_ENABLE
|
466 SDR0_ETH_CFG_SGMII1_ENABLE
|
467 SDR0_ETH_CFG_SGMII2_ENABLE
);
469 /* Set EMAC for MDIO */
470 eth_cfg
|= SDR0_ETH_CFG_MDIO_SEL_EMAC0
;
472 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
473 eth_cfg
|= (SDR0_ETH_CFG_TAHOE0_BYPASS
| SDR0_ETH_CFG_TAHOE1_BYPASS
);
475 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
477 /* reset all SGMII interfaces */
478 mfsdr(SDR0_SRST1
, reg
);
479 reg
|= (SDR0_SRST1_SGMII0
| SDR0_SRST1_SGMII1
| SDR0_SRST1_SGMII2
);
480 mtsdr(SDR0_SRST1
, reg
);
481 mtsdr(SDR0_ETH_STS
, 0xFFFFFFFF);
482 mtsdr(SDR0_SRST1
, 0x00000000);
485 mfsdr(SDR0_ETH_PLL
, eth_pll
);
486 } while (!(eth_pll
& SDR0_ETH_PLL_PLLLOCK
));
490 #endif /* !defined(CONFIG_ARCHES) */
492 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
493 extern int __ft_board_setup(void *blob
, bd_t
*bd
);
495 int ft_board_setup(void *blob
, bd_t
*bd
)
497 __ft_board_setup(blob
, bd
);
499 if (gd
->board_type
== BOARD_CANYONLANDS_SATA
) {
501 * When SATA is selected we need to disable the first PCIe
502 * node in the device tree, so that Linux doesn't initialize
505 fdt_find_and_setprop(blob
, "/plb/pciex@d00000000", "status",
506 "disabled", sizeof("disabled"), 1);
509 if (gd
->board_type
== BOARD_CANYONLANDS_PCIE
) {
511 * When PCIe is selected we need to disable the SATA
512 * node in the device tree, so that Linux doesn't initialize
515 fdt_find_and_setprop(blob
, "/plb/sata@bffd1000", "status",
516 "disabled", sizeof("disabled"), 1);
521 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */