]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/amcc/ebony/ebony.c
2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 #define BOOT_SMALL_FLASH 32 /* 00100000 */
28 #define FLASH_ONBD_N 2 /* 00000010 */
29 #define FLASH_SRAM_SEL 1 /* 00000001 */
31 DECLARE_GLOBAL_DATA_PTR
;
33 long int fixed_sdram(void);
35 int board_early_init_f(void)
38 unsigned char *fpga_base
= (unsigned char *)CONFIG_SYS_FPGA_BASE
;
41 /*--------------------------------------------------------------------
42 * Setup the external bus controller/chip selects
43 *-------------------------------------------------------------------*/
44 mtdcr(EBC0_CFGADDR
, EBC0_CFG
);
45 reg
= mfdcr(EBC0_CFGDATA
);
46 mtdcr(EBC0_CFGDATA
, reg
| 0x04000000); /* Set ATC */
48 mtebc(PB1AP
, 0x02815480); /* NVRAM/RTC */
49 mtebc(PB1CR
, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
50 mtebc(PB7AP
, 0x01015280); /* FPGA registers */
51 mtebc(PB7CR
, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
53 /* read FPGA_REG0 and set the bus controller */
55 if ((status
& BOOT_SMALL_FLASH
) && !(status
& FLASH_ONBD_N
)) {
56 mtebc(PB0AP
, 0x9b015480); /* FLASH/SRAM */
57 mtebc(PB0CR
, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
58 mtebc(PB2AP
, 0x9b015480); /* 4MB FLASH */
59 mtebc(PB2CR
, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
61 mtebc(PB0AP
, 0x9b015480); /* 4MB FLASH */
62 mtebc(PB0CR
, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
64 /* set CS2 if FLASH_ONBD_N == 0 */
65 if (!(status
& FLASH_ONBD_N
)) {
66 mtebc(PB2AP
, 0x9b015480); /* FLASH/SRAM */
67 mtebc(PB2CR
, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
71 /*--------------------------------------------------------------------
72 * Setup the interrupt controller polarities, triggers, etc.
73 *-------------------------------------------------------------------*/
74 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
75 mtdcr(UIC0ER
, 0x00000000); /* disable all */
76 mtdcr(UIC0CR
, 0x00000009); /* SMI & UIC1 crit are critical */
77 mtdcr(UIC0PR
, 0xfffffe13); /* per ref-board manual */
78 mtdcr(UIC0TR
, 0x01c00008); /* per ref-board manual */
79 mtdcr(UIC0VR
, 0x00000001); /* int31 highest, base=0x000 */
80 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
82 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
83 mtdcr(UIC1ER
, 0x00000000); /* disable all */
84 mtdcr(UIC1CR
, 0x00000000); /* all non-critical */
85 mtdcr(UIC1PR
, 0xffffe0ff); /* per ref-board manual */
86 mtdcr(UIC1TR
, 0x00ffc000); /* per ref-board manual */
87 mtdcr(UIC1VR
, 0x00000001); /* int31 highest, base=0x000 */
88 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
96 int i
= getenv_f("serial#", buf
, sizeof(buf
));
98 printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
108 phys_size_t
initdram(int board_type
)
112 #if defined(CONFIG_SPD_EEPROM)
113 dram_size
= spd_sdram();
115 dram_size
= fixed_sdram();
120 #if !defined(CONFIG_SPD_EEPROM)
121 /*************************************************************************
122 * fixed sdram init -- doesn't use serial presence detect.
124 * Assumes: 128 MB, non-ECC, non-registered
127 ************************************************************************/
128 long int fixed_sdram(void)
132 /*--------------------------------------------------------------------
134 *------------------------------------------------------------------*/
135 mtsdram(SDRAM0_UABBA
, 0x00000000); /* ubba=0 (default) */
136 mtsdram(SDRAM0_SLIO
, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
137 mtsdram(SDRAM0_DEVOPT
, 0x00000000); /* dll=0 ds=0 (normal) */
138 mtsdram(SDRAM0_WDDCTR
, 0x00000000); /* wrcp=0 dcd=0 */
139 mtsdram(SDRAM0_CLKTR
, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
141 /*--------------------------------------------------------------------
142 * Setup for board-specific specific mem
143 *------------------------------------------------------------------*/
145 * Following for CAS Latency = 2.5 @ 133 MHz PLB
147 mtsdram(SDRAM0_B0CR
, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
148 mtsdram(SDRAM0_TR0
, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
150 mtsdram(SDRAM0_TR1
, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
151 mtsdram(SDRAM0_RTR
, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
152 mtsdram(SDRAM0_CFG1
, 0x00000000); /* Self-refresh exit, disable PM */
153 udelay(400); /* Delay 200 usecs (min) */
155 /*--------------------------------------------------------------------
156 * Enable the controller, then wait for DCEN to complete
157 *------------------------------------------------------------------*/
158 mtsdram(SDRAM0_CFG0
, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
160 mfsdram(SDRAM0_MCSTS
, reg
);
161 if (reg
& 0x80000000)
165 return (128 * 1024 * 1024); /* 128 MB */
167 #endif /* !defined(CONFIG_SPD_EEPROM) */