3 * John Otken, jotken@softadvances.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/ppc4xx-isram.h>
29 #include <spd_sdram.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 extern flash_info_t flash_info
[CONFIG_SYS_MAX_FLASH_BANKS
]; /* info for FLASH chips */
37 /*************************************************************************
38 * int board_early_init_f()
40 ************************************************************************/
41 int board_early_init_f(void)
45 mtebc( PB0AP
, 0x03800000 ); /* set chip selects */
46 mtebc( PB0CR
, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
47 mtebc( PB1AP
, 0x03800000 );
48 mtebc( PB1CR
, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
49 mtebc( PB2AP
, 0x03800000 );
50 mtebc( PB2CR
, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
52 mtdcr( uic1sr
, 0xffffffff ); /* Clear all interrupts */
53 mtdcr( uic1er
, 0x00000000 ); /* disable all interrupts */
54 mtdcr( uic1cr
, 0x00000000 ); /* Set Critical / Non Critical interrupts */
55 mtdcr( uic1pr
, 0x7fff83ff ); /* Set Interrupt Polarities */
56 mtdcr( uic1tr
, 0x001f8000 ); /* Set Interrupt Trigger Levels */
57 mtdcr( uic1vr
, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
58 mtdcr( uic1sr
, 0x00000000 ); /* clear all interrupts */
59 mtdcr( uic1sr
, 0xffffffff );
61 mtdcr( uic0sr
, 0xffffffff ); /* Clear all interrupts */
62 mtdcr( uic0er
, 0x00000000 ); /* disable all interrupts excepted cascade */
63 mtdcr( uic0cr
, 0x00000001 ); /* Set Critical / Non Critical interrupts */
64 mtdcr( uic0pr
, 0xffffffff ); /* Set Interrupt Polarities */
65 mtdcr( uic0tr
, 0x01000004 ); /* Set Interrupt Trigger Levels */
66 mtdcr( uic0vr
, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
67 mtdcr( uic0sr
, 0x00000000 ); /* clear all interrupts */
68 mtdcr( uic0sr
, 0xffffffff );
71 mfr
|= SDR0_MFR_FIXD
; /* Workaround for PCI/DMA */
78 /*************************************************************************
81 ************************************************************************/
84 volatile epld_t
*x
= (epld_t
*) CONFIG_SYS_EPLD_BASE
;
86 /* set modes of operation */
87 x
->ethuart
|= EPLD2_ETH_MODE_10
| EPLD2_ETH_MODE_100
|
88 EPLD2_ETH_MODE_1000
| EPLD2_ETH_DUPLEX_MODE
;
89 /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
90 x
->ethuart
&= ~EPLD2_ETH_AUTO_NEGO
;
92 /* put Ethernet+PHY in reset */
93 x
->ethuart
&= ~EPLD2_RESET_ETH_N
;
95 /* take Ethernet+PHY out of reset */
96 x
->ethuart
|= EPLD2_RESET_ETH_N
;
102 /*************************************************************************
105 ************************************************************************/
108 char *s
= getenv("serial#");
110 printf("Board: Luan - AMCC PPC440SP Evaluation Board");
122 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
123 * board specific values.
125 u32
ddr_clktr(u32 default_val
) {
126 return (SDRAM_CLKTR_CLKP_180_DEG_ADV
);
129 /*************************************************************************
132 * This routine is called just prior to registering the hose and gives
133 * the board the opportunity to check things. Returning a value of zero
134 * indicates that things are bad & PCI initialization should be aborted.
136 * Different boards may wish to customize the pci controller structure
137 * (add regions, override default access routines, etc) or perform
138 * certain pre-initialization actions.
140 ************************************************************************/
141 #if defined(CONFIG_PCI)
142 int pci_pre_init( struct pci_controller
*hose
)
146 /*--------------------------------------------------------------------------+
147 * The luan board is always configured as the host & requires the
148 * PCI arbiter to be enabled.
149 *--------------------------------------------------------------------------*/
150 mfsdr(SDR0_SDSTP1
, strap
);
151 if( (strap
& SDR0_SDSTP1_PAE_MASK
) == 0 ) {
152 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap
);
159 #endif /* defined(CONFIG_PCI) */
162 /*************************************************************************
165 * The bootstrap configuration provides default settings for the pci
166 * inbound map (PIM). But the bootstrap config choices are limited and
167 * may not be sufficient for a given board.
169 ************************************************************************/
170 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
171 void pci_target_init(struct pci_controller
*hose
)
173 /*--------------------------------------------------------------------------+
175 *--------------------------------------------------------------------------*/
176 out32r( PCIX0_PIM0SA
, 0 ); /* disable */
177 out32r( PCIX0_PIM1SA
, 0 ); /* disable */
178 out32r( PCIX0_PIM2SA
, 0 ); /* disable */
179 out32r( PCIX0_EROMBA
, 0 ); /* disable expansion rom */
181 /*--------------------------------------------------------------------------+
182 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
183 * options to not support sizes such as 128/256 MB.
184 *--------------------------------------------------------------------------*/
185 out32r( PCIX0_PIM0LAL
, CONFIG_SYS_SDRAM_BASE
);
186 out32r( PCIX0_PIM0LAH
, 0 );
187 out32r( PCIX0_PIM0SA
, ~(gd
->ram_size
- 1) | 1 );
189 out32r( PCIX0_BAR0
, 0 );
191 /*--------------------------------------------------------------------------+
192 * Program the board's subsystem id/vendor id
193 *--------------------------------------------------------------------------*/
194 out16r( PCIX0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
195 out16r( PCIX0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
197 out16r( PCIX0_CMD
, in16r(PCIX0_CMD
) | PCI_COMMAND_MEMORY
);
199 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
202 /*************************************************************************
205 * This routine is called to determine if a pci scan should be
206 * performed. With various hardware environments (especially cPCI and
207 * PPMC) it's insufficient to depend on the state of the arbiter enable
208 * bit in the strap register, or generic host/adapter assumptions.
210 * Rather than hard-code a bad assumption in the general 440 code, the
211 * 440 pci code requires the board to decide at runtime.
213 * Return 0 for adapter mode, non-zero for host (monarch) mode.
216 ************************************************************************/
217 #if defined(CONFIG_PCI)
218 int is_pci_host(struct pci_controller
*hose
)
222 #endif /* defined(CONFIG_PCI) */
225 /*************************************************************************
228 * This routine is called to reset (keep alive) the watchdog timer
230 ************************************************************************/
231 #if defined(CONFIG_HW_WATCHDOG)
232 void hw_watchdog_reset(void)
238 /*************************************************************************
241 ************************************************************************/
242 static int on_off( const char *s
)
244 if (strcmp(s
, "on") == 0) {
246 } else if (strcmp(s
, "off") == 0) {
253 /*************************************************************************
254 * void l2cache_disable()
256 ************************************************************************/
257 static void l2cache_disable(void)
259 mtdcr( L2_CACHE_CFG
, 0 );
263 /*************************************************************************
264 * void l2cache_enable()
266 ************************************************************************/
267 static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
269 mtdcr( L2_CACHE_CFG
, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
271 mtdcr( L2_CACHE_ADDR
, 0 ); /* set L2_ADDR with all zeros */
273 mtdcr( L2_CACHE_CMD
, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
275 while (!(mfdcr( L2_CACHE_STAT
) & 0x80000000 )) ;; /* poll L2_SR for completion */
277 mtdcr( L2_CACHE_CMD
, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
279 mtdcr( L2_CACHE_CMD
, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
281 mtdcr( L2_CACHE_SNP0
, 0 ); /* snoop registers */
282 mtdcr( L2_CACHE_SNP1
, 0 );
284 __asm__
volatile ("sync"); /* msync */
286 mtdcr( L2_CACHE_CFG
, 0xe0000000 ); /* inst and data use L2 */
288 __asm__
volatile ("sync");
292 /*************************************************************************
293 * int l2cache_status()
295 ************************************************************************/
296 static int l2cache_status(void)
298 return (mfdcr( L2_CACHE_CFG
) & 0x60000000) != 0;
302 /*************************************************************************
305 ************************************************************************/
306 int do_l2cache( cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[] )
309 case 2: /* on / off */
310 switch (on_off(argv
[1])) {
311 case 0: l2cache_disable();
313 case 1: l2cache_enable();
317 case 1: /* get status */
318 printf ("L2 Cache is %s\n",
319 l2cache_status() ? "ON" : "OFF");
331 l2cache
, 2, 1, do_l2cache
,
332 "enable or disable L2 cache",
334 " - enable or disable L2 cache"