board/amcc/ocotea/ocotea.c

   1 /*
   2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
   3  *
   4  * (C) Copyright 2005
   5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #include <common.h>
  28 #include "ocotea.h"
  29 #include <asm/processor.h>
  30 #include <spd_sdram.h>
  31 #include <ppc4xx_enet.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  36 #define FLASH_ONBD_N            2       /* 00000010 */
  37 #define FLASH_SRAM_SEL          1       /* 00000001 */
  38
  39 long int fixed_sdram (void);
  40 void fpga_init (void);
  41
  42 int board_early_init_f (void)
  43 {
  44         unsigned long mfr;
  45         unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
  46         unsigned char switch_status;
  47         unsigned long cs0_base;
  48         unsigned long cs0_size;
  49         unsigned long cs0_twt;
  50         unsigned long cs2_base;
  51         unsigned long cs2_size;
  52         unsigned long cs2_twt;
  53
  54         /*-------------------------------------------------------------------------+
  55           | Initialize EBC CONFIG
  56           +-------------------------------------------------------------------------*/
  57         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  58               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  59               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  60               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  61               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  62
  63         /*-------------------------------------------------------------------------+
  64           | FPGA. Initialize bank 7 with default values.
  65           +-------------------------------------------------------------------------*/
  66         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  67               EBC_BXAP_BCE_DISABLE|
  68               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  69               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  70               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  71               EBC_BXAP_BEM_WRITEONLY|
  72               EBC_BXAP_PEN_DISABLED);
  73         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
  74               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  75
  76         /* read FPGA base register FPGA_REG0 */
  77         switch_status = *fpga_base;
  78
  79         if (switch_status & 0x40) {
  80                 cs0_base = 0xFFE00000;
  81                 cs0_size = EBC_BXCR_BS_2MB;
  82                 cs0_twt = 8;
  83                 cs2_base = 0xFF800000;
  84                 cs2_size = EBC_BXCR_BS_4MB;
  85                 cs2_twt = 10;
  86         } else {
  87                 cs0_base = 0xFFC00000;
  88                 cs0_size = EBC_BXCR_BS_4MB;
  89                 cs0_twt = 10;
  90                 cs2_base = 0xFF800000;
  91                 cs2_size = EBC_BXCR_BS_2MB;
  92                 cs2_twt = 8;
  93         }
  94
  95         /*-------------------------------------------------------------------------+
  96           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
  97           +-------------------------------------------------------------------------*/
  98         mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
  99               EBC_BXAP_BCE_DISABLE|
 100               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 101               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 102               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 103               EBC_BXAP_BEM_WRITEONLY|
 104               EBC_BXAP_PEN_DISABLED);
 105         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
 106               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 107
 108         /*-------------------------------------------------------------------------+
 109           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 110           +-------------------------------------------------------------------------*/
 111         mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
 112               EBC_BXAP_BCE_DISABLE|
 113               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 114               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 115               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 116               EBC_BXAP_BEM_WRITEONLY|
 117               EBC_BXAP_PEN_DISABLED);
 118         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
 119               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 120
 121         /*-------------------------------------------------------------------------+
 122           | 4 MB FLASH. Initialize bank 2 with default values.
 123           +-------------------------------------------------------------------------*/
 124         mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 125               EBC_BXAP_BCE_DISABLE|
 126               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 127               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 128               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 129               EBC_BXAP_BEM_WRITEONLY|
 130               EBC_BXAP_PEN_DISABLED);
 131         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
 132               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 133
 134         /*-------------------------------------------------------------------------+
 135           | FPGA. Initialize bank 7 with default values.
 136           +-------------------------------------------------------------------------*/
 137         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 138               EBC_BXAP_BCE_DISABLE|
 139               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 140               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 141               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 142               EBC_BXAP_BEM_WRITEONLY|
 143               EBC_BXAP_PEN_DISABLED);
 144         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
 145               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 146
 147         /*--------------------------------------------------------------------
 148          * Setup the interrupt controller polarities, triggers, etc.
 149          *-------------------------------------------------------------------*/
 150         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 151         mtdcr (uic0er, 0x00000000);     /* disable all */
 152         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
 153         mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
 154         mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
 155         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
 156         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 157
 158         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 159         mtdcr (uic1er, 0x00000000);     /* disable all */
 160         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
 161         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
 162         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
 163         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 164         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 165
 166         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 167         mtdcr (uic2er, 0x00000000);     /* disable all */
 168         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 169         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
 170         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
 171         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 172         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 173
 174         mtdcr (uicb0sr, 0xfc000000); /* clear all */
 175         mtdcr (uicb0er, 0x00000000); /* disable all */
 176         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
 177         mtdcr (uicb0pr, 0xfc000000); /* */
 178         mtdcr (uicb0tr, 0x00000000); /* */
 179         mtdcr (uicb0vr, 0x00000001); /* */
 180         mfsdr (sdr_mfr, mfr);
 181         mfr &= ~SDR0_MFR_ECS_MASK;
 182 /*      mtsdr(sdr_mfr, mfr); */
 183         fpga_init();
 184
 185         return 0;
 186 }
 187
 188
 189 int checkboard (void)
 190 {
 191         char *s = getenv ("serial#");
 192
 193         printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
 194         if (s != NULL) {
 195                 puts (", serial# ");
 196                 puts (s);
 197         }
 198         putc ('\n');
 199
 200         return (0);
 201 }
 202
 203
 204 long int initdram (int board_type)
 205 {
 206         long dram_size = 0;
 207
 208 #if defined(CONFIG_SPD_EEPROM)
 209         dram_size = spd_sdram ();
 210 #else
 211         dram_size = fixed_sdram ();
 212 #endif
 213         return dram_size;
 214 }
 215
 216
 217 #if defined(CFG_DRAM_TEST)
 218 int testdram (void)
 219 {
 220         uint *pstart = (uint *) 0x00000000;
 221         uint *pend = (uint *) 0x08000000;
 222         uint *p;
 223
 224         for (p = pstart; p < pend; p++)
 225                 *p = 0xaaaaaaaa;
 226
 227         for (p = pstart; p < pend; p++) {
 228                 if (*p != 0xaaaaaaaa) {
 229                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 230                         return 1;
 231                 }
 232         }
 233
 234         for (p = pstart; p < pend; p++)
 235                 *p = 0x55555555;
 236
 237         for (p = pstart; p < pend; p++) {
 238                 if (*p != 0x55555555) {
 239                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 240                         return 1;
 241                 }
 242         }
 243         return 0;
 244 }
 245 #endif
 246
 247 #if !defined(CONFIG_SPD_EEPROM)
 248 /*************************************************************************
 249  *  fixed sdram init -- doesn't use serial presence detect.
 250  *
 251  *  Assumes:    128 MB, non-ECC, non-registered
 252  *              PLB @ 133 MHz
 253  *
 254  ************************************************************************/
 255 long int fixed_sdram (void)
 256 {
 257         uint reg;
 258
 259         /*--------------------------------------------------------------------
 260          * Setup some default
 261          *------------------------------------------------------------------*/
 262         mtsdram (mem_uabba, 0x00000000);        /* ubba=0 (default)             */
 263         mtsdram (mem_slio, 0x00000000);         /* rdre=0 wrre=0 rarw=0         */
 264         mtsdram (mem_devopt, 0x00000000);       /* dll=0 ds=0 (normal)          */
 265         mtsdram (mem_wddctr, 0x00000000);       /* wrcp=0 dcd=0                 */
 266         mtsdram (mem_clktr, 0x40000000);        /* clkp=1 (90 deg wr) dcdt=0    */
 267
 268         /*--------------------------------------------------------------------
 269          * Setup for board-specific specific mem
 270          *------------------------------------------------------------------*/
 271         /*
 272          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 273          */
 274         mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
 275         mtsdram (mem_tr0, 0x410a4012);  /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 276         /* RA=10 RD=3                       */
 277         mtsdram (mem_tr1, 0x8080082f);  /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 278         mtsdram (mem_rtr, 0x08200000);  /* Rate 15.625 ns @ 133 MHz PLB     */
 279         mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
 280         udelay (400);                   /* Delay 200 usecs (min)            */
 281
 282         /*--------------------------------------------------------------------
 283          * Enable the controller, then wait for DCEN to complete
 284          *------------------------------------------------------------------*/
 285         mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit           */
 286         for (;;) {
 287                 mfsdram (mem_mcsts, reg);
 288                 if (reg & 0x80000000)
 289                         break;
 290         }
 291
 292         return (128 * 1024 * 1024);     /* 128 MB                           */
 293 }
 294 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 295
 296
 297 /*************************************************************************
 298  *  pci_pre_init
 299  *
 300  *  This routine is called just prior to registering the hose and gives
 301  *  the board the opportunity to check things. Returning a value of zero
 302  *  indicates that things are bad & PCI initialization should be aborted.
 303  *
 304  *      Different boards may wish to customize the pci controller structure
 305  *      (add regions, override default access routines, etc) or perform
 306  *      certain pre-initialization actions.
 307  *
 308  ************************************************************************/
 309 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 310 int pci_pre_init(struct pci_controller * hose )
 311 {
 312         unsigned long strap;
 313
 314         /*--------------------------------------------------------------------------+
 315          *      The ocotea board is always configured as the host & requires the
 316          *      PCI arbiter to be enabled.
 317          *--------------------------------------------------------------------------*/
 318         mfsdr(sdr_sdstp1, strap);
 319         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
 320                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 321                 return 0;
 322         }
 323
 324         return 1;
 325 }
 326 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 327
 328 /*************************************************************************
 329  *  pci_target_init
 330  *
 331  *      The bootstrap configuration provides default settings for the pci
 332  *      inbound map (PIM). But the bootstrap config choices are limited and
 333  *      may not be sufficient for a given board.
 334  *
 335  ************************************************************************/
 336 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 337 void pci_target_init(struct pci_controller * hose )
 338 {
 339         /*--------------------------------------------------------------------------+
 340          * Disable everything
 341          *--------------------------------------------------------------------------*/
 342         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 343         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 344         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 345         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 346
 347         /*--------------------------------------------------------------------------+
 348          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 349          * options to not support sizes such as 128/256 MB.
 350          *--------------------------------------------------------------------------*/
 351         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 352         out32r( PCIX0_PIM0LAH, 0 );
 353         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 354
 355         out32r( PCIX0_BAR0, 0 );
 356
 357         /*--------------------------------------------------------------------------+
 358          * Program the board's subsystem id/vendor id
 359          *--------------------------------------------------------------------------*/
 360         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 361         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 362
 363         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 364 }
 365 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 366
 367
 368 /*************************************************************************
 369  *  is_pci_host
 370  *
 371  *      This routine is called to determine if a pci scan should be
 372  *      performed. With various hardware environments (especially cPCI and
 373  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 374  *      bit in the strap register, or generic host/adapter assumptions.
 375  *
 376  *      Rather than hard-code a bad assumption in the general 440 code, the
 377  *      440 pci code requires the board to decide at runtime.
 378  *
 379  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 380  *
 381  *
 382  ************************************************************************/
 383 #if defined(CONFIG_PCI)
 384 int is_pci_host(struct pci_controller *hose)
 385 {
 386     /* The ocotea board is always configured as host. */
 387     return(1);
 388 }
 389 #endif /* defined(CONFIG_PCI) */
 390
 391
 392 void fpga_init(void)
 393 {
 394         unsigned long group;
 395         unsigned long sdr0_pfc0;
 396         unsigned long sdr0_pfc1;
 397         unsigned long sdr0_cust0;
 398         unsigned long pvr;
 399
 400         mfsdr (sdr_pfc0, sdr0_pfc0);
 401         mfsdr (sdr_pfc1, sdr0_pfc1);
 402         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
 403         pvr = get_pvr ();
 404
 405         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
 406         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
 407                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
 408                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 409                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 410                      FPGA_REG2_EXT_INTFACE_ENABLE);
 411                 mtsdr (sdr_pfc0, sdr0_pfc0);
 412                 mtsdr (sdr_pfc1, sdr0_pfc1);
 413         } else {
 414                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
 415                 switch (group)
 416                 {
 417                 case 0:
 418                 case 1:
 419                 case 2:
 420                         /* CPU trace A */
 421                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 422                              FPGA_REG2_EXT_INTFACE_ENABLE);
 423                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 424                         mtsdr (sdr_pfc0, sdr0_pfc0);
 425                         mtsdr (sdr_pfc1, sdr0_pfc1);
 426                         break;
 427                 case 3:
 428                 case 4:
 429                 case 5:
 430                 case 6:
 431                         /* CPU trace B - Over EBMI */
 432                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
 433                         mtsdr (sdr_pfc0, sdr0_pfc0);
 434                         mtsdr (sdr_pfc1, sdr0_pfc1);
 435                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 436                              FPGA_REG2_EXT_INTFACE_DISABLE);
 437                         break;
 438                 }
 439         }
 440
 441         /* Initialize the ethernet specific functions in the fpga */
 442         mfsdr(sdr_pfc1, sdr0_pfc1);
 443         mfsdr(sdr_cust0, sdr0_cust0);
 444         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
 445             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
 446              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
 447         {
 448                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 449                 {
 450                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 451                              FPGA_REG3_ENET_GROUP7);
 452                 }
 453                 else
 454                 {
 455                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
 456                         {
 457                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 458                                      FPGA_REG3_ENET_GROUP7);
 459                         }
 460                         else
 461                         {
 462                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 463                                      FPGA_REG3_ENET_GROUP8);
 464                         }
 465                 }
 466         }
 467         else
 468         {
 469                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 470                 {
 471                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 472                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 473                 }
 474                 else
 475                 {
 476                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 477                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 478                 }
 479         }
 480         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
 481              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
 482              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
 483
 484         /* reset the gigabyte phy if necessary */
 485         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
 486         {
 487                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 488                 {
 489                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
 490                         udelay(10000);
 491                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
 492                 }
 493                 else
 494                 {
 495                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
 496                         udelay(10000);
 497                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
 498                 }
 499         }
 500
 501         /*
 502          * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
 503          */
 504         if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
 505                 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
 506                 udelay(10000);
 507                 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
 508         }
 509
 510         /* Turn off the LED's */
 511         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
 512              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
 513              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
 514
 515         return;
 516 }
 517
 518 #ifdef CONFIG_POST
 519 /*
 520  * Returns 1 if keys pressed to start the power-on long-running tests
 521  * Called from board_init_f().
 522  */
 523 int post_hotkeys_pressed(void)
 524 {
 525
 526         return (ctrlc());
 527 }
 528 #endif