board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <libfdt.h>
  27 #include <fdt_support.h>
  28 #include <asm/ppc4xx.h>
  29 #include <asm/ppc4xx-gpio.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <asm/bitops.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #if !defined(CONFIG_SYS_NO_FLASH)
  37 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  38 #endif
  39
  40 extern void __ft_board_setup(void *blob, bd_t *bd);
  41 ulong flash_get_size(ulong base, int banknum);
  42
  43 static inline u32 get_async_pci_freq(void)
  44 {
  45         if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
  46                 CONFIG_SYS_BCSR5_PCI66EN)
  47                 return 66666666;
  48         else
  49                 return 33333333;
  50 }
  51
  52 int board_early_init_f(void)
  53 {
  54         u32 sdr0_cust0;
  55         u32 sdr0_pfc1, sdr0_pfc2;
  56         u32 reg;
  57
  58         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  59         mtdcr(EBC0_CFGDATA, 0xb8400000);
  60
  61         /*
  62          * Setup the interrupt controller polarities, triggers, etc.
  63          */
  64         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  65         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  66         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  67         mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
  68         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  69         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  70         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  71
  72         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  73         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  74         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  75         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
  76         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  77         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  78         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  79
  80         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  81         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  82         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  83         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  84         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  85         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  86         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  87
  88         /* Check and reconfigure the PCI sync clock if necessary */
  89         ppc4xx_pci_sync_clock_config(get_async_pci_freq());
  90
  91         /* 50MHz tmrclk */
  92         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
  93
  94         /* clear write protects */
  95         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
  96
  97         /* enable Ethernet */
  98         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
  99
 100         /* enable USB device */
 101         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
 102
 103         /* select Ethernet (and optionally IIC1) pins */
 104         mfsdr(SDR0_PFC1, sdr0_pfc1);
 105         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 106                 SDR0_PFC1_SELECT_CONFIG_4;
 107 #ifdef CONFIG_I2C_MULTI_BUS
 108         sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
 109 #endif
 110         /* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
 111         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
 112         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
 113         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
 114
 115         mfsdr(SDR0_PFC2, sdr0_pfc2);
 116         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 117                 SDR0_PFC2_SELECT_CONFIG_4;
 118         mtsdr(SDR0_PFC2, sdr0_pfc2);
 119         mtsdr(SDR0_PFC1, sdr0_pfc1);
 120
 121         /* PCI arbiter enabled */
 122         mfsdr(SDR0_PCI0, reg);
 123         mtsdr(SDR0_PCI0, 0x80000000 | reg);
 124
 125         /* setup NAND FLASH */
 126         mfsdr(SDR0_CUST0, sdr0_cust0);
 127         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 128                 SDR0_CUST0_NDFC_ENABLE          |
 129                 SDR0_CUST0_NDFC_BW_8_BIT        |
 130                 SDR0_CUST0_NDFC_ARE_MASK        |
 131                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 132         mtsdr(SDR0_CUST0, sdr0_cust0);
 133
 134         return 0;
 135 }
 136
 137 int misc_init_r(void)
 138 {
 139 #if !defined(CONFIG_SYS_NO_FLASH)
 140         uint pbcr;
 141         int size_val = 0;
 142 #endif
 143 #ifdef CONFIG_440EPX
 144         unsigned long usb2d0cr = 0;
 145         unsigned long usb2phy0cr, usb2h0cr = 0;
 146         unsigned long sdr0_pfc1;
 147         char *act = getenv("usbact");
 148 #endif
 149         u32 reg;
 150
 151 #if !defined(CONFIG_SYS_NO_FLASH)
 152         /* Re-do flash sizing to get full correct info */
 153
 154         /* adjust flash start and offset */
 155         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 156         gd->bd->bi_flashoffset = 0;
 157
 158 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
 159     defined(CONFIG_SYS_RAMBOOT)
 160         mtdcr(EBC0_CFGADDR, PB3CR);
 161 #else
 162         mtdcr(EBC0_CFGADDR, PB0CR);
 163 #endif
 164         pbcr = mfdcr(EBC0_CFGDATA);
 165         size_val = ffs(gd->bd->bi_flashsize) - 21;
 166         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 167 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
 168     defined(CONFIG_SYS_RAMBOOT)
 169         mtdcr(EBC0_CFGADDR, PB3CR);
 170 #else
 171         mtdcr(EBC0_CFGADDR, PB0CR);
 172 #endif
 173         mtdcr(EBC0_CFGDATA, pbcr);
 174
 175         /*
 176          * Re-check to get correct base address
 177          */
 178         flash_get_size(gd->bd->bi_flashstart, 0);
 179
 180 #ifdef CONFIG_ENV_IS_IN_FLASH
 181         /* Monitor protection ON by default */
 182         (void)flash_protect(FLAG_PROTECT_SET,
 183                             -CONFIG_SYS_MONITOR_LEN,
 184                             0xffffffff,
 185                             &flash_info[0]);
 186
 187         /* Env protection ON by default */
 188         (void)flash_protect(FLAG_PROTECT_SET,
 189                             CONFIG_ENV_ADDR_REDUND,
 190                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 191                             &flash_info[0]);
 192 #endif
 193 #endif /* CONFIG_SYS_NO_FLASH */
 194
 195         /*
 196          * USB suff...
 197          */
 198 #ifdef CONFIG_440EPX
 199         if (act == NULL || strcmp(act, "hostdev") == 0) {
 200                 /* SDR Setting */
 201                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 202                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 203                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 204                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 205
 206                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 207                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 208                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 209                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 210                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 211                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 212                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 213                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 214                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 215                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 216
 217                 /*
 218                  * An 8-bit/60MHz interface is the only possible alternative
 219                  * when connecting the Device to the PHY
 220                  */
 221                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 222                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 223
 224                 /*
 225                  * To enable the USB 2.0 Device function
 226                  * through the UTMI interface
 227                  */
 228                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 229                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
 230
 231                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 232                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
 233
 234                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 235                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 236                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 237                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 238
 239                 /*clear resets*/
 240                 udelay (1000);
 241                 mtsdr(SDR0_SRST1, 0x00000000);
 242                 udelay (1000);
 243                 mtsdr(SDR0_SRST0, 0x00000000);
 244
 245                 printf("USB:   Host(int phy) Device(ext phy)\n");
 246
 247         } else if (strcmp(act, "dev") == 0) {
 248                 /*-------------------PATCH-------------------------------*/
 249                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 250
 251                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 252                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 253                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 254                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 255                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 256                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 257                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 258                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 259                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 260
 261                 udelay (1000);
 262                 mtsdr(SDR0_SRST1, 0x672c6000);
 263
 264                 udelay (1000);
 265                 mtsdr(SDR0_SRST0, 0x00000080);
 266
 267                 udelay (1000);
 268                 mtsdr(SDR0_SRST1, 0x60206000);
 269
 270                 *(unsigned int *)(0xe0000350) = 0x00000001;
 271
 272                 udelay (1000);
 273                 mtsdr(SDR0_SRST1, 0x60306000);
 274                 /*-------------------PATCH-------------------------------*/
 275
 276                 /* SDR Setting */
 277                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 278                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 279                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 280                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 281
 282                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 283                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 284                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 285                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 286                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 287                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 288                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 289                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 290                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 291                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 292
 293                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 294                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 295
 296                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 297                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
 298
 299                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 300                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 301
 302                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 303                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 304                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 305                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 306
 307                 /* clear resets */
 308                 udelay (1000);
 309                 mtsdr(SDR0_SRST1, 0x00000000);
 310                 udelay (1000);
 311                 mtsdr(SDR0_SRST0, 0x00000000);
 312
 313                 printf("USB:   Device(int phy)\n");
 314         }
 315 #endif /* CONFIG_440EPX */
 316
 317         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 318         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 319         mtsdr(SDR0_SRST1, reg);
 320
 321         /*
 322          * Clear PLB4A0_ACR[WRP]
 323          * This fix will make the MAL burst disabling patch for the Linux
 324          * EMAC driver obsolete.
 325          */
 326         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 327         mtdcr(PLB4A0_ACR, reg);
 328
 329         return 0;
 330 }
 331
 332 int checkboard(void)
 333 {
 334         char *s = getenv("serial#");
 335         u8 rev;
 336         u32 clock = get_async_pci_freq();
 337
 338 #ifdef CONFIG_440EPX
 339         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 340 #else
 341         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 342 #endif
 343
 344         rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
 345         printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 346
 347         if (s != NULL) {
 348                 puts(", serial# ");
 349                 puts(s);
 350         }
 351         putc('\n');
 352
 353         /*
 354          * Reconfiguration of the PCI sync clock is already done,
 355          * now check again if everything is in range:
 356          */
 357         if (ppc4xx_pci_sync_clock_config(clock)) {
 358                 printf("ERROR: PCI clocking incorrect (async=%d "
 359                        "sync=%ld)!\n", clock, get_PCI_freq());
 360         }
 361
 362         return (0);
 363 }
 364
 365 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 366 /*
 367  * Assign interrupts to PCI devices.
 368  */
 369 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 370 {
 371         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 372 }
 373 #endif
 374
 375 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 376 /*
 377  * On NAND-booting sequoia, we need to patch the chips select numbers
 378  * in the dtb (CS0 - NAND, CS3 - NOR)
 379  */
 380 void ft_board_setup(void *blob, bd_t *bd)
 381 {
 382         int rc;
 383         int len;
 384         int nodeoffset;
 385         struct fdt_property *prop;
 386         u32 *reg;
 387         char path[32];
 388
 389         /* First do common fdt setup */
 390         __ft_board_setup(blob, bd);
 391
 392         /* And now configure NOR chip select to 3 instead of 0 */
 393         strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
 394         nodeoffset = fdt_path_offset(blob, path);
 395         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 396         if (prop == NULL) {
 397                 printf("Unable to update NOR chip select for NAND booting\n");
 398                 return;
 399         }
 400         reg = (u32 *)&prop->data[0];
 401         reg[0] = 3;
 402         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 403         if (rc) {
 404                 printf("Unable to update property NOR mappings, err=%s\n",
 405                        fdt_strerror(rc));
 406                 return;
 407         }
 408
 409         /* And now configure NAND chip select to 0 instead of 3 */
 410         strcpy(path, "/plb/opb/ebc/ndfc@3,0");
 411         nodeoffset = fdt_path_offset(blob, path);
 412         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 413         if (prop == NULL) {
 414                 printf("Unable to update NDFC chip select for NAND booting\n");
 415                 return;
 416         }
 417         reg = (u32 *)&prop->data[0];
 418         reg[0] = 0;
 419         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 420         if (rc) {
 421                 printf("Unable to update property NDFC mappings, err=%s\n",
 422                        fdt_strerror(rc));
 423                 return;
 424         }
 425 }
 426 #endif /* CONFIG_NAND_U_BOOT */