2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <spd_sdram.h>
29 #include <asm/ppc4xx-emac.h>
32 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
33 void show_reset_reg(void);
36 DECLARE_GLOBAL_DATA_PTR
;
40 int board_early_init_f (void)
43 volatile unsigned int *GpioOdr
;
44 volatile unsigned int *GpioTcr
;
45 volatile unsigned int *GpioOr
;
47 /*-------------------------------------------------------------------------+
48 | Initialize EBC CONFIG
49 +-------------------------------------------------------------------------*/
50 mtebc(EBC0_CFG
, EBC_CFG_LE_UNLOCK
|
51 EBC_CFG_PTD_ENABLE
| EBC_CFG_RTC_64PERCLK
|
52 EBC_CFG_ATC_PREVIOUS
| EBC_CFG_DTC_PREVIOUS
|
53 EBC_CFG_CTC_PREVIOUS
| EBC_CFG_EMC_DEFAULT
|
54 EBC_CFG_PME_DISABLE
| EBC_CFG_PR_32
);
56 /*-------------------------------------------------------------------------+
57 | 64MB FLASH. Initialize bank 0 with default values.
58 +-------------------------------------------------------------------------*/
59 mtebc(PB0AP
, EBC_BXAP_BME_DISABLED
|EBC_BXAP_TWT_ENCODE(15) |
60 EBC_BXAP_BCE_DISABLE
|
61 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
62 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
63 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED
|
64 EBC_BXAP_BEM_WRITEONLY
|
65 EBC_BXAP_PEN_DISABLED
);
66 mtebc(PB0CR
, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE
) |
67 EBC_BXCR_BS_64MB
| EBC_BXCR_BU_RW
|EBC_BXCR_BW_32BIT
);
69 /*-------------------------------------------------------------------------+
70 | FPGA. Initialize bank 1 with default values.
71 +-------------------------------------------------------------------------*/
72 mtebc(PB1AP
, EBC_BXAP_BME_DISABLED
|EBC_BXAP_TWT_ENCODE(5) |
73 EBC_BXAP_BCE_DISABLE
|
74 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
75 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
76 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED
|
77 EBC_BXAP_BEM_WRITEONLY
|
78 EBC_BXAP_PEN_DISABLED
);
79 mtebc(PB1CR
, EBC_BXCR_BAS_ENCODE(0x41000000) |
80 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_8BIT
);
82 /*-------------------------------------------------------------------------+
83 | LCM. Initialize bank 2 with default values.
84 +-------------------------------------------------------------------------*/
85 mtebc(PB2AP
, EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(64) |
86 EBC_BXAP_BCE_DISABLE
|
87 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
88 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
89 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED
|
90 EBC_BXAP_BEM_WRITEONLY
|
91 EBC_BXAP_PEN_DISABLED
);
92 mtebc(PB2CR
, EBC_BXCR_BAS_ENCODE(0x42000000) |
93 EBC_BXCR_BS_1MB
| EBC_BXCR_BU_RW
|EBC_BXCR_BW_8BIT
);
95 /*-------------------------------------------------------------------------+
96 | TMP. Initialize bank 3 with default values.
97 +-------------------------------------------------------------------------*/
98 mtebc(PB3AP
, EBC_BXAP_BME_DISABLED
| EBC_BXAP_TWT_ENCODE(128) |
99 EBC_BXAP_BCE_DISABLE
|
100 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
101 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
102 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED
|
103 EBC_BXAP_BEM_WRITEONLY
|
104 EBC_BXAP_PEN_DISABLED
);
105 mtebc(PB3CR
, EBC_BXCR_BAS_ENCODE(0x48000000) |
106 EBC_BXCR_BS_64MB
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_32BIT
);
108 /*-------------------------------------------------------------------------+
109 | Connector 4~7. Initialize bank 3~ 7 with default values.
110 +-------------------------------------------------------------------------*/
120 /*--------------------------------------------------------------------
121 * Setup the interrupt controller polarities, triggers, etc.
122 *-------------------------------------------------------------------*/
124 * Because of the interrupt handling rework to handle 440GX interrupts
125 * with the common code, we needed to change names of the UIC registers.
126 * Here the new relationship:
128 * U-Boot name 440GX name
129 * -----------------------
135 mtdcr (UIC1SR
, 0xffffffff); /* clear all */
136 mtdcr (UIC1ER
, 0x00000000); /* disable all */
137 mtdcr (UIC1CR
, 0x00000009); /* SMI & UIC1 crit are critical */
138 mtdcr (UIC1PR
, 0xfffffe13); /* per ref-board manual */
139 mtdcr (UIC1TR
, 0x01c00008); /* per ref-board manual */
140 mtdcr (UIC1VR
, 0x00000001); /* int31 highest, base=0x000 */
141 mtdcr (UIC1SR
, 0xffffffff); /* clear all */
143 mtdcr (UIC2SR
, 0xffffffff); /* clear all */
144 mtdcr (UIC2ER
, 0x00000000); /* disable all */
145 mtdcr (UIC2CR
, 0x00000000); /* all non-critical */
146 mtdcr (UIC2PR
, 0xffffe0ff); /* per ref-board manual */
147 mtdcr (UIC2TR
, 0x00ffc000); /* per ref-board manual */
148 mtdcr (UIC2VR
, 0x00000001); /* int31 highest, base=0x000 */
149 mtdcr (UIC2SR
, 0xffffffff); /* clear all */
151 mtdcr (UIC3SR
, 0xffffffff); /* clear all */
152 mtdcr (UIC3ER
, 0x00000000); /* disable all */
153 mtdcr (UIC3CR
, 0x00000000); /* all non-critical */
154 mtdcr (UIC3PR
, 0xffffffff); /* per ref-board manual */
155 mtdcr (UIC3TR
, 0x00ff8c0f); /* per ref-board manual */
156 mtdcr (UIC3VR
, 0x00000001); /* int31 highest, base=0x000 */
157 mtdcr (UIC3SR
, 0xffffffff); /* clear all */
159 mtdcr (UIC0SR
, 0xfc000000); /* clear all */
160 mtdcr (UIC0ER
, 0x00000000); /* disable all */
161 mtdcr (UIC0CR
, 0x00000000); /* all non-critical */
162 mtdcr (UIC0PR
, 0xfc000000); /* */
163 mtdcr (UIC0TR
, 0x00000000); /* */
164 mtdcr (UIC0VR
, 0x00000001); /* */
166 /* Enable two GPIO 10~11 and TraceA signal */
167 mfsdr(SDR0_PFC0
,reg
);
169 mtsdr(SDR0_PFC0
,reg
);
171 mfsdr(SDR0_PFC1
,reg
);
173 mtsdr(SDR0_PFC1
,reg
);
175 /* Set GPIO 10 and 11 as output */
176 GpioOdr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x718);
177 GpioTcr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x704);
178 GpioOr
= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE
+0x700);
180 *GpioOdr
&= ~(0x00300000);
181 *GpioTcr
|= 0x00300000;
182 *GpioOr
|= 0x00300000;
187 int misc_init_r(void)
194 int checkboard (void)
196 char *s
= getenv ("serial#");
198 printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
205 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
212 int board_eth_init(bd_t
*bis
)
215 return pci_eth_init(bis
);