board/amcc/yellowstone/yellowstone.c

   1 /*
   2  *
   3  * See file CREDITS for list of people who contributed to this
   4  * project.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <ppc4xx.h>
  24 #include <asm/processor.h>
  25 #include <spd_sdram.h>
  26
  27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  28
  29 int board_early_init_f(void)
  30 {
  31         register uint reg;
  32
  33         /*--------------------------------------------------------------------
  34          * Setup the external bus controller/chip selects
  35          *-------------------------------------------------------------------*/
  36         mtdcr(ebccfga, xbcfg);
  37         reg = mfdcr(ebccfgd);
  38         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  39
  40         mtebc(pb0ap, 0x03017300);       /* FLASH/SRAM */
  41         mtebc(pb0cr, 0xfc0da000);       /* BAS=0xfc0 64MB r/w 16-bit */
  42
  43         mtebc(pb1ap, 0x00000000);
  44         mtebc(pb1cr, 0x00000000);
  45
  46         mtebc(pb2ap, 0x04814500);
  47         /*CPLD*/ mtebc(pb2cr, 0x80018000);      /*BAS=0x800 1MB r/w 8-bit */
  48
  49         mtebc(pb3ap, 0x00000000);
  50         mtebc(pb3cr, 0x00000000);
  51
  52         mtebc(pb4ap, 0x00000000);
  53         mtebc(pb4cr, 0x00000000);
  54
  55         mtebc(pb5ap, 0x00000000);
  56         mtebc(pb5cr, 0x00000000);
  57
  58         /*--------------------------------------------------------------------
  59          * Setup the GPIO pins
  60          *-------------------------------------------------------------------*/
  61         /*CPLD cs */
  62         /*setup Address lines for flash sizes larger than 16Meg. */
  63         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
  64         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
  65         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  66
  67         /*setup emac */
  68         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  69         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  70         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  71         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  72         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  73
  74         /*UART1 */
  75         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  76         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  77         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  78
  79         /* external interrupts IRQ0...3 */
  80         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
  81         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
  82         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  83
  84 #if 0 /* test-only */
  85         /*setup USB 2.0 */
  86         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  87         out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  88         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  89         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  90         out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  91 #endif
  92
  93         /*--------------------------------------------------------------------
  94          * Setup the interrupt controller polarities, triggers, etc.
  95          *-------------------------------------------------------------------*/
  96         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  97         mtdcr(uic0er, 0x00000000);      /* disable all */
  98         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
  99         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 100         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 101         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 102         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 103
 104         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 105         mtdcr(uic1er, 0x00000000);      /* disable all */
 106         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 107         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 108         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 109         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 110         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 111
 112         /*--------------------------------------------------------------------
 113          * Setup other serial configuration
 114          *-------------------------------------------------------------------*/
 115         mfsdr(sdr_pci0, reg);
 116         mtsdr(sdr_pci0, 0x80000000 | reg);      /* PCI arbiter enabled */
 117         mtsdr(sdr_pfc0, 0x00003e00);    /* Pin function */
 118         mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 119
 120         /*clear tmrclk divisor */
 121         *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
 122
 123         /*enable ethernet */
 124         *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 125
 126 #if 0 /* test-only */
 127         /*enable usb 1.1 fs device and remove usb 2.0 reset */
 128         *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
 129 #endif
 130
 131         /*get rid of flash write protect */
 132         *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
 133
 134         return 0;
 135 }
 136
 137 int misc_init_r (void)
 138 {
 139         DECLARE_GLOBAL_DATA_PTR;
 140         uint pbcr;
 141         int size_val = 0;
 142
 143         /* Re-do sizing to get full correct info */
 144         mtdcr(ebccfga, pb0cr);
 145         pbcr = mfdcr(ebccfgd);
 146         switch (gd->bd->bi_flashsize) {
 147         case 1 << 20:
 148                 size_val = 0;
 149                 break;
 150         case 2 << 20:
 151                 size_val = 1;
 152                 break;
 153         case 4 << 20:
 154                 size_val = 2;
 155                 break;
 156         case 8 << 20:
 157                 size_val = 3;
 158                 break;
 159         case 16 << 20:
 160                 size_val = 4;
 161                 break;
 162         case 32 << 20:
 163                 size_val = 5;
 164                 break;
 165         case 64 << 20:
 166                 size_val = 6;
 167                 break;
 168         case 128 << 20:
 169                 size_val = 7;
 170                 break;
 171         }
 172         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 173         mtdcr(ebccfga, pb0cr);
 174         mtdcr(ebccfgd, pbcr);
 175
 176         /* adjust flash start and offset */
 177         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 178         gd->bd->bi_flashoffset = 0;
 179
 180         /* Monitor protection ON by default */
 181         (void)flash_protect(FLAG_PROTECT_SET,
 182                             -CFG_MONITOR_LEN,
 183                             0xffffffff,
 184                             &flash_info[0]);
 185
 186         return 0;
 187 }
 188
 189 int checkboard(void)
 190 {
 191         char *s = getenv("serial#");
 192
 193         printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 194         if (s != NULL) {
 195                 puts(", serial# ");
 196                 puts(s);
 197         }
 198         putc('\n');
 199
 200         return (0);
 201 }
 202
 203 /*************************************************************************
 204  *  sdram_init -- doesn't use serial presence detect.
 205  *
 206  *  Assumes:    256 MB, ECC, non-registered
 207  *              PLB @ 133 MHz
 208  *
 209  ************************************************************************/
 210 void sdram_init(void)
 211 {
 212         register uint reg;
 213
 214         /*--------------------------------------------------------------------
 215          * Setup some default
 216          *------------------------------------------------------------------*/
 217         mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
 218         mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
 219         mtsdram(mem_devopt, 0x00000000);        /* dll=0 ds=0 (normal)          */
 220         mtsdram(mem_clktr, 0x40000000); /* ?? */
 221         mtsdram(mem_wddctr, 0x40000000);        /* ?? */
 222
 223         /*clear this first, if the DDR is enabled by a debugger
 224            then you can not make changes. */
 225         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 226
 227         /*--------------------------------------------------------------------
 228          * Setup for board-specific specific mem
 229          *------------------------------------------------------------------*/
 230         /*
 231          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 232          */
 233         mtsdram(mem_b0cr, 0x000a4001);  /* SDBA=0x000 128MB, Mode 3, enabled */
 234         mtsdram(mem_b1cr, 0x080a4001);  /* SDBA=0x080 128MB, Mode 3, enabled */
 235
 236         mtsdram(mem_tr0, 0x410a4012);   /* ?? */
 237         mtsdram(mem_tr1, 0x8080080b);   /* ?? */
 238         mtsdram(mem_rtr, 0x04080000);   /* ?? */
 239         mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM    */
 240         mtsdram(mem_cfg0, 0x34000000);  /* Disable EEC */
 241         udelay(400);            /* Delay 200 usecs (min)            */
 242
 243         /*--------------------------------------------------------------------
 244          * Enable the controller, then wait for DCEN to complete
 245          *------------------------------------------------------------------*/
 246         mtsdram(mem_cfg0, 0x84000000);  /* Enable */
 247
 248         for (;;) {
 249                 mfsdram(mem_mcsts, reg);
 250                 if (reg & 0x80000000)
 251                         break;
 252         }
 253 }
 254
 255 /*************************************************************************
 256  *  long int initdram
 257  *
 258  ************************************************************************/
 259 long int initdram(int board)
 260 {
 261         sdram_init();
 262         return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
 263 }
 264
 265 #if defined(CFG_DRAM_TEST)
 266 int testdram(void)
 267 {
 268         unsigned long *mem = (unsigned long *)0;
 269         const unsigned long kend = (1024 / sizeof(unsigned long));
 270         unsigned long k, n;
 271
 272         mtmsr(0);
 273
 274         for (k = 0; k < CFG_KBYTES_SDRAM;
 275              ++k, mem += (1024 / sizeof(unsigned long))) {
 276                 if ((k & 1023) == 0) {
 277                         printf("%3d MB\r", k / 1024);
 278                 }
 279
 280                 memset(mem, 0xaaaaaaaa, 1024);
 281                 for (n = 0; n < kend; ++n) {
 282                         if (mem[n] != 0xaaaaaaaa) {
 283                                 printf("SDRAM test fails at: %08x\n",
 284                                        (uint) & mem[n]);
 285                                 return 1;
 286                         }
 287                 }
 288
 289                 memset(mem, 0x55555555, 1024);
 290                 for (n = 0; n < kend; ++n) {
 291                         if (mem[n] != 0x55555555) {
 292                                 printf("SDRAM test fails at: %08x\n",
 293                                        (uint) & mem[n]);
 294                                 return 1;
 295                         }
 296                 }
 297         }
 298         printf("SDRAM test passes\n");
 299         return 0;
 300 }
 301 #endif
 302
 303 /*************************************************************************
 304  *  pci_pre_init
 305  *
 306  *  This routine is called just prior to registering the hose and gives
 307  *  the board the opportunity to check things. Returning a value of zero
 308  *  indicates that things are bad & PCI initialization should be aborted.
 309  *
 310  *      Different boards may wish to customize the pci controller structure
 311  *      (add regions, override default access routines, etc) or perform
 312  *      certain pre-initialization actions.
 313  *
 314  ************************************************************************/
 315 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 316 int pci_pre_init(struct pci_controller *hose)
 317 {
 318         unsigned long strap;
 319         unsigned long addr;
 320
 321         /*--------------------------------------------------------------------------+
 322          *      Bamboo is always configured as the host & requires the
 323          *      PCI arbiter to be enabled.
 324          *--------------------------------------------------------------------------*/
 325         mfsdr(sdr_sdstp1, strap);
 326         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 327                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 328                 printf("PCI: Configuration aborted.\n");
 329                 return 0;
 330         }
 331
 332         /*-------------------------------------------------------------------------+
 333           | Set priority for all PLB3 devices to 0.
 334           | Set PLB3 arbiter to fair mode.
 335           +-------------------------------------------------------------------------*/
 336         mfsdr(sdr_amp1, addr);
 337         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 338         addr = mfdcr(plb3_acr);
 339         mtdcr(plb3_acr, addr | 0x80000000);
 340
 341         /*-------------------------------------------------------------------------+
 342           | Set priority for all PLB4 devices to 0.
 343           +-------------------------------------------------------------------------*/
 344         mfsdr(sdr_amp0, addr);
 345         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 346         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 347         mtdcr(plb4_acr, addr);
 348
 349         /*-------------------------------------------------------------------------+
 350           | Set Nebula PLB4 arbiter to fair mode.
 351           +-------------------------------------------------------------------------*/
 352         /* Segment0 */
 353         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 354         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 355         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 356         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 357         mtdcr(plb0_acr, addr);
 358
 359         /* Segment1 */
 360         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 361         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 362         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 363         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 364         mtdcr(plb1_acr, addr);
 365
 366         return 1;
 367 }
 368 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 369
 370 /*************************************************************************
 371  *  pci_target_init
 372  *
 373  *      The bootstrap configuration provides default settings for the pci
 374  *      inbound map (PIM). But the bootstrap config choices are limited and
 375  *      may not be sufficient for a given board.
 376  *
 377  ************************************************************************/
 378 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 379 void pci_target_init(struct pci_controller *hose)
 380 {
 381         /*--------------------------------------------------------------------------+
 382          * Set up Direct MMIO registers
 383          *--------------------------------------------------------------------------*/
 384         /*--------------------------------------------------------------------------+
 385           | PowerPC440 EP PCI Master configuration.
 386           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 387           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 388           |   Use byte reversed out routines to handle endianess.
 389           | Make this region non-prefetchable.
 390           +--------------------------------------------------------------------------*/
 391         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 392         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 393         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 394         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 395         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 396
 397         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 398         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 399         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 400         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 401         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 402
 403         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 404         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 405         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 406         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 407
 408         /*--------------------------------------------------------------------------+
 409          * Set up Configuration registers
 410          *--------------------------------------------------------------------------*/
 411
 412         /* Program the board's subsystem id/vendor id */
 413         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 414                               CFG_PCI_SUBSYS_VENDORID);
 415         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 416
 417         /* Configure command register as bus master */
 418         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 419
 420         /* 240nS PCI clock */
 421         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 422
 423         /* No error reporting */
 424         pci_write_config_word(0, PCI_ERREN, 0);
 425
 426         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 427
 428 }
 429 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 430
 431 /*************************************************************************
 432  *  pci_master_init
 433  *
 434  ************************************************************************/
 435 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 436 void pci_master_init(struct pci_controller *hose)
 437 {
 438         unsigned short temp_short;
 439
 440         /*--------------------------------------------------------------------------+
 441           | Write the PowerPC440 EP PCI Configuration regs.
 442           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 443           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 444           +--------------------------------------------------------------------------*/
 445         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 446         pci_write_config_word(0, PCI_COMMAND,
 447                               temp_short | PCI_COMMAND_MASTER |
 448                               PCI_COMMAND_MEMORY);
 449 }
 450 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 451
 452 /*************************************************************************
 453  *  is_pci_host
 454  *
 455  *      This routine is called to determine if a pci scan should be
 456  *      performed. With various hardware environments (especially cPCI and
 457  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 458  *      bit in the strap register, or generic host/adapter assumptions.
 459  *
 460  *      Rather than hard-code a bad assumption in the general 440 code, the
 461  *      440 pci code requires the board to decide at runtime.
 462  *
 463  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 464  *
 465  *
 466  ************************************************************************/
 467 #if defined(CONFIG_PCI)
 468 int is_pci_host(struct pci_controller *hose)
 469 {
 470         /* Bamboo is always configured as host. */
 471         return (1);
 472 }
 473 #endif                          /* defined(CONFIG_PCI) */
 474
 475 /*************************************************************************
 476  *  hw_watchdog_reset
 477  *
 478  *      This routine is called to reset (keep alive) the watchdog timer
 479  *
 480  ************************************************************************/
 481 #if defined(CONFIG_HW_WATCHDOG)
 482 void hw_watchdog_reset(void)
 483 {
 484
 485 }
 486 #endif