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Remove warnings re CONFIG_EXTRA_ENV_SETTINGS
[people/ms/u-boot.git] / board / amcc / yucca / yucca.c
1 /*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005
24 *
25 * PCIe supporting routines derived from Linux 440SPe PCIe driver.
26 */
27
28 #include <common.h>
29 #include <ppc4xx.h>
30 #include <asm/processor.h>
31 #include <i2c.h>
32 #include <asm-ppc/io.h>
33
34 #include "yucca.h"
35 #include "../cpu/ppc4xx/440spe_pcie.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #undef PCIE_ENDPOINT
40 /* #define PCIE_ENDPOINT 1 */
41
42 void fpga_init (void);
43
44 void get_sys_info(PPC440_SYS_INFO *board_cfg );
45 int compare_to_true(char *str );
46 char *remove_l_w_space(char *in_str );
47 char *remove_t_w_space(char *in_str );
48 int get_console_port(void);
49
50 int ppc440spe_init_pcie_rootport(int port);
51 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
52
53 #define DEBUG_ENV
54 #ifdef DEBUG_ENV
55 #define DEBUGF(fmt,args...) printf(fmt ,##args)
56 #else
57 #define DEBUGF(fmt,args...)
58 #endif
59
60 #define FALSE 0
61 #define TRUE 1
62
63 int board_early_init_f (void)
64 {
65 /*----------------------------------------------------------------------------+
66 | Define Boot devices
67 +----------------------------------------------------------------------------*/
68 #define BOOT_FROM_SMALL_FLASH 0x00
69 #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
70 #define BOOT_FROM_PCI 0x02
71 #define BOOT_DEVICE_UNKNOWN 0x03
72
73 /*----------------------------------------------------------------------------+
74 | EBC Devices Characteristics
75 | Peripheral Bank Access Parameters - EBC_BxAP
76 | Peripheral Bank Configuration Register - EBC_BxCR
77 +----------------------------------------------------------------------------*/
78
79 /*
80 * Small Flash and FRAM
81 * BU Value
82 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
83 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
84 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
85 */
86 #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
87 EBC_BXAP_TWT_ENCODE(7) | \
88 EBC_BXAP_BCE_DISABLE | \
89 EBC_BXAP_BCT_2TRANS | \
90 EBC_BXAP_CSN_ENCODE(0) | \
91 EBC_BXAP_OEN_ENCODE(0) | \
92 EBC_BXAP_WBN_ENCODE(0) | \
93 EBC_BXAP_WBF_ENCODE(0) | \
94 EBC_BXAP_TH_ENCODE(0) | \
95 EBC_BXAP_RE_DISABLED | \
96 EBC_BXAP_SOR_DELAYED | \
97 EBC_BXAP_BEM_WRITEONLY | \
98 EBC_BXAP_PEN_DISABLED
99
100 #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
101 EBC_BXCR_BS_16MB | \
102 EBC_BXCR_BU_RW | \
103 EBC_BXCR_BW_8BIT
104
105 #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
106 EBC_BXCR_BS_16MB | \
107 EBC_BXCR_BU_RW | \
108 EBC_BXCR_BW_8BIT
109
110 /*
111 * Large Flash and SRAM
112 * BU Value
113 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
114 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
115 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
116 */
117 #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
118 EBC_BXAP_TWT_ENCODE(7) | \
119 EBC_BXAP_BCE_DISABLE | \
120 EBC_BXAP_BCT_2TRANS | \
121 EBC_BXAP_CSN_ENCODE(0) | \
122 EBC_BXAP_OEN_ENCODE(0) | \
123 EBC_BXAP_WBN_ENCODE(0) | \
124 EBC_BXAP_WBF_ENCODE(0) | \
125 EBC_BXAP_TH_ENCODE(0) | \
126 EBC_BXAP_RE_DISABLED | \
127 EBC_BXAP_SOR_DELAYED | \
128 EBC_BXAP_BEM_WRITEONLY | \
129 EBC_BXAP_PEN_DISABLED
130
131 #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
132 EBC_BXCR_BS_16MB | \
133 EBC_BXCR_BU_RW | \
134 EBC_BXCR_BW_16BIT
135
136 #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
137 EBC_BXCR_BS_16MB | \
138 EBC_BXCR_BU_RW | \
139 EBC_BXCR_BW_16BIT
140
141 /*
142 * FPGA
143 * BU value :
144 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
145 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
146 */
147 #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
148 EBC_BXAP_TWT_ENCODE(11) | \
149 EBC_BXAP_BCE_DISABLE | \
150 EBC_BXAP_BCT_2TRANS | \
151 EBC_BXAP_CSN_ENCODE(10) | \
152 EBC_BXAP_OEN_ENCODE(1) | \
153 EBC_BXAP_WBN_ENCODE(1) | \
154 EBC_BXAP_WBF_ENCODE(1) | \
155 EBC_BXAP_TH_ENCODE(1) | \
156 EBC_BXAP_RE_DISABLED | \
157 EBC_BXAP_SOR_DELAYED | \
158 EBC_BXAP_BEM_RW | \
159 EBC_BXAP_PEN_DISABLED
160
161 #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
162 EBC_BXCR_BS_1MB | \
163 EBC_BXCR_BU_RW | \
164 EBC_BXCR_BW_16BIT
165
166 unsigned long mfr;
167 /*
168 * Define Variables for EBC initialization depending on BOOTSTRAP option
169 */
170 unsigned long sdr0_pinstp, sdr0_sdstp1 ;
171 unsigned long bootstrap_settings, ebc_data_width, boot_selection;
172 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
173
174 /*-------------------------------------------------------------------+
175 | Initialize EBC CONFIG -
176 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
177 | default value :
178 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
179 |
180 +-------------------------------------------------------------------*/
181 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
182 EBC_CFG_PTD_ENABLE |
183 EBC_CFG_RTC_16PERCLK |
184 EBC_CFG_ATC_PREVIOUS |
185 EBC_CFG_DTC_PREVIOUS |
186 EBC_CFG_CTC_PREVIOUS |
187 EBC_CFG_OEO_PREVIOUS |
188 EBC_CFG_EMC_DEFAULT |
189 EBC_CFG_PME_DISABLE |
190 EBC_CFG_PR_16);
191
192 /*-------------------------------------------------------------------+
193 |
194 | PART 1 : Initialize EBC Bank 1
195 | ==============================
196 | Bank1 is always associated to the EPLD.
197 | It has to be initialized prior to other banks settings computation
198 | since some board registers values may be needed to determine the
199 | boot type
200 |
201 +-------------------------------------------------------------------*/
202 mtebc(pb1ap, EBC_BXAP_FPGA);
203 mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
204
205 /*-------------------------------------------------------------------+
206 |
207 | PART 2 : Determine which boot device was selected
208 | =================================================
209 |
210 | Read Pin Strap Register in PPC440SPe
211 | Result can either be :
212 | - Boot strap = boot from EBC 8bits => Small Flash
213 | - Boot strap = boot from PCI
214 | - Boot strap = IIC
215 | In case of boot from IIC, read Serial Device Strap Register1
216 |
217 | Result can either be :
218 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
219 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
220 | - Boot from PCI
221 |
222 +-------------------------------------------------------------------*/
223 /* Read Pin Strap Register in PPC440SP */
224 mfsdr(SDR0_PINSTP, sdr0_pinstp);
225 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
226
227 switch (bootstrap_settings) {
228 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
229 /*
230 * Strapping Option A
231 * Boot from EBC - 8 bits , Small Flash
232 */
233 computed_boot_device = BOOT_FROM_SMALL_FLASH;
234 break;
235 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
236 /*
237 * Strappping Option B
238 * Boot from PCI
239 */
240 computed_boot_device = BOOT_FROM_PCI;
241 break;
242 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
243 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
244 /*
245 * Strapping Option C or D
246 * Boot Settings in IIC EEprom address 0x50 or 0x54
247 * Read Serial Device Strap Register1 in PPC440SPe
248 */
249 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
250 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
251 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
252
253 switch (boot_selection) {
254 case SDR0_SDSTP1_ERPN_EBC:
255 switch (ebc_data_width) {
256 case SDR0_SDSTP1_EBCW_16_BITS:
257 computed_boot_device =
258 BOOT_FROM_LARGE_FLASH_OR_SRAM;
259 break;
260 case SDR0_SDSTP1_EBCW_8_BITS :
261 computed_boot_device = BOOT_FROM_SMALL_FLASH;
262 break;
263 }
264 break;
265
266 case SDR0_SDSTP1_ERPN_PCI:
267 computed_boot_device = BOOT_FROM_PCI;
268 break;
269 default:
270 /* should not occure */
271 computed_boot_device = BOOT_DEVICE_UNKNOWN;
272 }
273 break;
274 default:
275 /* should not be */
276 computed_boot_device = BOOT_DEVICE_UNKNOWN;
277 break;
278 }
279
280 /*-------------------------------------------------------------------+
281 |
282 | PART 3 : Compute EBC settings depending on selected boot device
283 | ====== ======================================================
284 |
285 | Resulting EBC init will be among following configurations :
286 |
287 | - Boot from EBC 8bits => boot from Small Flash selected
288 | EBC-CS0 = Small Flash
289 | EBC-CS2 = Large Flash and SRAM
290 |
291 | - Boot from EBC 16bits => boot from Large Flash or SRAM
292 | EBC-CS0 = Large Flash or SRAM
293 | EBC-CS2 = Small Flash
294 |
295 | - Boot from PCI
296 | EBC-CS0 = not initialized to avoid address contention
297 | EBC-CS2 = same as boot from Small Flash selected
298 |
299 +-------------------------------------------------------------------*/
300 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
301 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
302
303 switch (computed_boot_device) {
304 /*-------------------------------------------------------------------*/
305 case BOOT_FROM_PCI:
306 /*-------------------------------------------------------------------*/
307 /*
308 * By Default CS2 is affected to LARGE Flash
309 * do not initialize SMALL FLASH to avoid address contention
310 * Large Flash
311 */
312 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
313 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
314 break;
315
316 /*-------------------------------------------------------------------*/
317 case BOOT_FROM_SMALL_FLASH:
318 /*-------------------------------------------------------------------*/
319 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
320 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
321
322 /*
323 * Large Flash or SRAM
324 */
325 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
326 ebc0_cs2_bxap_value = 0x048ff240;
327 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
328 break;
329
330 /*-------------------------------------------------------------------*/
331 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
332 /*-------------------------------------------------------------------*/
333 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
334 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
335
336 /* Small flash */
337 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
338 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
339 break;
340
341 /*-------------------------------------------------------------------*/
342 default:
343 /*-------------------------------------------------------------------*/
344 /* BOOT_DEVICE_UNKNOWN */
345 break;
346 }
347
348 mtebc(pb0ap, ebc0_cs0_bxap_value);
349 mtebc(pb0cr, ebc0_cs0_bxcr_value);
350 mtebc(pb2ap, ebc0_cs2_bxap_value);
351 mtebc(pb2cr, ebc0_cs2_bxcr_value);
352
353 /*--------------------------------------------------------------------+
354 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
355 +--------------------------------------------------------------------+
356 +---------------------------------------------------------------------+
357 |Interrupt| Source | Pol. | Sensi.| Crit. |
358 +---------+-----------------------------------+-------+-------+-------+
359 | IRQ 00 | UART0 | High | Level | Non |
360 | IRQ 01 | UART1 | High | Level | Non |
361 | IRQ 02 | IIC0 | High | Level | Non |
362 | IRQ 03 | IIC1 | High | Level | Non |
363 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
364 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
365 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
366 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
367 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
368 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
369 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
370 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
371 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
372 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
373 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
374 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
375 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
376 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
377 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
378 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
379 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
380 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
381 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
382 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
383 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
384 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
385 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
386 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
387 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
388 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
389 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
390 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
391 |----------------------------------------------------------------------
392 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
393 | IRQ 33 | MAL Serr | High | Level | Non |
394 | IRQ 34 | MAL Txde | High | Level | Non |
395 | IRQ 35 | MAL Rxde | High | Level | Non |
396 | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
397 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
398 | IRQ 38 | MAL TX EOB | High | Level | Non |
399 | IRQ 39 | MAL RX EOB | High | Level | Non |
400 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
401 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
402 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
403 | IRQ 43 | L2 Cache | Risin | Edge | Non |
404 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
405 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
406 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
407 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
408 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
409 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
410 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
411 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
412 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
413 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
414 | IRQ 54 | DMA Error | High | Level | Non |
415 | IRQ 55 | DMA I2O Error | High | Level | Non |
416 | IRQ 56 | Serial ROM | High | Level | Non |
417 | IRQ 57 | PCIX0 Error | High | Edge | Non |
418 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
419 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
420 | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
421 | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
422 | IRQ 62 | Reserved | High | Level | Non |
423 | IRQ 63 | XOR | High | Level | Non |
424 |----------------------------------------------------------------------
425 | IRQ 64 | PE0 AL | High | Level | Non |
426 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
427 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
428 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
429 | IRQ 68 | PE0 TCR | High | Level | Non |
430 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
431 | IRQ 70 | PE0 DCR Error | High | Level | Non |
432 | IRQ 71 | Reserved | N/A | N/A | Non |
433 | IRQ 72 | PE1 AL | High | Level | Non |
434 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
435 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
436 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
437 | IRQ 76 | PE1 TCR | High | Level | Non |
438 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
439 | IRQ 78 | PE1 DCR Error | High | Level | Non |
440 | IRQ 79 | Reserved | N/A | N/A | Non |
441 | IRQ 80 | PE2 AL | High | Level | Non |
442 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
443 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
444 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
445 | IRQ 84 | PE2 TCR | High | Level | Non |
446 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
447 | IRQ 86 | PE2 DCR Error | High | Level | Non |
448 | IRQ 87 | Reserved | N/A | N/A | Non |
449 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
450 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
451 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
452 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
453 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
454 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
455 | IRQ 94 | Reserved | N/A | N/A | Non |
456 | IRQ 95 | Reserved | N/A | N/A | Non |
457 |---------------------------------------------------------------------
458 | IRQ 96 | PE0 INTA | High | Level | Non |
459 | IRQ 97 | PE0 INTB | High | Level | Non |
460 | IRQ 98 | PE0 INTC | High | Level | Non |
461 | IRQ 99 | PE0 INTD | High | Level | Non |
462 | IRQ 100 | PE1 INTA | High | Level | Non |
463 | IRQ 101 | PE1 INTB | High | Level | Non |
464 | IRQ 102 | PE1 INTC | High | Level | Non |
465 | IRQ 103 | PE1 INTD | High | Level | Non |
466 | IRQ 104 | PE2 INTA | High | Level | Non |
467 | IRQ 105 | PE2 INTB | High | Level | Non |
468 | IRQ 106 | PE2 INTC | High | Level | Non |
469 | IRQ 107 | PE2 INTD | Risin | Edge | Non |
470 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
471 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
472 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
473 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
474 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
475 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
476 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
477 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
478 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
479 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
480 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
481 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
482 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
483 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
484 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
485 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
486 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
487 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
488 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
489 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
490 +---------+-----------------------------------+-------+-------+------*/
491 /*--------------------------------------------------------------------+
492 | Put UICs in PowerPC440SPemode.
493 | Initialise UIC registers. Clear all interrupts. Disable all
494 | interrupts.
495 | Set critical interrupt values. Set interrupt polarities. Set
496 | interrupt trigger levels. Make bit 0 High priority. Clear all
497 | interrupts again.
498 +-------------------------------------------------------------------*/
499 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
500 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
501 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
502 * interrupts */
503 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
504 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
505 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
506 * priority */
507 mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
508 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
509
510 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
511 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
512 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
513 * interrupts */
514 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
515 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
516 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
517 * priority */
518 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
519 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
520
521 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
522 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
523 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
524 * interrupts */
525 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
526 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
527 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
528 * priority */
529 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
530 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
531
532 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
533 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
534 * cascade to be checked */
535 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
536 * interrupts */
537 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
538 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
539 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
540 * priority */
541 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
542 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
543
544 /* SDR0_MFR should be part of Ethernet init */
545 mfsdr (sdr_mfr, mfr);
546 mfr &= ~SDR0_MFR_ECS_MASK;
547 /*mtsdr(sdr_mfr, mfr);*/
548 fpga_init();
549
550 return 0;
551 }
552
553 int checkboard (void)
554 {
555 char *s = getenv("serial#");
556
557 printf("Board: Yucca - AMCC 440SPe Evaluation Board");
558 if (s != NULL) {
559 puts(", serial# ");
560 puts(s);
561 }
562 putc('\n');
563
564 return 0;
565 }
566
567 /*
568 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
569 * board specific values.
570 */
571 static int ppc440spe_rev_a(void)
572 {
573 if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
574 return 1;
575 else
576 return 0;
577 }
578
579 u32 ddr_wrdtr(u32 default_val) {
580 /*
581 * Yucca boards with 440SPe rev. A need a slightly different setup
582 * for the MCIF0_WRDTR register.
583 */
584 if (ppc440spe_rev_a())
585 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
586
587 return default_val;
588 }
589
590 u32 ddr_clktr(u32 default_val) {
591 /*
592 * Yucca boards with 440SPe rev. A need a slightly different setup
593 * for the MCIF0_CLKTR register.
594 */
595 if (ppc440spe_rev_a())
596 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
597
598 return default_val;
599 }
600
601 #if defined(CFG_DRAM_TEST)
602 int testdram (void)
603 {
604 uint *pstart = (uint *) 0x00000000;
605 uint *pend = (uint *) 0x08000000;
606 uint *p;
607
608 for (p = pstart; p < pend; p++)
609 *p = 0xaaaaaaaa;
610
611 for (p = pstart; p < pend; p++) {
612 if (*p != 0xaaaaaaaa) {
613 printf ("SDRAM test fails at: %08x\n", (uint) p);
614 return 1;
615 }
616 }
617
618 for (p = pstart; p < pend; p++)
619 *p = 0x55555555;
620
621 for (p = pstart; p < pend; p++) {
622 if (*p != 0x55555555) {
623 printf ("SDRAM test fails at: %08x\n", (uint) p);
624 return 1;
625 }
626 }
627 return 0;
628 }
629 #endif
630
631 /*************************************************************************
632 * pci_pre_init
633 *
634 * This routine is called just prior to registering the hose and gives
635 * the board the opportunity to check things. Returning a value of zero
636 * indicates that things are bad & PCI initialization should be aborted.
637 *
638 * Different boards may wish to customize the pci controller structure
639 * (add regions, override default access routines, etc) or perform
640 * certain pre-initialization actions.
641 *
642 ************************************************************************/
643 #if defined(CONFIG_PCI)
644 int pci_pre_init(struct pci_controller * hose )
645 {
646 unsigned long strap;
647
648 /*-------------------------------------------------------------------+
649 * The yucca board is always configured as the host & requires the
650 * PCI arbiter to be enabled.
651 *-------------------------------------------------------------------*/
652 mfsdr(sdr_sdstp1, strap);
653 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
654 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
655 return 0;
656 }
657
658 return 1;
659 }
660 #endif /* defined(CONFIG_PCI) */
661
662 /*************************************************************************
663 * pci_target_init
664 *
665 * The bootstrap configuration provides default settings for the pci
666 * inbound map (PIM). But the bootstrap config choices are limited and
667 * may not be sufficient for a given board.
668 *
669 ************************************************************************/
670 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
671 void pci_target_init(struct pci_controller * hose )
672 {
673 /*-------------------------------------------------------------------+
674 * Disable everything
675 *-------------------------------------------------------------------*/
676 out32r( PCIX0_PIM0SA, 0 ); /* disable */
677 out32r( PCIX0_PIM1SA, 0 ); /* disable */
678 out32r( PCIX0_PIM2SA, 0 ); /* disable */
679 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
680
681 /*-------------------------------------------------------------------+
682 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
683 * strapping options to not support sizes such as 128/256 MB.
684 *-------------------------------------------------------------------*/
685 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
686 out32r( PCIX0_PIM0LAH, 0 );
687 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
688 out32r( PCIX0_BAR0, 0 );
689
690 /*-------------------------------------------------------------------+
691 * Program the board's subsystem id/vendor id
692 *-------------------------------------------------------------------*/
693 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
694 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
695
696 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
697 }
698 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
699
700 #if defined(CONFIG_PCI)
701 /*************************************************************************
702 * is_pci_host
703 *
704 * This routine is called to determine if a pci scan should be
705 * performed. With various hardware environments (especially cPCI and
706 * PPMC) it's insufficient to depend on the state of the arbiter enable
707 * bit in the strap register, or generic host/adapter assumptions.
708 *
709 * Rather than hard-code a bad assumption in the general 440 code, the
710 * 440 pci code requires the board to decide at runtime.
711 *
712 * Return 0 for adapter mode, non-zero for host (monarch) mode.
713 *
714 *
715 ************************************************************************/
716 int is_pci_host(struct pci_controller *hose)
717 {
718 /* The yucca board is always configured as host. */
719 return 1;
720 }
721
722 int yucca_pcie_card_present(int port)
723 {
724 u16 reg;
725
726 reg = in_be16((u16 *)FPGA_REG1C);
727 switch(port) {
728 case 0:
729 return !(reg & FPGA_REG1C_PE0_PRSNT);
730 case 1:
731 return !(reg & FPGA_REG1C_PE1_PRSNT);
732 case 2:
733 return !(reg & FPGA_REG1C_PE2_PRSNT);
734 default:
735 return 0;
736 }
737 }
738
739 /*
740 * For the given slot, set rootpoint mode, send power to the slot,
741 * turn on the green LED and turn off the yellow LED, enable the clock
742 * and turn off reset.
743 */
744 void yucca_setup_pcie_fpga_rootpoint(int port)
745 {
746 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
747
748 switch(port) {
749 case 0:
750 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
751 endpoint = 0;
752 power = FPGA_REG1A_PE0_PWRON;
753 green_led = FPGA_REG1A_PE0_GLED;
754 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
755 yellow_led = FPGA_REG1A_PE0_YLED;
756 reset_off = FPGA_REG1C_PE0_PERST;
757 break;
758 case 1:
759 rootpoint = 0;
760 endpoint = FPGA_REG1C_PE1_ENDPOINT;
761 power = FPGA_REG1A_PE1_PWRON;
762 green_led = FPGA_REG1A_PE1_GLED;
763 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
764 yellow_led = FPGA_REG1A_PE1_YLED;
765 reset_off = FPGA_REG1C_PE1_PERST;
766 break;
767 case 2:
768 rootpoint = 0;
769 endpoint = FPGA_REG1C_PE2_ENDPOINT;
770 power = FPGA_REG1A_PE2_PWRON;
771 green_led = FPGA_REG1A_PE2_GLED;
772 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
773 yellow_led = FPGA_REG1A_PE2_YLED;
774 reset_off = FPGA_REG1C_PE2_PERST;
775 break;
776
777 default:
778 return;
779 }
780
781 out_be16((u16 *)FPGA_REG1A,
782 ~(power | clock | green_led) &
783 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
784
785 out_be16((u16 *)FPGA_REG1C,
786 ~(endpoint | reset_off) &
787 (rootpoint | in_be16((u16 *)FPGA_REG1C)));
788 /*
789 * Leave device in reset for a while after powering on the
790 * slot to give it a chance to initialize.
791 */
792 udelay(250 * 1000);
793
794 out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
795 }
796 /*
797 * For the given slot, set endpoint mode, send power to the slot,
798 * turn on the green LED and turn off the yellow LED, enable the clock
799 * .In end point mode reset bit is read only.
800 */
801 void yucca_setup_pcie_fpga_endpoint(int port)
802 {
803 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
804
805 switch(port) {
806 case 0:
807 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
808 endpoint = 0;
809 power = FPGA_REG1A_PE0_PWRON;
810 green_led = FPGA_REG1A_PE0_GLED;
811 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
812 yellow_led = FPGA_REG1A_PE0_YLED;
813 reset_off = FPGA_REG1C_PE0_PERST;
814 break;
815 case 1:
816 rootpoint = 0;
817 endpoint = FPGA_REG1C_PE1_ENDPOINT;
818 power = FPGA_REG1A_PE1_PWRON;
819 green_led = FPGA_REG1A_PE1_GLED;
820 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
821 yellow_led = FPGA_REG1A_PE1_YLED;
822 reset_off = FPGA_REG1C_PE1_PERST;
823 break;
824 case 2:
825 rootpoint = 0;
826 endpoint = FPGA_REG1C_PE2_ENDPOINT;
827 power = FPGA_REG1A_PE2_PWRON;
828 green_led = FPGA_REG1A_PE2_GLED;
829 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
830 yellow_led = FPGA_REG1A_PE2_YLED;
831 reset_off = FPGA_REG1C_PE2_PERST;
832 break;
833
834 default:
835 return;
836 }
837
838 out_be16((u16 *)FPGA_REG1A,
839 ~(power | clock | green_led) &
840 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
841
842 out_be16((u16 *)FPGA_REG1C,
843 ~(rootpoint | reset_off) &
844 (endpoint | in_be16((u16 *)FPGA_REG1C)));
845 }
846
847 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
848
849 void pcie_setup_hoses(int busno)
850 {
851 struct pci_controller *hose;
852 int i, bus;
853 char *env;
854 unsigned int delay;
855
856 /*
857 * assume we're called after the PCIX hose is initialized, which takes
858 * bus ID 0 and therefore start numbering PCIe's from 1.
859 */
860 bus = busno;
861 for (i = 0; i <= 2; i++) {
862 /* Check for yucca card presence */
863 if (!yucca_pcie_card_present(i))
864 continue;
865
866 #ifdef PCIE_ENDPOINT
867 yucca_setup_pcie_fpga_endpoint(i);
868 if (ppc440spe_init_pcie_endport(i)) {
869 #else
870 yucca_setup_pcie_fpga_rootpoint(i);
871 if (ppc440spe_init_pcie_rootport(i)) {
872 #endif
873 printf("PCIE%d: initialization failed\n", i);
874 continue;
875 }
876
877 hose = &pcie_hose[i];
878 hose->first_busno = bus;
879 hose->last_busno = bus;
880 hose->current_busno = bus;
881
882 /* setup mem resource */
883 pci_set_region(hose->regions + 0,
884 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
885 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
886 CFG_PCIE_MEMSIZE,
887 PCI_REGION_MEM
888 );
889 hose->region_count = 1;
890 pci_register_hose(hose);
891
892 #ifdef PCIE_ENDPOINT
893 ppc440spe_setup_pcie_endpoint(hose, i);
894 /*
895 * Reson for no scanning is endpoint can not generate
896 * upstream configuration accesses.
897 */
898 #else
899 ppc440spe_setup_pcie_rootpoint(hose, i);
900
901 env = getenv ("pciscandelay");
902 if (env != NULL) {
903 delay = simple_strtoul (env, NULL, 10);
904 if (delay > 5)
905 printf ("Warning, expect noticable delay before PCIe"
906 "scan due to 'pciscandelay' value!\n");
907 mdelay (delay * 1000);
908 }
909
910 /*
911 * Config access can only go down stream
912 */
913 hose->last_busno = pci_hose_scan(hose);
914 bus = hose->last_busno + 1;
915 #endif
916 }
917 }
918 #endif /* defined(CONFIG_PCI) */
919
920 int misc_init_f (void)
921 {
922 uint reg;
923 #if defined(CONFIG_STRESS)
924 uint i ;
925 uint disp;
926 #endif
927
928 out16(FPGA_REG10, (in16(FPGA_REG10) &
929 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
930 FPGA_REG10_10MHZ_ENABLE |
931 FPGA_REG10_100MHZ_ENABLE |
932 FPGA_REG10_GIGABIT_ENABLE |
933 FPGA_REG10_FULL_DUPLEX );
934
935 udelay(10000); /* wait 10ms */
936
937 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
938
939 /* minimal init for PCIe */
940 /* pci express 0 Endpoint Mode */
941 mfsdr(SDR0_PE0DLPSET, reg);
942 reg &= (~0x00400000);
943 mtsdr(SDR0_PE0DLPSET, reg);
944 /* pci express 1 Rootpoint Mode */
945 mfsdr(SDR0_PE1DLPSET, reg);
946 reg |= 0x00400000;
947 mtsdr(SDR0_PE1DLPSET, reg);
948 /* pci express 2 Rootpoint Mode */
949 mfsdr(SDR0_PE2DLPSET, reg);
950 reg |= 0x00400000;
951 mtsdr(SDR0_PE2DLPSET, reg);
952
953 out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
954 ~FPGA_REG1C_PE0_ROOTPOINT &
955 ~FPGA_REG1C_PE1_ENDPOINT &
956 ~FPGA_REG1C_PE2_ENDPOINT));
957
958 #if defined(CONFIG_STRESS)
959 /*
960 * all this setting done by linux only needed by stress an charac. test
961 * procedure
962 * PCIe 1 Rootpoint PCIe2 Endpoint
963 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
964 * Power Level
965 */
966 for (i = 0, disp = 0; i < 8; i++, disp += 3) {
967 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
968 reg |= 0x33000000;
969 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
970 }
971
972 /*
973 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
974 * Power Level
975 */
976 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
977 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
978 reg |= 0x33000000;
979 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
980 }
981
982 /*
983 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
984 * Power Level
985 */
986 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
987 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
988 reg |= 0x33000000;
989 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
990 }
991
992 reg = 0x21242222;
993 mtsdr(SDR0_PE2UTLSET1, reg);
994 reg = 0x11000000;
995 mtsdr(SDR0_PE2UTLSET2, reg);
996 /* pci express 1 Endpoint Mode */
997 reg = 0x00004000;
998 mtsdr(SDR0_PE2DLPSET, reg);
999
1000 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
1001 #endif
1002 return 0;
1003 }
1004
1005 void fpga_init(void)
1006 {
1007 /*
1008 * by default sdram access is disabled by fpga
1009 */
1010 out16(FPGA_REG10, (in16 (FPGA_REG10) |
1011 FPGA_REG10_SDRAM_ENABLE |
1012 FPGA_REG10_ENABLE_DISPLAY ));
1013
1014 return;
1015 }
1016
1017 #ifdef CONFIG_POST
1018 /*
1019 * Returns 1 if keys pressed to start the power-on long-running tests
1020 * Called from board_init_f().
1021 */
1022 int post_hotkeys_pressed(void)
1023 {
1024 return (ctrlc());
1025 }
1026 #endif
1027
1028 /*---------------------------------------------------------------------------+
1029 | onboard_pci_arbiter_selected => from EPLD
1030 +---------------------------------------------------------------------------*/
1031 int onboard_pci_arbiter_selected(int core_pci)
1032 {
1033 #if 0
1034 unsigned long onboard_pci_arbiter_sel;
1035
1036 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1037
1038 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1039 return (BOARD_OPTION_SELECTED);
1040 else
1041 #endif
1042 return (BOARD_OPTION_NOT_SELECTED);
1043 }
"Das U-Boot" Source Tree