board/armltd/integrator/integrator.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002
   4  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   5  * Marius Groeger <mgroeger@sysgo.de>
   6  *
   7  * (C) Copyright 2002
   8  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   9  *
  10  * (C) Copyright 2003
  11  * Texas Instruments, <www.ti.com>
  12  * Kshitij Gupta <Kshitij@ti.com>
  13  *
  14  * (C) Copyright 2004
  15  * ARM Ltd.
  16  * Philippe Robin, <philippe.robin@arm.com>
  17  */
  18
  19 #include <common.h>
  20 #include <cpu_func.h>
  21 #include <dm.h>
  22 #include <env.h>
  23 #include <init.h>
  24 #include <netdev.h>
  25 #include <asm/io.h>
  26 #include <dm/platform_data/serial_pl01x.h>
  27 #include "arm-ebi.h"
  28 #include "integrator-sc.h"
  29 #include <asm/mach-types.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static const struct pl01x_serial_platdata serial_platdata = {
  34         .base = 0x16000000,
  35 #ifdef CONFIG_ARCH_CINTEGRATOR
  36         .type = TYPE_PL011,
  37         .clock = 14745600,
  38 #else
  39         .type = TYPE_PL010,
  40         .clock = 0, /* Not used for PL010 */
  41 #endif
  42 };
  43
  44 U_BOOT_DEVICE(integrator_serials) = {
  45         .name = "serial_pl01x",
  46         .platdata = &serial_platdata,
  47 };
  48
  49 void peripheral_power_enable (void);
  50
  51 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  52 void show_boot_progress(int progress)
  53 {
  54         printf("Boot reached stage %d\n", progress);
  55 }
  56 #endif
  57
  58 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  59
  60 /*
  61  * Miscellaneous platform dependent initialisations
  62  */
  63
  64 int board_init (void)
  65 {
  66         u32 val;
  67
  68         /* arch number of Integrator Board */
  69 #ifdef CONFIG_ARCH_CINTEGRATOR
  70         gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
  71 #else
  72         gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
  73 #endif
  74
  75         /* adress of boot parameters */
  76         gd->bd->bi_boot_params = 0x00000100;
  77
  78 #ifdef CONFIG_CM_REMAP
  79 extern void cm_remap(void);
  80         cm_remap();     /* remaps writeable memory to 0x00000000 */
  81 #endif
  82
  83 #ifdef CONFIG_ARCH_CINTEGRATOR
  84         /*
  85          * Flash protection on the Integrator/CP is in a simple register
  86          */
  87         val = readl(CP_FLASHPROG);
  88         val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
  89         writel(val, CP_FLASHPROG);
  90 #else
  91         /*
  92          * The Integrator/AP has some special protection mechanisms
  93          * for the external memories, first the External Bus Interface (EBI)
  94          * then the system controller (SC).
  95          *
  96          * The system comes up with the flash memory non-writable and
  97          * configuration locked. If we want U-Boot to be used for flash
  98          * access we cannot have the flash memory locked.
  99          */
 100         writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
 101         val = readl(EBI_BASE + EBI_CSR1_REG);
 102         val &= EBI_CSR_WREN_MASK;
 103         val |= EBI_CSR_WREN_ENABLE;
 104         writel(val, EBI_BASE + EBI_CSR1_REG);
 105         writel(0, EBI_BASE + EBI_LOCK_REG);
 106
 107         /*
 108          * Set up the system controller to remove write protection from
 109          * the flash memory and enable Vpp
 110          */
 111         writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
 112 #endif
 113
 114         icache_enable();
 115
 116         return 0;
 117 }
 118
 119 int misc_init_r (void)
 120 {
 121         env_set("verify", "n");
 122         return (0);
 123 }
 124
 125 /*
 126  * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
 127  * from there, which means we cannot test the RAM underneath the ROM at this
 128  * point. It will be unmapped later on, when we are executing from the
 129  * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
 130  * RAM on higher addresses works fine.
 131  */
 132 #define REMAPPED_FLASH_SZ 0x40000
 133
 134 int dram_init (void)
 135 {
 136         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 137 #ifdef CONFIG_CM_SPD_DETECT
 138         {
 139 extern void dram_query(void);
 140         u32 cm_reg_sdram;
 141         u32 sdram_shift;
 142
 143         dram_query();   /* Assembler accesses to CM registers */
 144                         /* Queries the SPD values             */
 145
 146         /* Obtain the SDRAM size from the CM SDRAM register */
 147
 148         cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
 149         /*   Register         SDRAM size
 150          *
 151          *   0xXXXXXXbbb000bb    16 MB
 152          *   0xXXXXXXbbb001bb    32 MB
 153          *   0xXXXXXXbbb010bb    64 MB
 154          *   0xXXXXXXbbb011bb   128 MB
 155          *   0xXXXXXXbbb100bb   256 MB
 156          *
 157          */
 158         sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
 159         gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
 160                                     REMAPPED_FLASH_SZ,
 161                                     0x01000000 << sdram_shift);
 162         }
 163 #else
 164         gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
 165                                     REMAPPED_FLASH_SZ,
 166                                     PHYS_SDRAM_1_SIZE);
 167 #endif /* CM_SPD_DETECT */
 168         /* We only have one bank of RAM, set it to whatever was detected */
 169         gd->bd->bi_dram[0].size  = gd->ram_size;
 170
 171         return 0;
 172 }
 173
 174 #ifdef CONFIG_CMD_NET
 175 int board_eth_init(bd_t *bis)
 176 {
 177         int rc = 0;
 178 #ifdef CONFIG_SMC91111
 179         rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
 180 #endif
 181         rc += pci_eth_init(bis);
 182         return rc;
 183 }
 184 #endif