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1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35 #include <common.h>
36 #include <netdev.h>
37 #include <asm/io.h>
38 #include <asm/arch/systimer.h>
39 #include <asm/arch/sysctrl.h>
40 #include <asm/arch/wdt.h>
41 #include "../drivers/mmc/arm_pl180_mmci.h"
42
43 static ulong timestamp;
44 static ulong lastdec;
45
46 static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
47 static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
48 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
49
50 static void flash__init(void);
51 static void vexpress_timer_init(void);
52 DECLARE_GLOBAL_DATA_PTR;
53
54 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
55 void show_boot_progress(int progress)
56 {
57 printf("Boot reached stage %d\n", progress);
58 }
59 #endif
60
61 static inline void delay(ulong loops)
62 {
63 __asm__ volatile ("1:\n"
64 "subs %0, %1, #1\n"
65 "bne 1b" : "=r" (loops) : "0" (loops));
66 }
67
68 int board_init(void)
69 {
70 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
71 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
72 gd->flags = 0;
73
74 icache_enable();
75 flash__init();
76 vexpress_timer_init();
77
78 return 0;
79 }
80
81 int board_eth_init(bd_t *bis)
82 {
83 int rc = 0;
84 #ifdef CONFIG_SMC911X
85 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
86 #endif
87 return rc;
88 }
89
90 int cpu_mmc_init(bd_t *bis)
91 {
92 int rc = 0;
93 #ifdef CONFIG_ARM_PL180_MMCI
94 rc = arm_pl180_mmci_init();
95 #endif
96 return rc;
97 }
98
99 static void flash__init(void)
100 {
101 /* Setup the sytem control register to allow writing to flash */
102 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
103 &sysctrl_base->scflashctrl);
104 }
105
106 int dram_init(void)
107 {
108 gd->ram_size =
109 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
110 return 0;
111 }
112
113 void dram_init_banksize(void)
114 {
115 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
116 gd->bd->bi_dram[0].size =
117 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
118 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
119 gd->bd->bi_dram[1].size =
120 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
121 }
122
123 int timer_init(void)
124 {
125 return 0;
126 }
127
128 /*
129 * Start timer:
130 * Setup a 32 bit timer, running at 1KHz
131 * Versatile Express Motherboard provides 1 MHz timer
132 */
133 static void vexpress_timer_init(void)
134 {
135 /*
136 * Set clock frequency in system controller:
137 * VEXPRESS_REFCLK is 32KHz
138 * VEXPRESS_TIMCLK is 1MHz
139 */
140 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
141 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
142 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
143
144 /*
145 * Set Timer0 to be:
146 * Enabled, free running, no interrupt, 32-bit, wrapping
147 */
148 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
149 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
150 writel(SYSTIMER_EN | SYSTIMER_32BIT | \
151 readl(&systimer_base->timer0control), \
152 &systimer_base->timer0control);
153
154 reset_timer_masked();
155 }
156
157 /* Use the ARM Watchdog System to cause reset */
158 void reset_cpu(ulong addr)
159 {
160 writeb(WDT_EN, &wdt_base->wdogcontrol);
161 writel(WDT_RESET_LOAD, &wdt_base->wdogload);
162 while (1)
163 ;
164 }
165
166 /*
167 * Delay x useconds AND perserve advance timstamp value
168 * assumes timer is ticking at 1 msec
169 */
170 void __udelay(ulong usec)
171 {
172 ulong tmo, tmp;
173
174 tmo = usec / 1000;
175 tmp = get_timer(0); /* get current timestamp */
176
177 /*
178 * If setting this forward will roll time stamp then
179 * reset "advancing" timestamp to 0 and set lastdec value
180 * otherwise set the advancing stamp to the wake up time
181 */
182 if ((tmo + tmp + 1) < tmp)
183 reset_timer_masked();
184 else
185 tmo += tmp;
186
187 while (get_timer_masked() < tmo)
188 ; /* loop till wakeup event */
189 }
190
191 ulong get_timer(ulong base)
192 {
193 return get_timer_masked() - base;
194 }
195
196 void reset_timer_masked(void)
197 {
198 lastdec = readl(&systimer_base->timer0value) / 1000;
199 timestamp = 0;
200 }
201
202 ulong get_timer_masked(void)
203 {
204 ulong now = readl(&systimer_base->timer0value) / 1000;
205
206 if (lastdec >= now) { /* normal mode (non roll) */
207 timestamp += lastdec - now;
208 } else { /* count down timer overflowed */
209 /*
210 * nts = ts + ld - now
211 * ts = old stamp, ld = time before passing through - 1
212 * now = amount of time after passing though - 1
213 * nts = new "advancing time stamp"
214 */
215 timestamp += lastdec + SYSTIMER_RELOAD - now;
216 }
217 lastdec = now;
218
219 return timestamp;
220 }
221
222 void lowlevel_init(void)
223 {
224 }
225
226 ulong get_board_rev(void){
227 return readl((u32 *)SYS_ID);
228 }
229
230 unsigned long long get_ticks(void)
231 {
232 return get_timer(0);
233 }
234
235 ulong get_tbclk (void)
236 {
237 return (ulong)CONFIG_SYS_HZ;
238 }