3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
15 * Philippe Robin, <philippe.robin@arm.com>
17 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/arch/systimer.h>
25 #include <asm/arch/sysctrl.h>
26 #include <asm/arch/wdt.h>
27 #include "../drivers/mmc/arm_pl180_mmci.h"
29 static ulong timestamp
;
32 static struct systimer
*systimer_base
= (struct systimer
*)V2M_TIMER01
;
33 static struct sysctrl
*sysctrl_base
= (struct sysctrl
*)SCTL_BASE
;
35 static void flash__init(void);
36 static void vexpress_timer_init(void);
37 DECLARE_GLOBAL_DATA_PTR
;
39 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
40 void show_boot_progress(int progress
)
42 printf("Boot reached stage %d\n", progress
);
46 static inline void delay(ulong loops
)
48 __asm__
volatile ("1:\n"
50 "bne 1b" : "=r" (loops
) : "0" (loops
));
55 gd
->bd
->bi_boot_params
= LINUX_BOOT_PARAM_ADDR
;
56 gd
->bd
->bi_arch_number
= MACH_TYPE_VEXPRESS
;
61 vexpress_timer_init();
66 int board_eth_init(bd_t
*bis
)
70 rc
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);
75 int cpu_mmc_init(bd_t
*bis
)
79 #ifdef CONFIG_ARM_PL180_MMCI
80 struct pl180_mmc_host
*host
;
82 host
= malloc(sizeof(struct pl180_mmc_host
));
85 memset(host
, 0, sizeof(*host
));
87 strcpy(host
->name
, "MMC");
88 host
->base
= (struct sdi_registers
*)CONFIG_ARM_PL180_MMCI_BASE
;
89 host
->pwr_init
= INIT_PWR
;
90 host
->clkdiv_init
= SDI_CLKCR_CLKDIV_INIT_V1
| SDI_CLKCR_CLKEN
;
91 host
->voltages
= VOLTAGE_WINDOW_MMC
;
93 host
->clock_in
= ARM_MCLK
;
94 host
->clock_min
= ARM_MCLK
/ (2 * (SDI_CLKCR_CLKDIV_INIT_V1
+ 1));
95 host
->clock_max
= CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
;
96 rc
= arm_pl180_mmci_init(host
);
101 static void flash__init(void)
103 /* Setup the sytem control register to allow writing to flash */
104 writel(readl(&sysctrl_base
->scflashctrl
) | VEXPRESS_FLASHPROG_FLVPPEN
,
105 &sysctrl_base
->scflashctrl
);
111 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, PHYS_SDRAM_1_SIZE
);
115 void dram_init_banksize(void)
117 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
118 gd
->bd
->bi_dram
[0].size
=
119 get_ram_size((long *)PHYS_SDRAM_1
, PHYS_SDRAM_1_SIZE
);
120 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
121 gd
->bd
->bi_dram
[1].size
=
122 get_ram_size((long *)PHYS_SDRAM_2
, PHYS_SDRAM_2_SIZE
);
132 * Setup a 32 bit timer, running at 1KHz
133 * Versatile Express Motherboard provides 1 MHz timer
135 static void vexpress_timer_init(void)
138 * Set clock frequency in system controller:
139 * VEXPRESS_REFCLK is 32KHz
140 * VEXPRESS_TIMCLK is 1MHz
142 writel(SP810_TIMER0_ENSEL
| SP810_TIMER1_ENSEL
|
143 SP810_TIMER2_ENSEL
| SP810_TIMER3_ENSEL
|
144 readl(&sysctrl_base
->scctrl
), &sysctrl_base
->scctrl
);
148 * Enabled, free running, no interrupt, 32-bit, wrapping
150 writel(SYSTIMER_RELOAD
, &systimer_base
->timer0load
);
151 writel(SYSTIMER_RELOAD
, &systimer_base
->timer0value
);
152 writel(SYSTIMER_EN
| SYSTIMER_32BIT
|
153 readl(&systimer_base
->timer0control
),
154 &systimer_base
->timer0control
);
156 reset_timer_masked();
159 int v2m_cfg_write(u32 devfn
, u32 data
)
161 /* Configuration interface broken? */
164 devfn
|= SYS_CFG_START
| SYS_CFG_WRITE
;
166 val
= readl(V2M_SYS_CFGSTAT
);
167 writel(val
& ~SYS_CFG_COMPLETE
, V2M_SYS_CFGSTAT
);
169 writel(data
, V2M_SYS_CFGDATA
);
170 writel(devfn
, V2M_SYS_CFGCTRL
);
173 val
= readl(V2M_SYS_CFGSTAT
);
176 return !!(val
& SYS_CFG_ERR
);
179 /* Use the ARM Watchdog System to cause reset */
180 void reset_cpu(ulong addr
)
182 if (v2m_cfg_write(SYS_CFG_REBOOT
| SYS_CFG_SITE_MB
, 0))
183 printf("Unable to reboot\n");
187 * Delay x useconds AND perserve advance timstamp value
188 * assumes timer is ticking at 1 msec
190 void __udelay(ulong usec
)
195 tmp
= get_timer(0); /* get current timestamp */
198 * If setting this forward will roll time stamp then
199 * reset "advancing" timestamp to 0 and set lastdec value
200 * otherwise set the advancing stamp to the wake up time
202 if ((tmo
+ tmp
+ 1) < tmp
)
203 reset_timer_masked();
207 while (get_timer_masked() < tmo
)
208 ; /* loop till wakeup event */
211 ulong
get_timer(ulong base
)
213 return get_timer_masked() - base
;
216 void reset_timer_masked(void)
218 lastdec
= readl(&systimer_base
->timer0value
) / 1000;
222 ulong
get_timer_masked(void)
224 ulong now
= readl(&systimer_base
->timer0value
) / 1000;
226 if (lastdec
>= now
) { /* normal mode (non roll) */
227 timestamp
+= lastdec
- now
;
228 } else { /* count down timer overflowed */
230 * nts = ts + ld - now
231 * ts = old stamp, ld = time before passing through - 1
232 * now = amount of time after passing though - 1
233 * nts = new "advancing time stamp"
235 timestamp
+= lastdec
+ SYSTIMER_RELOAD
- now
;
242 void lowlevel_init(void)
246 ulong
get_board_rev(void){
247 return readl((u32
*)SYS_ID
);
250 unsigned long long get_ticks(void)
255 ulong
get_tbclk(void)
257 return (ulong
)CONFIG_SYS_HZ
;
260 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
261 /* Setting the address at which secondary cores start from.
262 * Versatile Express uses one address for all cores, so ignore corenr
264 void smp_set_core_boot_addr(unsigned long addr
, int corenr
)
266 /* The SYSFLAGS register on VExpress needs to be cleared first
267 * by writing to the next address, since any writes to the address
268 * at offset 0 will only be ORed in
270 writel(~0, CONFIG_SYSFLAGS_ADDR
+ 4);
271 writel(addr
, CONFIG_SYSFLAGS_ADDR
);