board/atmel/at91sam9n12ek/at91sam9n12ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Atmel Corporation
   4  * Josh Wu <josh.wu@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <vsprintf.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/at91sam9x5_matrix.h>
  13 #include <asm/arch/at91sam9_smc.h>
  14 #include <asm/arch/at91_common.h>
  15 #include <asm/arch/at91_rstc.h>
  16 #include <asm/arch/at91_pio.h>
  17 #include <asm/arch/clk.h>
  18 #include <debug_uart.h>
  19 #include <lcd.h>
  20 #include <atmel_hlcdc.h>
  21 #include <netdev.h>
  22
  23 #ifdef CONFIG_LCD_INFO
  24 #include <nand.h>
  25 #include <version.h>
  26 #endif
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34 #ifdef CONFIG_NAND_ATMEL
  35 static void at91sam9n12ek_nand_hw_init(void)
  36 {
  37         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  38         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  39         unsigned long csa;
  40
  41         /* Assign CS3 to NAND/SmartMedia Interface */
  42         csa = readl(&matrix->ebicsa);
  43         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  44         /* Configure databus */
  45         csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  46         /* Configure IO drive */
  47         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  48
  49         writel(csa, &matrix->ebicsa);
  50
  51         /* Configure SMC CS3 for NAND/SmartMedia */
  52         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  53                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  54                 &smc->cs[3].setup);
  55         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  56                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  57                 &smc->cs[3].pulse);
  58         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  59                 &smc->cs[3].cycle);
  60         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  61                 AT91_SMC_MODE_EXNW_DISABLE |
  62 #ifdef CONFIG_SYS_NAND_DBW_16
  63                 AT91_SMC_MODE_DBW_16 |
  64 #else /* CONFIG_SYS_NAND_DBW_8 */
  65                 AT91_SMC_MODE_DBW_8 |
  66 #endif
  67                 AT91_SMC_MODE_TDF_CYCLE(1),
  68                 &smc->cs[3].mode);
  69
  70         /* Configure RDY/BSY pin */
  71         at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  72
  73         /* Configure ENABLE pin for NandFlash */
  74         at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  75
  76         at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
  77         at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
  78         at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
  79         at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
  80 }
  81 #endif
  82
  83 #ifdef CONFIG_LCD
  84 vidinfo_t panel_info = {
  85         .vl_col = 480,
  86         .vl_row = 272,
  87         .vl_clk = 9000000,
  88         .vl_bpix = LCD_BPP,
  89         .vl_sync = 0,
  90         .vl_tft = 1,
  91         .vl_hsync_len = 5,
  92         .vl_left_margin = 8,
  93         .vl_right_margin = 43,
  94         .vl_vsync_len = 10,
  95         .vl_upper_margin = 4,
  96         .vl_lower_margin = 12,
  97         .mmio = ATMEL_BASE_LCDC,
  98 };
  99
 100 void lcd_enable(void)
 101 {
 102         at91_set_pio_output(AT91_PIO_PORTC, 25, 0);     /* power up */
 103 }
 104
 105 void lcd_disable(void)
 106 {
 107         at91_set_pio_output(AT91_PIO_PORTC, 25, 1);     /* power down */
 108 }
 109
 110 #ifdef CONFIG_LCD_INFO
 111 void lcd_show_board_info(void)
 112 {
 113         ulong dram_size, nand_size;
 114         int i;
 115         char temp[32];
 116
 117         lcd_printf("%s\n", U_BOOT_VERSION);
 118         lcd_printf("ATMEL Corp\n");
 119         lcd_printf("at91@atmel.com\n");
 120         lcd_printf("%s CPU at %s MHz\n",
 121                 ATMEL_CPU_NAME,
 122                 strmhz(temp, get_cpu_clk_rate()));
 123
 124         dram_size = 0;
 125         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 126                 dram_size += gd->bd->bi_dram[i].size;
 127         nand_size = 0;
 128         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 129                 nand_size += get_nand_dev_by_index(i)->size;
 130         lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 131                 dram_size >> 20,
 132                 nand_size >> 20);
 133 }
 134 #endif /* CONFIG_LCD_INFO */
 135 #endif /* CONFIG_LCD */
 136
 137 #ifdef CONFIG_KS8851_MLL
 138 void at91sam9n12ek_ks8851_hw_init(void)
 139 {
 140         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 141
 142         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
 143                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 144                &smc->cs[2].setup);
 145         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 146                AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
 147                &smc->cs[2].pulse);
 148         writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
 149                &smc->cs[2].cycle);
 150         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 151                AT91_SMC_MODE_EXNW_DISABLE |
 152                AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 153                AT91_SMC_MODE_TDF_CYCLE(1),
 154                &smc->cs[2].mode);
 155
 156         /* Configure NCS2 PIN */
 157         at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
 158 }
 159 #endif
 160
 161 #ifdef CONFIG_USB_ATMEL
 162 void at91sam9n12ek_usb_hw_init(void)
 163 {
 164         at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
 165 }
 166 #endif
 167
 168 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 169 void board_debug_uart_init(void)
 170 {
 171         at91_seriald_hw_init();
 172 }
 173 #endif
 174
 175 #ifdef CONFIG_BOARD_EARLY_INIT_F
 176 int board_early_init_f(void)
 177 {
 178 #ifdef CONFIG_DEBUG_UART
 179         debug_uart_init();
 180 #endif
 181         return 0;
 182 }
 183 #endif
 184
 185 int board_init(void)
 186 {
 187         /* adress of boot parameters */
 188         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 189
 190 #ifdef CONFIG_NAND_ATMEL
 191         at91sam9n12ek_nand_hw_init();
 192 #endif
 193
 194 #ifdef CONFIG_LCD
 195         at91_lcd_hw_init();
 196 #endif
 197
 198 #ifdef CONFIG_KS8851_MLL
 199         at91sam9n12ek_ks8851_hw_init();
 200 #endif
 201
 202 #ifdef CONFIG_USB_ATMEL
 203         at91sam9n12ek_usb_hw_init();
 204 #endif
 205
 206         return 0;
 207 }
 208
 209 #ifdef CONFIG_KS8851_MLL
 210 int board_eth_init(bd_t *bis)
 211 {
 212         return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
 213 }
 214 #endif
 215
 216 int dram_init(void)
 217 {
 218         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 219                                         CONFIG_SYS_SDRAM_SIZE);
 220         return 0;
 221 }
 222
 223 #if defined(CONFIG_SPL_BUILD)
 224 #include <spl.h>
 225 #include <nand.h>
 226
 227 void at91_spl_board_init(void)
 228 {
 229 #ifdef CONFIG_SD_BOOT
 230         at91_mci_hw_init();
 231 #elif CONFIG_NAND_BOOT
 232         at91sam9n12ek_nand_hw_init();
 233 #elif CONFIG_SPI_BOOT
 234         at91_spi0_hw_init(1 << 4);
 235 #endif
 236 }
 237
 238 #include <asm/arch/atmel_mpddrc.h>
 239 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 240 {
 241         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 242
 243         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 244                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 245                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 246                     ATMEL_MPDDRC_CR_NB_8BANKS |
 247                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
 248
 249         ddr2->rtr = 0x411;
 250
 251         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 252                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 253                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 254                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 255                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 256                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 257                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 258                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 259
 260         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 261                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 262                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 263                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 264
 265         ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 266                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 267                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 268                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 269 }
 270
 271 void mem_init(void)
 272 {
 273         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 274         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 275         struct atmel_mpddrc_config ddr2;
 276         unsigned long csa;
 277
 278         ddr2_conf(&ddr2);
 279
 280         /* enable DDR2 clock */
 281         writel(AT91_PMC_DDR, &pmc->scer);
 282
 283         /* Chip select 1 is for DDR2/SDRAM */
 284         csa = readl(&matrix->ebicsa);
 285         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 286         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 287         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 288         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 289         writel(csa, &matrix->ebicsa);
 290
 291         /* DDRAM2 Controller initialize */
 292         ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 293 }
 294 #endif