board/atmel/at91sam9rlek/at91sam9rlek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <config.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <vsprintf.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/mach-types.h>
  15 #include <asm/arch/at91sam9rl.h>
  16 #include <asm/arch/at91sam9rl_matrix.h>
  17 #include <asm/arch/at91sam9_smc.h>
  18 #include <asm/arch/at91_common.h>
  19 #include <asm/arch/at91_rstc.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/gpio.h>
  22
  23 #include <atmel_lcdc.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_CMD_NAND
  33 static void at91sam9rlek_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37         unsigned long csa;
  38
  39         /* Enable CS3 */
  40         csa = readl(&matrix->ebicsa);
  41         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  42
  43         writel(csa, &matrix->ebicsa);
  44
  45         /* Configure SMC CS3 for NAND/SmartMedia */
  46         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  48                 &smc->cs[3].setup);
  49         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  50                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  51                 &smc->cs[3].pulse);
  52         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  53                 &smc->cs[3].cycle);
  54         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55                 AT91_SMC_MODE_EXNW_DISABLE |
  56 #ifdef CONFIG_SYS_NAND_DBW_16
  57                 AT91_SMC_MODE_DBW_16 |
  58 #else /* CONFIG_SYS_NAND_DBW_8 */
  59                 AT91_SMC_MODE_DBW_8 |
  60 #endif
  61                 AT91_SMC_MODE_TDF_CYCLE(2),
  62                 &smc->cs[3].mode);
  63
  64         at91_periph_clk_enable(ATMEL_ID_PIOD);
  65
  66         /* Configure RDY/BSY */
  67         at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
  68
  69         /* Enable NandFlash */
  70         at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
  71
  72         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
  73         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  78 void board_debug_uart_init(void)
  79 {
  80         at91_seriald_hw_init();
  81 }
  82 #endif
  83
  84 #ifdef CONFIG_BOARD_EARLY_INIT_F
  85 int board_early_init_f(void)
  86 {
  87         return 0;
  88 }
  89 #endif
  90
  91 int board_init(void)
  92 {
  93         /* arch number of AT91SAM9RLEK-Board */
  94         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
  95         /* adress of boot parameters */
  96         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
  97
  98 #ifdef CONFIG_CMD_NAND
  99         at91sam9rlek_nand_hw_init();
 100 #endif
 101         return 0;
 102 }
 103
 104 int dram_init(void)
 105 {
 106         gd->ram_size = get_ram_size(
 107                 (void *)CFG_SYS_SDRAM_BASE,
 108                 CFG_SYS_SDRAM_SIZE);
 109         return 0;
 110 }