2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/at91sam9rl.h>
12 #include <asm/arch/at91sam9rl_matrix.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/at91_rstc.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
21 #include <atmel_lcdc.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
26 DECLARE_GLOBAL_DATA_PTR
;
28 /* ------------------------------------------------------------------------- */
30 * Miscelaneous platform dependent initialisations
33 #ifdef CONFIG_CMD_NAND
34 static void at91sam9rlek_nand_hw_init(void)
36 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
37 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
38 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
42 csa
= readl(&matrix
->ebicsa
);
43 csa
|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA
;
45 writel(csa
, &matrix
->ebicsa
);
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
54 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
56 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
57 AT91_SMC_MODE_EXNW_DISABLE
|
58 #ifdef CONFIG_SYS_NAND_DBW_16
59 AT91_SMC_MODE_DBW_16
|
60 #else /* CONFIG_SYS_NAND_DBW_8 */
63 AT91_SMC_MODE_TDF_CYCLE(2),
66 writel(1 << ATMEL_ID_PIOD
, &pmc
->pcer
);
68 /* Configure RDY/BSY */
69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
71 /* Enable NandFlash */
72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
74 at91_set_A_periph(AT91_PIN_PB4
, 0); /* NANDOE */
75 at91_set_A_periph(AT91_PIN_PB5
, 0); /* NANDWE */
80 vidinfo_t panel_info
= {
84 .vl_sync
= ATMEL_LCDC_INVLINE_INVERTED
|
85 ATMEL_LCDC_INVFRAME_INVERTED
,
90 .vl_right_margin
= 33,
94 .mmio
= ATMEL_BASE_LCDC
,
99 at91_set_gpio_value(AT91_PIN_PA30
, 0); /* power up */
102 void lcd_disable(void)
104 at91_set_gpio_value(AT91_PIN_PA30
, 1); /* power down */
106 static void at91sam9rlek_lcd_hw_init(void)
108 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
110 at91_set_B_periph(AT91_PIN_PC1
, 0); /* LCDPWR */
111 at91_set_A_periph(AT91_PIN_PC5
, 0); /* LCDHSYNC */
112 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDDOTCK */
113 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDDEN */
114 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDCC */
115 at91_set_B_periph(AT91_PIN_PC9
, 0); /* LCDD3 */
116 at91_set_B_periph(AT91_PIN_PC10
, 0); /* LCDD4 */
117 at91_set_B_periph(AT91_PIN_PC11
, 0); /* LCDD5 */
118 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD6 */
119 at91_set_B_periph(AT91_PIN_PC13
, 0); /* LCDD7 */
120 at91_set_B_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
121 at91_set_B_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
122 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD13 */
123 at91_set_B_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
124 at91_set_B_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
125 at91_set_B_periph(AT91_PIN_PC20
, 0); /* LCDD18 */
126 at91_set_B_periph(AT91_PIN_PC21
, 0); /* LCDD19 */
127 at91_set_B_periph(AT91_PIN_PC22
, 0); /* LCDD20 */
128 at91_set_B_periph(AT91_PIN_PC23
, 0); /* LCDD21 */
129 at91_set_B_periph(AT91_PIN_PC24
, 0); /* LCDD22 */
130 at91_set_B_periph(AT91_PIN_PC25
, 0); /* LCDD23 */
132 writel(1 << ATMEL_ID_LCDC
, &pmc
->pcer
);
135 #ifdef CONFIG_LCD_INFO
139 void lcd_show_board_info(void)
141 ulong dram_size
, nand_size
;
145 lcd_printf ("%s\n", U_BOOT_VERSION
);
146 lcd_printf ("(C) 2008 ATMEL Corp\n");
147 lcd_printf ("at91support@atmel.com\n");
148 lcd_printf ("%s CPU at %s MHz\n",
150 strmhz(temp
, get_cpu_clk_rate()));
153 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
154 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
156 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
157 nand_size
+= nand_info
[i
].size
;
158 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
162 #endif /* CONFIG_LCD_INFO */
165 int board_early_init_f(void)
167 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
169 /* Enable clocks for all PIOs */
170 writel((1 << ATMEL_ID_PIOA
) | (1 << ATMEL_ID_PIOB
) |
171 (1 << ATMEL_ID_PIOC
) | (1 << ATMEL_ID_PIOD
),
179 /* arch number of AT91SAM9RLEK-Board */
180 gd
->bd
->bi_arch_number
= MACH_TYPE_AT91SAM9RLEK
;
181 /* adress of boot parameters */
182 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
184 at91_seriald_hw_init();
185 #ifdef CONFIG_CMD_NAND
186 at91sam9rlek_nand_hw_init();
188 #ifdef CONFIG_HAS_DATAFLASH
189 at91_spi0_hw_init(1 << 0);
192 at91sam9rlek_lcd_hw_init();
199 gd
->ram_size
= get_ram_size(
200 (void *)CONFIG_SYS_SDRAM_BASE
,
201 CONFIG_SYS_SDRAM_SIZE
);