board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Microchip Corporation
   4  *                    Wenyou.Yang <wenyou.yang@microchip.com>
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/atmel_pio4.h>
  12 #include <asm/arch/atmel_mpddrc.h>
  13 #include <asm/arch/atmel_sdhci.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/sama5d2.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static void board_usb_hw_init(void)
  21 {
  22         atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
  23 }
  24
  25 #ifdef CONFIG_BOARD_LATE_INIT
  26 int board_late_init(void)
  27 {
  28 #ifdef CONFIG_DM_VIDEO
  29         at91_video_show_board_info();
  30 #endif
  31         return 0;
  32 }
  33 #endif
  34
  35 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  36 static void board_uart1_hw_init(void)
  37 {
  38         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);        /* URXD1 */
  39         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
  40
  41         at91_periph_clk_enable(ATMEL_ID_UART1);
  42 }
  43
  44 void board_debug_uart_init(void)
  45 {
  46         board_uart1_hw_init();
  47 }
  48 #endif
  49
  50 #ifdef CONFIG_BOARD_EARLY_INIT_F
  51 int board_early_init_f(void)
  52 {
  53 #ifdef CONFIG_DEBUG_UART
  54         debug_uart_init();
  55 #endif
  56
  57         return 0;
  58 }
  59 #endif
  60
  61 int board_init(void)
  62 {
  63         /* address of boot parameters */
  64         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  65
  66 #ifdef CONFIG_CMD_USB
  67         board_usb_hw_init();
  68 #endif
  69
  70         return 0;
  71 }
  72
  73 int dram_init(void)
  74 {
  75         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  76                                     CONFIG_SYS_SDRAM_SIZE);
  77         return 0;
  78 }
  79
  80 #define MAC24AA_MAC_OFFSET      0xfa
  81
  82 #ifdef CONFIG_MISC_INIT_R
  83 int misc_init_r(void)
  84 {
  85 #ifdef CONFIG_I2C_EEPROM
  86         at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  87 #endif
  88         return 0;
  89 }
  90 #endif
  91
  92 /* SPL */
  93 #ifdef CONFIG_SPL_BUILD
  94 void spl_board_init(void)
  95 {
  96 }
  97
  98 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
  99 {
 100         ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 101
 102         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 103                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 104                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 105                     ATMEL_MPDDRC_CR_DIC_DS |
 106                     ATMEL_MPDDRC_CR_ZQ_LONG |
 107                     ATMEL_MPDDRC_CR_NB_8BANKS |
 108                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 109                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 110
 111         ddrc->rtr = 0x511;
 112
 113         ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
 114                       (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
 115                       (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
 116                       (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
 117                       (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
 118                       (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
 119                       (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
 120                       (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
 121
 122         ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
 123                       (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
 124                       (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
 125                       (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
 126
 127         ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
 128                       (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
 129                       (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
 130                       (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
 131                       (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
 132 }
 133
 134 void mem_init(void)
 135 {
 136         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 137         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 138         struct atmel_mpddrc_config ddrc_config;
 139         u32 reg;
 140
 141         ddrc_conf(&ddrc_config);
 142
 143         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 144         writel(AT91_PMC_DDR, &pmc->scer);
 145
 146         reg = readl(&mpddrc->io_calibr);
 147         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 148         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 149         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 150         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
 151         writel(reg, &mpddrc->io_calibr);
 152
 153         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
 154                &mpddrc->rd_data_path);
 155
 156         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 157
 158         writel(0x3, &mpddrc->cal_mr4);
 159         writel(64, &mpddrc->tim_cal);
 160 }
 161
 162 void at91_pmc_init(void)
 163 {
 164         u32 tmp;
 165
 166         /*
 167          * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 168          * so we need to slow down and configure MCKR accordingly.
 169          * This is why we have a special flavor of the switching function.
 170          */
 171         tmp = AT91_PMC_MCKR_PLLADIV_2 |
 172               AT91_PMC_MCKR_MDIV_3 |
 173               AT91_PMC_MCKR_CSS_MAIN;
 174         at91_mck_init_down(tmp);
 175
 176         tmp = AT91_PMC_PLLAR_29 |
 177               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 178               AT91_PMC_PLLXR_MUL(40) |
 179               AT91_PMC_PLLXR_DIV(1);
 180         at91_plla_init(tmp);
 181
 182         tmp = AT91_PMC_MCKR_H32MXDIV |
 183               AT91_PMC_MCKR_PLLADIV_2 |
 184               AT91_PMC_MCKR_MDIV_3 |
 185               AT91_PMC_MCKR_CSS_PLLA;
 186         at91_mck_init(tmp);
 187 }
 188 #endif