2 * Copyright (C) 2012 - 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/arch/at91_rstc.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
18 #include <atmel_lcdc.h>
19 #include <atmel_mci.h>
24 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
25 #include <asm/arch/atmel_usba_udc.h>
28 DECLARE_GLOBAL_DATA_PTR
;
30 /* ------------------------------------------------------------------------- */
32 * Miscelaneous platform dependent initialisations
35 #ifdef CONFIG_NAND_ATMEL
36 void sama5d3xek_nand_hw_init(void)
38 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
40 at91_periph_clk_enable(ATMEL_ID_SMC
);
42 /* Configure SMC CS3 for NAND/SmartMedia */
43 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
44 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
46 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
47 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
49 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
51 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
52 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
53 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
54 AT91_SMC_TIMINGS_NFSEL(1), &smc
->cs
[3].timings
);
55 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
56 AT91_SMC_MODE_EXNW_DISABLE
|
57 #ifdef CONFIG_SYS_NAND_DBW_16
58 AT91_SMC_MODE_DBW_16
|
59 #else /* CONFIG_SYS_NAND_DBW_8 */
62 AT91_SMC_MODE_TDF_CYCLE(3),
68 static void sama5d3xek_usb_hw_init(void)
70 at91_set_pio_output(AT91_PIO_PORTD
, 25, 0);
71 at91_set_pio_output(AT91_PIO_PORTD
, 26, 0);
72 at91_set_pio_output(AT91_PIO_PORTD
, 27, 0);
76 #ifdef CONFIG_GENERIC_ATMEL_MCI
77 static void sama5d3xek_mci_hw_init(void)
81 at91_set_pio_output(AT91_PIO_PORTB
, 10, 0); /* MCI0 Power */
86 vidinfo_t panel_info
= {
90 .vl_sync
= ATMEL_LCDC_INVLINE_NORMAL
| ATMEL_LCDC_INVFRAME_NORMAL
,
95 .vl_right_margin
= 64,
97 .vl_upper_margin
= 22,
98 .vl_lower_margin
= 21,
99 .mmio
= ATMEL_BASE_LCDC
,
102 void lcd_enable(void)
106 void lcd_disable(void)
110 static void sama5d3xek_lcd_hw_init(void)
112 gd
->fb_base
= CONFIG_SAMA5D3_LCD_BASE
;
114 /* The higher 8 bit of LCD is board related */
115 at91_set_c_periph(AT91_PIO_PORTC
, 14, 0); /* LCDD16 */
116 at91_set_c_periph(AT91_PIO_PORTC
, 13, 0); /* LCDD17 */
117 at91_set_c_periph(AT91_PIO_PORTC
, 12, 0); /* LCDD18 */
118 at91_set_c_periph(AT91_PIO_PORTC
, 11, 0); /* LCDD19 */
119 at91_set_c_periph(AT91_PIO_PORTC
, 10, 0); /* LCDD20 */
120 at91_set_c_periph(AT91_PIO_PORTC
, 15, 0); /* LCDD21 */
121 at91_set_c_periph(AT91_PIO_PORTE
, 27, 0); /* LCDD22 */
122 at91_set_c_periph(AT91_PIO_PORTE
, 28, 0); /* LCDD23 */
124 /* Configure lower 16 bit of LCD and enable clock */
128 #ifdef CONFIG_LCD_INFO
132 void lcd_show_board_info(void)
134 ulong dram_size
, nand_size
;
138 lcd_printf("%s\n", U_BOOT_VERSION
);
139 lcd_printf("(C) 2013 ATMEL Corp\n");
140 lcd_printf("at91@atmel.com\n");
141 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
142 strmhz(temp
, get_cpu_clk_rate()));
145 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
146 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
149 #ifdef CONFIG_NAND_ATMEL
150 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
151 nand_size
+= nand_info
[i
].size
;
153 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
154 dram_size
>> 20, nand_size
>> 20);
156 #endif /* CONFIG_LCD_INFO */
157 #endif /* CONFIG_LCD */
159 int board_early_init_f(void)
161 at91_seriald_hw_init();
168 /* adress of boot parameters */
169 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
171 #ifdef CONFIG_NAND_ATMEL
172 sama5d3xek_nand_hw_init();
174 #ifdef CONFIG_CMD_USB
175 sama5d3xek_usb_hw_init();
177 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
180 #ifdef CONFIG_GENERIC_ATMEL_MCI
181 sama5d3xek_mci_hw_init();
183 #ifdef CONFIG_ATMEL_SPI
184 at91_spi0_hw_init(1 << 0);
194 sama5d3xek_lcd_hw_init();
201 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
202 CONFIG_SYS_SDRAM_SIZE
);
206 int board_phy_config(struct phy_device
*phydev
)
209 ksz9021_phy_extended_write(phydev
,
210 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW
, 0x2222);
212 ksz9021_phy_extended_write(phydev
,
213 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW
, 0x2222);
214 /* rx/tx clock delay */
215 ksz9021_phy_extended_write(phydev
,
216 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW
, 0xf2f4);
221 int board_eth_init(bd_t
*bis
)
227 rc
= macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC
, 0x00);
229 rc
= macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC
, 0x00);
231 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
232 usba_udc_probe(&pdata
);
233 #ifdef CONFIG_USB_ETH_RNDIS
234 usb_eth_initialize(bis
);
241 #ifdef CONFIG_GENERIC_ATMEL_MCI
242 int board_mmc_init(bd_t
*bis
)
246 rc
= atmel_mci_init((void *)ATMEL_BASE_MCI0
);
252 /* SPI chip select control */
253 #ifdef CONFIG_ATMEL_SPI
256 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
258 return bus
== 0 && cs
< 4;
261 void spi_cs_activate(struct spi_slave
*slave
)
265 at91_set_pio_output(AT91_PIO_PORTD
, 13, 0);
267 at91_set_pio_output(AT91_PIO_PORTD
, 14, 0);
269 at91_set_pio_output(AT91_PIO_PORTD
, 15, 0);
271 at91_set_pio_output(AT91_PIO_PORTD
, 16, 0);
277 void spi_cs_deactivate(struct spi_slave
*slave
)
281 at91_set_pio_output(AT91_PIO_PORTD
, 13, 1);
283 at91_set_pio_output(AT91_PIO_PORTD
, 14, 1);
285 at91_set_pio_output(AT91_PIO_PORTD
, 15, 1);
287 at91_set_pio_output(AT91_PIO_PORTD
, 16, 1);
292 #endif /* CONFIG_ATMEL_SPI */