board/atmel/sama5d3xek/sama5d3xek.c

   1 /*
   2  * Copyright (C) 2012 - 2013 Atmel Corporation
   3  * Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mmc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/sama5d3_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_pmc.h>
  14 #include <asm/arch/at91_rstc.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/clk.h>
  17 #include <lcd.h>
  18 #include <atmel_lcdc.h>
  19 #include <atmel_mci.h>
  20 #include <phy.h>
  21 #include <micrel.h>
  22 #include <net.h>
  23 #include <netdev.h>
  24 #include <spl.h>
  25 #include <asm/arch/atmel_mpddrc.h>
  26 #include <asm/arch/at91_wdt.h>
  27
  28 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  29 #include <asm/arch/atmel_usba_udc.h>
  30 #endif
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* ------------------------------------------------------------------------- */
  35 /*
  36  * Miscelaneous platform dependent initialisations
  37  */
  38
  39 #ifdef CONFIG_NAND_ATMEL
  40 void sama5d3xek_nand_hw_init(void)
  41 {
  42         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  43
  44         at91_periph_clk_enable(ATMEL_ID_SMC);
  45
  46         /* Configure SMC CS3 for NAND/SmartMedia */
  47         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  48                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  49                &smc->cs[3].setup);
  50         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  51                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  52                &smc->cs[3].pulse);
  53         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  54                &smc->cs[3].cycle);
  55         writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  56                AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  57                AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  58                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  59         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                AT91_SMC_MODE_EXNW_DISABLE |
  61 #ifdef CONFIG_SYS_NAND_DBW_16
  62                AT91_SMC_MODE_DBW_16 |
  63 #else /* CONFIG_SYS_NAND_DBW_8 */
  64                AT91_SMC_MODE_DBW_8 |
  65 #endif
  66                AT91_SMC_MODE_TDF_CYCLE(3),
  67                &smc->cs[3].mode);
  68 }
  69 #endif
  70
  71 #ifndef CONFIG_SYS_NO_FLASH
  72 static void sama5d3xek_nor_hw_init(void)
  73 {
  74         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  75
  76         at91_periph_clk_enable(ATMEL_ID_SMC);
  77
  78         /* Configure SMC CS0 for NOR flash */
  79         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  80                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  81                &smc->cs[0].setup);
  82         writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
  83                AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
  84                &smc->cs[0].pulse);
  85         writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
  86                &smc->cs[0].cycle);
  87         writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
  88                AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
  89                AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
  90                AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
  91         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  92                AT91_SMC_MODE_EXNW_DISABLE |
  93                AT91_SMC_MODE_DBW_16 |
  94                AT91_SMC_MODE_TDF_CYCLE(1),
  95                &smc->cs[0].mode);
  96
  97         /* Address pin (A1 ~ A23) configuration */
  98         at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
  99         at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
 100         at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
 101         at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
 102         at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
 103         at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
 104         at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
 105         at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
 106         at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
 107         at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
 108         at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
 109         at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
 110         at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
 111         at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
 112         at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
 113         at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
 114         at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
 115         at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
 116         at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
 117         at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
 118         at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
 119         at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
 120         at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
 121         /* CS0 pin configuration */
 122         at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
 123 }
 124 #endif
 125
 126 #ifdef CONFIG_CMD_USB
 127 static void sama5d3xek_usb_hw_init(void)
 128 {
 129         at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
 130         at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
 131         at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_GENERIC_ATMEL_MCI
 136 static void sama5d3xek_mci_hw_init(void)
 137 {
 138         at91_mci_hw_init();
 139
 140         at91_set_pio_output(AT91_PIO_PORTB, 10, 0);     /* MCI0 Power */
 141 }
 142 #endif
 143
 144 #ifdef CONFIG_LCD
 145 vidinfo_t panel_info = {
 146         .vl_col = 800,
 147         .vl_row = 480,
 148         .vl_clk = 24000000,
 149         .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
 150         .vl_bpix = LCD_BPP,
 151         .vl_tft = 1,
 152         .vl_hsync_len = 128,
 153         .vl_left_margin = 64,
 154         .vl_right_margin = 64,
 155         .vl_vsync_len = 2,
 156         .vl_upper_margin = 22,
 157         .vl_lower_margin = 21,
 158         .mmio = ATMEL_BASE_LCDC,
 159 };
 160
 161 void lcd_enable(void)
 162 {
 163 }
 164
 165 void lcd_disable(void)
 166 {
 167 }
 168
 169 static void sama5d3xek_lcd_hw_init(void)
 170 {
 171         gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
 172
 173         /* The higher 8 bit of LCD is board related */
 174         at91_set_c_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD16 */
 175         at91_set_c_periph(AT91_PIO_PORTC, 13, 0);       /* LCDD17 */
 176         at91_set_c_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD18 */
 177         at91_set_c_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD19 */
 178         at91_set_c_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD20 */
 179         at91_set_c_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD21 */
 180         at91_set_c_periph(AT91_PIO_PORTE, 27, 0);       /* LCDD22 */
 181         at91_set_c_periph(AT91_PIO_PORTE, 28, 0);       /* LCDD23 */
 182
 183         /* Configure lower 16 bit of LCD and enable clock */
 184         at91_lcd_hw_init();
 185 }
 186
 187 #ifdef CONFIG_LCD_INFO
 188 #include <nand.h>
 189 #include <version.h>
 190
 191 void lcd_show_board_info(void)
 192 {
 193         ulong dram_size;
 194         uint64_t nand_size;
 195         int i;
 196         char temp[32];
 197
 198         lcd_printf("%s\n", U_BOOT_VERSION);
 199         lcd_printf("(C) 2013 ATMEL Corp\n");
 200         lcd_printf("at91@atmel.com\n");
 201         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 202                    strmhz(temp, get_cpu_clk_rate()));
 203
 204         dram_size = 0;
 205         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 206                 dram_size += gd->bd->bi_dram[i].size;
 207
 208         nand_size = 0;
 209 #ifdef CONFIG_NAND_ATMEL
 210         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 211                 nand_size += nand_info[i].size;
 212 #endif
 213         lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 214                    dram_size >> 20, nand_size >> 20);
 215 }
 216 #endif /* CONFIG_LCD_INFO */
 217 #endif /* CONFIG_LCD */
 218
 219 int board_early_init_f(void)
 220 {
 221         at91_periph_clk_enable(ATMEL_ID_PIOA);
 222         at91_periph_clk_enable(ATMEL_ID_PIOB);
 223         at91_periph_clk_enable(ATMEL_ID_PIOC);
 224         at91_periph_clk_enable(ATMEL_ID_PIOD);
 225         at91_periph_clk_enable(ATMEL_ID_PIOE);
 226
 227         at91_seriald_hw_init();
 228
 229         return 0;
 230 }
 231
 232 int board_init(void)
 233 {
 234         /* adress of boot parameters */
 235         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 236
 237 #ifdef CONFIG_NAND_ATMEL
 238         sama5d3xek_nand_hw_init();
 239 #endif
 240 #ifndef CONFIG_SYS_NO_FLASH
 241         sama5d3xek_nor_hw_init();
 242 #endif
 243 #ifdef CONFIG_CMD_USB
 244         sama5d3xek_usb_hw_init();
 245 #endif
 246 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 247         at91_udp_hw_init();
 248 #endif
 249 #ifdef CONFIG_GENERIC_ATMEL_MCI
 250         sama5d3xek_mci_hw_init();
 251 #endif
 252 #ifdef CONFIG_ATMEL_SPI
 253         at91_spi0_hw_init(1 << 0);
 254 #endif
 255 #ifdef CONFIG_MACB
 256         if (has_emac())
 257                 at91_macb_hw_init();
 258         if (has_gmac())
 259                 at91_gmac_hw_init();
 260 #endif
 261 #ifdef CONFIG_LCD
 262         if (has_lcdc())
 263                 sama5d3xek_lcd_hw_init();
 264 #endif
 265         return 0;
 266 }
 267
 268 int dram_init(void)
 269 {
 270         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 271                                     CONFIG_SYS_SDRAM_SIZE);
 272         return 0;
 273 }
 274
 275 int board_phy_config(struct phy_device *phydev)
 276 {
 277         /* board specific timings for GMAC */
 278         if (has_gmac()) {
 279                 /* rx data delay */
 280                 ksz9021_phy_extended_write(phydev,
 281                                            MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
 282                                            0x2222);
 283                 /* tx data delay */
 284                 ksz9021_phy_extended_write(phydev,
 285                                            MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
 286                                            0x2222);
 287                 /* rx/tx clock delay */
 288                 ksz9021_phy_extended_write(phydev,
 289                                            MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
 290                                            0xf2f4);
 291         }
 292
 293         /* always run the PHY's config routine */
 294         if (phydev->drv->config)
 295                 return phydev->drv->config(phydev);
 296
 297         return 0;
 298 }
 299
 300 int board_eth_init(bd_t *bis)
 301 {
 302         int rc = 0;
 303
 304 #ifdef CONFIG_MACB
 305         if (has_emac())
 306                 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 307         if (has_gmac())
 308                 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
 309 #endif
 310 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 311         usba_udc_probe(&pdata);
 312 #ifdef CONFIG_USB_ETH_RNDIS
 313         usb_eth_initialize(bis);
 314 #endif
 315 #endif
 316
 317         return rc;
 318 }
 319
 320 #ifdef CONFIG_GENERIC_ATMEL_MCI
 321 int board_mmc_init(bd_t *bis)
 322 {
 323         int rc = 0;
 324
 325         rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
 326
 327         return rc;
 328 }
 329 #endif
 330
 331 /* SPI chip select control */
 332 #ifdef CONFIG_ATMEL_SPI
 333 #include <spi.h>
 334
 335 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 336 {
 337         return bus == 0 && cs < 4;
 338 }
 339
 340 void spi_cs_activate(struct spi_slave *slave)
 341 {
 342         switch (slave->cs) {
 343         case 0:
 344                 at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
 345         case 1:
 346                 at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
 347         case 2:
 348                 at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
 349         case 3:
 350                 at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
 351         default:
 352                 break;
 353         }
 354 }
 355
 356 void spi_cs_deactivate(struct spi_slave *slave)
 357 {
 358         switch (slave->cs) {
 359         case 0:
 360                 at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
 361         case 1:
 362                 at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
 363         case 2:
 364                 at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
 365         case 3:
 366                 at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
 367         default:
 368                 break;
 369         }
 370 }
 371 #endif /* CONFIG_ATMEL_SPI */
 372
 373 /* SPL */
 374 #ifdef CONFIG_SPL_BUILD
 375 void spl_board_init(void)
 376 {
 377 #ifdef CONFIG_SYS_USE_MMC
 378         sama5d3xek_mci_hw_init();
 379 #elif CONFIG_SYS_USE_NANDFLASH
 380         sama5d3xek_nand_hw_init();
 381 #elif CONFIG_SYS_USE_SERIALFLASH
 382         at91_spi0_hw_init(1 << 0);
 383 #endif
 384 }
 385
 386 static void ddr2_conf(struct atmel_mpddr *ddr2)
 387 {
 388         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 389
 390         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 391                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 392                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 393                     ATMEL_MPDDRC_CR_ENRDM_ON |
 394                     ATMEL_MPDDRC_CR_NB_8BANKS |
 395                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 396                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 397                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 398         /*
 399          * As the DDR2-SDRAm device requires a refresh time is 7.8125us
 400          * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
 401          */
 402         ddr2->rtr = 0x411;
 403
 404         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 405                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 406                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 407                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 408                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 409                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 410                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 411                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 412
 413         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 414                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 415                       28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 416                       26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 417
 418         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 419                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 420                       2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 421                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 422                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 423 }
 424
 425 void mem_init(void)
 426 {
 427         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 428         struct atmel_mpddr ddr2;
 429
 430         ddr2_conf(&ddr2);
 431
 432         /* enable MPDDR clock */
 433         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 434         writel(0x4, &pmc->scer);
 435
 436         /* DDRAM2 Controller initialize */
 437         ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
 438 }
 439
 440 void at91_pmc_init(void)
 441 {
 442         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 443         u32 tmp;
 444
 445         tmp = AT91_PMC_PLLAR_29 |
 446               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 447               AT91_PMC_PLLXR_MUL(43) |
 448               AT91_PMC_PLLXR_DIV(1);
 449         at91_plla_init(tmp);
 450
 451         writel(0x3 << 8, &pmc->pllicpr);
 452
 453         tmp = AT91_PMC_MCKR_MDIV_4 |
 454               AT91_PMC_MCKR_CSS_PLLA;
 455         at91_mck_init(tmp);
 456 }
 457 #endif