2 * Copyright (C) 2012 - 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/arch/at91_rstc.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
18 #include <atmel_lcdc.h>
19 #include <atmel_mci.h>
24 #include <asm/arch/atmel_mpddrc.h>
25 #include <asm/arch/at91_wdt.h>
27 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
28 #include <asm/arch/atmel_usba_udc.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 /* ------------------------------------------------------------------------- */
35 * Miscelaneous platform dependent initialisations
38 #ifdef CONFIG_NAND_ATMEL
39 void sama5d3xek_nand_hw_init(void)
41 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
43 at91_periph_clk_enable(ATMEL_ID_SMC
);
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
49 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
52 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
54 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
55 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
56 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
57 AT91_SMC_TIMINGS_NFSEL(1), &smc
->cs
[3].timings
);
58 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
59 AT91_SMC_MODE_EXNW_DISABLE
|
60 #ifdef CONFIG_SYS_NAND_DBW_16
61 AT91_SMC_MODE_DBW_16
|
62 #else /* CONFIG_SYS_NAND_DBW_8 */
65 AT91_SMC_MODE_TDF_CYCLE(3),
70 #ifndef CONFIG_SYS_NO_FLASH
71 static void sama5d3xek_nor_hw_init(void)
73 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
75 at91_periph_clk_enable(ATMEL_ID_SMC
);
77 /* Configure SMC CS0 for NOR flash */
78 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
79 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
81 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
82 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
84 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
86 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
87 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
88 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
89 AT91_SMC_TIMINGS_NFSEL(0), &smc
->cs
[0].timings
);
90 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
91 AT91_SMC_MODE_EXNW_DISABLE
|
92 AT91_SMC_MODE_DBW_16
|
93 AT91_SMC_MODE_TDF_CYCLE(1),
96 /* Address pin (A1 ~ A23) configuration */
97 at91_set_a_periph(AT91_PIO_PORTE
, 1, 0);
98 at91_set_a_periph(AT91_PIO_PORTE
, 2, 0);
99 at91_set_a_periph(AT91_PIO_PORTE
, 3, 0);
100 at91_set_a_periph(AT91_PIO_PORTE
, 4, 0);
101 at91_set_a_periph(AT91_PIO_PORTE
, 5, 0);
102 at91_set_a_periph(AT91_PIO_PORTE
, 6, 0);
103 at91_set_a_periph(AT91_PIO_PORTE
, 7, 0);
104 at91_set_a_periph(AT91_PIO_PORTE
, 8, 0);
105 at91_set_a_periph(AT91_PIO_PORTE
, 9, 0);
106 at91_set_a_periph(AT91_PIO_PORTE
, 10, 0);
107 at91_set_a_periph(AT91_PIO_PORTE
, 11, 0);
108 at91_set_a_periph(AT91_PIO_PORTE
, 12, 0);
109 at91_set_a_periph(AT91_PIO_PORTE
, 13, 0);
110 at91_set_a_periph(AT91_PIO_PORTE
, 14, 0);
111 at91_set_a_periph(AT91_PIO_PORTE
, 15, 0);
112 at91_set_a_periph(AT91_PIO_PORTE
, 16, 0);
113 at91_set_a_periph(AT91_PIO_PORTE
, 17, 0);
114 at91_set_a_periph(AT91_PIO_PORTE
, 18, 0);
115 at91_set_a_periph(AT91_PIO_PORTE
, 19, 0);
116 at91_set_a_periph(AT91_PIO_PORTE
, 20, 0);
117 at91_set_a_periph(AT91_PIO_PORTE
, 21, 0);
118 at91_set_a_periph(AT91_PIO_PORTE
, 22, 0);
119 at91_set_a_periph(AT91_PIO_PORTE
, 23, 0);
120 /* CS0 pin configuration */
121 at91_set_a_periph(AT91_PIO_PORTE
, 26, 0);
125 #ifdef CONFIG_CMD_USB
126 static void sama5d3xek_usb_hw_init(void)
128 at91_set_pio_output(AT91_PIO_PORTD
, 25, 0);
129 at91_set_pio_output(AT91_PIO_PORTD
, 26, 0);
130 at91_set_pio_output(AT91_PIO_PORTD
, 27, 0);
134 #ifdef CONFIG_GENERIC_ATMEL_MCI
135 static void sama5d3xek_mci_hw_init(void)
139 at91_set_pio_output(AT91_PIO_PORTB
, 10, 0); /* MCI0 Power */
144 vidinfo_t panel_info
= {
148 .vl_sync
= ATMEL_LCDC_INVLINE_NORMAL
| ATMEL_LCDC_INVFRAME_NORMAL
,
152 .vl_left_margin
= 64,
153 .vl_right_margin
= 64,
155 .vl_upper_margin
= 22,
156 .vl_lower_margin
= 21,
157 .mmio
= ATMEL_BASE_LCDC
,
160 void lcd_enable(void)
164 void lcd_disable(void)
168 static void sama5d3xek_lcd_hw_init(void)
170 gd
->fb_base
= CONFIG_SAMA5D3_LCD_BASE
;
172 /* The higher 8 bit of LCD is board related */
173 at91_set_c_periph(AT91_PIO_PORTC
, 14, 0); /* LCDD16 */
174 at91_set_c_periph(AT91_PIO_PORTC
, 13, 0); /* LCDD17 */
175 at91_set_c_periph(AT91_PIO_PORTC
, 12, 0); /* LCDD18 */
176 at91_set_c_periph(AT91_PIO_PORTC
, 11, 0); /* LCDD19 */
177 at91_set_c_periph(AT91_PIO_PORTC
, 10, 0); /* LCDD20 */
178 at91_set_c_periph(AT91_PIO_PORTC
, 15, 0); /* LCDD21 */
179 at91_set_c_periph(AT91_PIO_PORTE
, 27, 0); /* LCDD22 */
180 at91_set_c_periph(AT91_PIO_PORTE
, 28, 0); /* LCDD23 */
182 /* Configure lower 16 bit of LCD and enable clock */
186 #ifdef CONFIG_LCD_INFO
190 void lcd_show_board_info(void)
197 lcd_printf("%s\n", U_BOOT_VERSION
);
198 lcd_printf("(C) 2013 ATMEL Corp\n");
199 lcd_printf("at91@atmel.com\n");
200 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
201 strmhz(temp
, get_cpu_clk_rate()));
204 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
205 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
208 #ifdef CONFIG_NAND_ATMEL
209 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
210 nand_size
+= nand_info
[i
].size
;
212 lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
213 dram_size
>> 20, nand_size
>> 20);
215 #endif /* CONFIG_LCD_INFO */
216 #endif /* CONFIG_LCD */
218 int board_early_init_f(void)
220 at91_periph_clk_enable(ATMEL_ID_PIOA
);
221 at91_periph_clk_enable(ATMEL_ID_PIOB
);
222 at91_periph_clk_enable(ATMEL_ID_PIOC
);
223 at91_periph_clk_enable(ATMEL_ID_PIOD
);
224 at91_periph_clk_enable(ATMEL_ID_PIOE
);
226 at91_seriald_hw_init();
233 /* adress of boot parameters */
234 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
236 #ifdef CONFIG_NAND_ATMEL
237 sama5d3xek_nand_hw_init();
239 #ifndef CONFIG_SYS_NO_FLASH
240 sama5d3xek_nor_hw_init();
242 #ifdef CONFIG_CMD_USB
243 sama5d3xek_usb_hw_init();
245 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
248 #ifdef CONFIG_GENERIC_ATMEL_MCI
249 sama5d3xek_mci_hw_init();
251 #ifdef CONFIG_ATMEL_SPI
252 at91_spi0_hw_init(1 << 0);
262 sama5d3xek_lcd_hw_init();
269 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
270 CONFIG_SYS_SDRAM_SIZE
);
274 int board_phy_config(struct phy_device
*phydev
)
277 ksz9021_phy_extended_write(phydev
,
278 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW
, 0x2222);
280 ksz9021_phy_extended_write(phydev
,
281 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW
, 0x2222);
282 /* rx/tx clock delay */
283 ksz9021_phy_extended_write(phydev
,
284 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW
, 0xf2f4);
289 int board_eth_init(bd_t
*bis
)
295 rc
= macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC
, 0x00);
297 rc
= macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC
, 0x00);
299 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
300 usba_udc_probe(&pdata
);
301 #ifdef CONFIG_USB_ETH_RNDIS
302 usb_eth_initialize(bis
);
309 #ifdef CONFIG_GENERIC_ATMEL_MCI
310 int board_mmc_init(bd_t
*bis
)
314 rc
= atmel_mci_init((void *)ATMEL_BASE_MCI0
);
320 /* SPI chip select control */
321 #ifdef CONFIG_ATMEL_SPI
324 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
326 return bus
== 0 && cs
< 4;
329 void spi_cs_activate(struct spi_slave
*slave
)
333 at91_set_pio_output(AT91_PIO_PORTD
, 13, 0);
335 at91_set_pio_output(AT91_PIO_PORTD
, 14, 0);
337 at91_set_pio_output(AT91_PIO_PORTD
, 15, 0);
339 at91_set_pio_output(AT91_PIO_PORTD
, 16, 0);
345 void spi_cs_deactivate(struct spi_slave
*slave
)
349 at91_set_pio_output(AT91_PIO_PORTD
, 13, 1);
351 at91_set_pio_output(AT91_PIO_PORTD
, 14, 1);
353 at91_set_pio_output(AT91_PIO_PORTD
, 15, 1);
355 at91_set_pio_output(AT91_PIO_PORTD
, 16, 1);
360 #endif /* CONFIG_ATMEL_SPI */
363 #ifdef CONFIG_SPL_BUILD
364 void spl_board_init(void)
366 #ifdef CONFIG_SYS_USE_MMC
367 sama5d3xek_mci_hw_init();
368 #elif CONFIG_SYS_USE_NANDFLASH
369 sama5d3xek_nand_hw_init();
370 #elif CONFIG_SYS_USE_SERIALFLASH
371 at91_spi0_hw_init(1 << 0);
375 static void ddr2_conf(struct atmel_mpddr
*ddr2
)
377 ddr2
->md
= (ATMEL_MPDDRC_MD_DBW_32_BITS
| ATMEL_MPDDRC_MD_DDR2_SDRAM
);
379 ddr2
->cr
= (ATMEL_MPDDRC_CR_NC_COL_10
|
380 ATMEL_MPDDRC_CR_NR_ROW_14
|
381 ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
382 ATMEL_MPDDRC_CR_ENRDM_ON
|
383 ATMEL_MPDDRC_CR_NB_8BANKS
|
384 ATMEL_MPDDRC_CR_NDQS_DISABLED
|
385 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
|
386 ATMEL_MPDDRC_CR_UNAL_SUPPORTED
);
388 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
389 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
393 ddr2
->tpr0
= (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
394 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
395 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
396 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
397 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
398 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
399 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
400 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
402 ddr2
->tpr1
= (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
403 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
404 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
405 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
407 ddr2
->tpr2
= (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET
|
408 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
409 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
410 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
411 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
416 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
417 struct atmel_mpddr ddr2
;
421 /* enable MPDDR clock */
422 at91_periph_clk_enable(ATMEL_ID_MPDDRC
);
423 writel(0x4, &pmc
->scer
);
425 /* DDRAM2 Controller initialize */
426 ddr2_init(ATMEL_BASE_DDRCS
, &ddr2
);
429 void at91_pmc_init(void)
431 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
434 tmp
= AT91_PMC_PLLAR_29
|
435 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
436 AT91_PMC_PLLXR_MUL(43) |
437 AT91_PMC_PLLXR_DIV(1);
440 writel(0x3 << 8, &pmc
->pllicpr
);
442 tmp
= AT91_PMC_MCKR_MDIV_4
|
443 AT91_PMC_MCKR_CSS_PLLA
;