board/atmel/sama5d3xek/sama5d3xek.c

   1 /*
   2  * Copyright (C) 2012 - 2013 Atmel Corporation
   3  * Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mmc.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/sama5d3_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_pmc.h>
  14 #include <asm/arch/at91_rstc.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/clk.h>
  17 #include <lcd.h>
  18 #include <atmel_lcdc.h>
  19 #include <atmel_mci.h>
  20 #include <micrel.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23
  24 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  25 #include <asm/arch/atmel_usba_udc.h>
  26 #endif
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_NAND_ATMEL
  36 void sama5d3xek_nand_hw_init(void)
  37 {
  38         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  39
  40         at91_periph_clk_enable(ATMEL_ID_SMC);
  41
  42         /* Configure SMC CS3 for NAND/SmartMedia */
  43         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  44                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  45                &smc->cs[3].setup);
  46         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  47                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  48                &smc->cs[3].pulse);
  49         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  50                &smc->cs[3].cycle);
  51         writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  52                AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  53                AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  54                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  55         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  56                AT91_SMC_MODE_EXNW_DISABLE |
  57 #ifdef CONFIG_SYS_NAND_DBW_16
  58                AT91_SMC_MODE_DBW_16 |
  59 #else /* CONFIG_SYS_NAND_DBW_8 */
  60                AT91_SMC_MODE_DBW_8 |
  61 #endif
  62                AT91_SMC_MODE_TDF_CYCLE(3),
  63                &smc->cs[3].mode);
  64 }
  65 #endif
  66
  67 #ifdef CONFIG_CMD_USB
  68 static void sama5d3xek_usb_hw_init(void)
  69 {
  70         at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
  71         at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
  72         at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
  73 }
  74 #endif
  75
  76 #ifdef CONFIG_GENERIC_ATMEL_MCI
  77 static void sama5d3xek_mci_hw_init(void)
  78 {
  79         at91_mci_hw_init();
  80
  81         at91_set_pio_output(AT91_PIO_PORTB, 10, 0);     /* MCI0 Power */
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_LCD
  86 vidinfo_t panel_info = {
  87         .vl_col = 800,
  88         .vl_row = 480,
  89         .vl_clk = 24000000,
  90         .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
  91         .vl_bpix = LCD_BPP,
  92         .vl_tft = 1,
  93         .vl_hsync_len = 128,
  94         .vl_left_margin = 64,
  95         .vl_right_margin = 64,
  96         .vl_vsync_len = 2,
  97         .vl_upper_margin = 22,
  98         .vl_lower_margin = 21,
  99         .mmio = ATMEL_BASE_LCDC,
 100 };
 101
 102 void lcd_enable(void)
 103 {
 104 }
 105
 106 void lcd_disable(void)
 107 {
 108 }
 109
 110 static void sama5d3xek_lcd_hw_init(void)
 111 {
 112         gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
 113
 114         /* The higher 8 bit of LCD is board related */
 115         at91_set_c_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD16 */
 116         at91_set_c_periph(AT91_PIO_PORTC, 13, 0);       /* LCDD17 */
 117         at91_set_c_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD18 */
 118         at91_set_c_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD19 */
 119         at91_set_c_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD20 */
 120         at91_set_c_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD21 */
 121         at91_set_c_periph(AT91_PIO_PORTE, 27, 0);       /* LCDD22 */
 122         at91_set_c_periph(AT91_PIO_PORTE, 28, 0);       /* LCDD23 */
 123
 124         /* Configure lower 16 bit of LCD and enable clock */
 125         at91_lcd_hw_init();
 126 }
 127
 128 #ifdef CONFIG_LCD_INFO
 129 #include <nand.h>
 130 #include <version.h>
 131
 132 void lcd_show_board_info(void)
 133 {
 134         ulong dram_size, nand_size;
 135         int i;
 136         char temp[32];
 137
 138         lcd_printf("%s\n", U_BOOT_VERSION);
 139         lcd_printf("(C) 2013 ATMEL Corp\n");
 140         lcd_printf("at91@atmel.com\n");
 141         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 142                    strmhz(temp, get_cpu_clk_rate()));
 143
 144         dram_size = 0;
 145         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 146                 dram_size += gd->bd->bi_dram[i].size;
 147
 148         nand_size = 0;
 149 #ifdef CONFIG_NAND_ATMEL
 150         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 151                 nand_size += nand_info[i].size;
 152 #endif
 153         lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 154                    dram_size >> 20, nand_size >> 20);
 155 }
 156 #endif /* CONFIG_LCD_INFO */
 157 #endif /* CONFIG_LCD */
 158
 159 int board_early_init_f(void)
 160 {
 161         at91_seriald_hw_init();
 162
 163         return 0;
 164 }
 165
 166 int board_init(void)
 167 {
 168         /* adress of boot parameters */
 169         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 170
 171 #ifdef CONFIG_NAND_ATMEL
 172         sama5d3xek_nand_hw_init();
 173 #endif
 174 #ifdef CONFIG_CMD_USB
 175         sama5d3xek_usb_hw_init();
 176 #endif
 177 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 178         at91_udp_hw_init();
 179 #endif
 180 #ifdef CONFIG_GENERIC_ATMEL_MCI
 181         sama5d3xek_mci_hw_init();
 182 #endif
 183 #ifdef CONFIG_ATMEL_SPI
 184         at91_spi0_hw_init(1 << 0);
 185 #endif
 186 #ifdef CONFIG_MACB
 187         if (has_emac())
 188                 at91_macb_hw_init();
 189         if (has_gmac())
 190                 at91_gmac_hw_init();
 191 #endif
 192 #ifdef CONFIG_LCD
 193         if (has_lcdc())
 194                 sama5d3xek_lcd_hw_init();
 195 #endif
 196         return 0;
 197 }
 198
 199 int dram_init(void)
 200 {
 201         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 202                                     CONFIG_SYS_SDRAM_SIZE);
 203         return 0;
 204 }
 205
 206 int board_phy_config(struct phy_device *phydev)
 207 {
 208         /* rx data delay */
 209         ksz9021_phy_extended_write(phydev,
 210                                    MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
 211         /* tx data delay */
 212         ksz9021_phy_extended_write(phydev,
 213                                    MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
 214         /* rx/tx clock delay */
 215         ksz9021_phy_extended_write(phydev,
 216                                    MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
 217
 218         return 0;
 219 }
 220
 221 int board_eth_init(bd_t *bis)
 222 {
 223         int rc = 0;
 224
 225 #ifdef CONFIG_MACB
 226         if (has_emac())
 227                 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 228         if (has_gmac())
 229                 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
 230 #endif
 231 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 232         usba_udc_probe(&pdata);
 233 #ifdef CONFIG_USB_ETH_RNDIS
 234         usb_eth_initialize(bis);
 235 #endif
 236 #endif
 237
 238         return rc;
 239 }
 240
 241 #ifdef CONFIG_GENERIC_ATMEL_MCI
 242 int board_mmc_init(bd_t *bis)
 243 {
 244         int rc = 0;
 245
 246         rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
 247
 248         return rc;
 249 }
 250 #endif
 251
 252 /* SPI chip select control */
 253 #ifdef CONFIG_ATMEL_SPI
 254 #include <spi.h>
 255
 256 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 257 {
 258         return bus == 0 && cs < 4;
 259 }
 260
 261 void spi_cs_activate(struct spi_slave *slave)
 262 {
 263         switch (slave->cs) {
 264         case 0:
 265                 at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
 266         case 1:
 267                 at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
 268         case 2:
 269                 at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
 270         case 3:
 271                 at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
 272         default:
 273                 break;
 274         }
 275 }
 276
 277 void spi_cs_deactivate(struct spi_slave *slave)
 278 {
 279         switch (slave->cs) {
 280         case 0:
 281                 at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
 282         case 1:
 283                 at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
 284         case 2:
 285                 at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
 286         case 3:
 287                 at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
 288         default:
 289                 break;
 290         }
 291 }
 292 #endif /* CONFIG_ATMEL_SPI */