2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014, Bachmann electronic GmbH
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/sata.h>
17 #include <asm/imx-common/mxc_i2c.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/sys_proto.h>
22 #include <fsl_esdhc.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
43 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
47 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51 gd
->ram_size
= imx_ddr_size();
56 static iomux_v3_cfg_t
const uart1_pads
[] = {
57 MX6_PAD_CSI0_DAT10__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
58 MX6_PAD_CSI0_DAT11__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
61 static void setup_iomux_uart(void)
63 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
66 static iomux_v3_cfg_t
const enet_pads
[] = {
67 MX6_PAD_KEY_ROW1__ENET_COL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
68 MX6_PAD_KEY_COL3__ENET_CRS
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
69 MX6_PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
70 MX6_PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
71 MX6_PAD_GPIO_16__ENET_REF_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
72 MX6_PAD_GPIO_18__ENET_RX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
73 MX6_PAD_ENET_RXD0__ENET_RX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
74 MX6_PAD_ENET_RXD1__ENET_RX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
75 MX6_PAD_KEY_COL2__ENET_RX_DATA2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
76 MX6_PAD_KEY_COL0__ENET_RX_DATA3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
77 MX6_PAD_ENET_CRS_DV__ENET_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
78 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
79 MX6_PAD_ENET_TXD0__ENET_TX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
80 MX6_PAD_ENET_TXD1__ENET_TX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
81 MX6_PAD_KEY_ROW2__ENET_TX_DATA2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
82 MX6_PAD_KEY_ROW0__ENET_TX_DATA3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
83 MX6_PAD_ENET_TX_EN__ENET_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
86 static void setup_iomux_enet(void)
88 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
91 static iomux_v3_cfg_t
const ecspi1_pads
[] = {
92 MX6_PAD_DISP0_DAT3__ECSPI3_SS0
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
93 MX6_PAD_DISP0_DAT4__ECSPI3_SS1
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
94 MX6_PAD_DISP0_DAT2__ECSPI3_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
95 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
96 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
99 static void setup_iomux_spi(void)
101 imx_iomux_v3_setup_multiple_pads(ecspi1_pads
, ARRAY_SIZE(ecspi1_pads
));
104 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
106 return (bus
== 2 && cs
== 0) ? (IMX_GPIO_NR(1, 3)) : -1;
109 static iomux_v3_cfg_t
const feature_pads
[] = {
111 MX6_PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN
),
114 MX6_PAD_GPIO_19__GPIO4_IO05
| MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP
),
117 static void setup_iomux_features(void)
119 imx_iomux_v3_setup_multiple_pads(feature_pads
,
120 ARRAY_SIZE(feature_pads
));
123 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
126 static struct i2c_pads_info i2c_pad_info1
= {
128 .i2c_mode
= MX6_PAD_EIM_EB2__I2C2_SCL
| PC
,
129 .gpio_mode
= MX6_PAD_EIM_EB2__GPIO2_IO30
| PC
,
130 .gp
= IMX_GPIO_NR(2, 30)
133 .i2c_mode
= MX6_PAD_EIM_D16__I2C2_SDA
| PC
,
134 .gpio_mode
= MX6_PAD_EIM_D16__GPIO3_IO16
| PC
,
135 .gp
= IMX_GPIO_NR(3, 16)
139 /* I2C3 - IO expander */
140 static struct i2c_pads_info i2c_pad_info2
= {
142 .i2c_mode
= MX6_PAD_EIM_D17__I2C3_SCL
| PC
,
143 .gpio_mode
= MX6_PAD_EIM_D17__GPIO3_IO17
| PC
,
144 .gp
= IMX_GPIO_NR(3, 17)
147 .i2c_mode
= MX6_PAD_EIM_D18__I2C3_SDA
| PC
,
148 .gpio_mode
= MX6_PAD_EIM_D18__GPIO3_IO18
| PC
,
149 .gp
= IMX_GPIO_NR(3, 18)
153 static void setup_iomux_i2c(void)
155 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
156 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info2
);
159 static void ccgr_init(void)
161 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
163 writel(0x00C03F3F, &ccm
->CCGR0
);
164 writel(0x0030FC33, &ccm
->CCGR1
);
165 writel(0x0FFFC000, &ccm
->CCGR2
);
166 writel(0x3FF00000, &ccm
->CCGR3
);
167 writel(0x00FFF300, &ccm
->CCGR4
);
168 writel(0x0F0000C3, &ccm
->CCGR5
);
169 writel(0x000003FF, &ccm
->CCGR6
);
172 static void gpr_init(void)
174 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
176 /* enable AXI cache for VDOA/VPU/IPU */
177 writel(0xF00000CF, &iomux
->gpr
[4]);
178 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
179 writel(0x007F007F, &iomux
->gpr
[6]);
180 writel(0x007F007F, &iomux
->gpr
[7]);
183 int board_early_init_f(void)
191 setup_iomux_features();
196 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
197 MX6_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
198 MX6_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
199 MX6_PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
200 MX6_PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
201 MX6_PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
202 MX6_PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
203 MX6_PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
204 MX6_PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
205 MX6_PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
206 MX6_PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
207 MX6_PAD_SD3_RST__SD3_RESET
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
210 iomux_v3_cfg_t
const usdhc4_pads
[] = {
211 MX6_PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
212 MX6_PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
213 MX6_PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
214 MX6_PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
215 MX6_PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
216 MX6_PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
219 int board_mmc_getcd(struct mmc
*mmc
)
221 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
224 if (cfg
->esdhc_base
== USDHC3_BASE_ADDR
) {
225 gpio_direction_input(IMX_GPIO_NR(4, 5));
226 ret
= gpio_get_value(IMX_GPIO_NR(4, 5));
228 gpio_direction_input(IMX_GPIO_NR(1, 5));
229 ret
= !gpio_get_value(IMX_GPIO_NR(1, 5));
235 struct fsl_esdhc_cfg usdhc_cfg
[2] = {
240 int board_mmc_init(bd_t
*bis
)
245 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
246 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
248 usdhc_cfg
[0].max_bus_width
= 8;
249 usdhc_cfg
[1].max_bus_width
= 4;
251 for (index
= 0; index
< CONFIG_SYS_FSL_USDHC_NUM
; ++index
) {
254 imx_iomux_v3_setup_multiple_pads(
255 usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
258 imx_iomux_v3_setup_multiple_pads(
259 usdhc4_pads
, ARRAY_SIZE(usdhc4_pads
));
262 printf("Warning: you configured more USDHC controllers"
263 "(%d) then supported by the board (%d)\n",
264 index
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
268 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[index
]);
276 static void leds_on(void)
278 /* turn on all possible leds connected via GPIO expander */
280 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR
, 0xffff, PCA953X_DIR_OUT
);
281 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR
, 0xffff, 0x0);
284 static void backlight_lcd_off(void)
286 unsigned gpio
= IMX_GPIO_NR(2, 0);
287 gpio_direction_output(gpio
, 0);
289 gpio
= IMX_GPIO_NR(2, 3);
290 gpio_direction_output(gpio
, 0);
293 int board_eth_init(bd_t
*bis
)
295 uint32_t base
= IMX_FEC_BASE
;
296 struct mii_dev
*bus
= NULL
;
297 struct phy_device
*phydev
= NULL
;
302 bus
= fec_get_miibus(base
, -1);
306 /* scan phy 0 and 5 */
307 phydev
= phy_find_by_mask(bus
, 0x21, PHY_INTERFACE_MODE_RGMII
);
313 /* depending on the phy address we can detect our board version */
314 if (phydev
->addr
== 0)
315 setenv("boardver", "");
317 setenv("boardver", "mr");
319 printf("using phy at %d\n", phydev
->addr
);
320 ret
= fec_probe(bis
, -1, base
, bus
, phydev
);
335 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
350 puts("Board: "CONFIG_SYS_BOARD
"\n");
354 #ifdef CONFIG_CMD_BMODE
355 static const struct boot_mode board_boot_modes
[] = {
356 /* 4 bit bus width */
357 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
362 int misc_init_r(void)
364 #ifdef CONFIG_CMD_BMODE
365 add_board_boot_modes(board_boot_modes
);