4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/hardware.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 void balloon3_init_fpga(void);
34 * Miscelaneous platform dependent initialisations
39 /* arch number of vpac270 */
40 gd
->bd
->bi_arch_number
= MACH_TYPE_BALLOON3
;
42 /* adress of boot parameters */
43 gd
->bd
->bi_boot_params
= 0xa0000100;
51 struct serial_device
*default_serial_console(void)
53 return &serial_stuart_device
;
58 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
59 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
60 gd
->bd
->bi_dram
[2].start
= PHYS_SDRAM_3
;
62 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
63 gd
->bd
->bi_dram
[1].size
= PHYS_SDRAM_2_SIZE
;
64 gd
->bd
->bi_dram
[2].size
= PHYS_SDRAM_3_SIZE
;
70 int usb_board_init(void)
72 writel((readl(UHCHR
) | UHCHR_PCPL
| UHCHR_PSPL
) &
73 ~(UHCHR_SSEP0
| UHCHR_SSEP1
| UHCHR_SSEP2
| UHCHR_SSE
),
76 writel(readl(UHCHR
) | UHCHR_FSBIR
, UHCHR
);
78 while (readl(UHCHR
) & UHCHR_FSBIR
)
81 writel(readl(UHCHR
) & ~UHCHR_SSE
, UHCHR
);
82 writel((UHCHIE_UPRIE
| UHCHIE_RWIE
), UHCHIE
);
84 /* Clear any OTG Pin Hold */
85 if (readl(PSSR
) & PSSR_OTGPH
)
86 writel(readl(PSSR
) | PSSR_OTGPH
, PSSR
);
88 writel(readl(UHCRHDA
) & ~(0x200), UHCRHDA
);
89 writel(readl(UHCRHDA
) | 0x100, UHCRHDA
);
91 /* Set port power control mask bits, only 3 ports. */
92 writel(readl(UHCRHDB
) | (0x7<<17), UHCRHDB
);
95 writel(readl(UP2OCR
) | UP2OCR_HXOE
| UP2OCR_HXS
|
96 UP2OCR_DMPDE
| UP2OCR_DPPDE
, UP2OCR
);
101 void usb_board_init_fail(void)
106 void usb_board_stop(void)
108 writel(readl(UHCHR
) | UHCHR_FHR
, UHCHR
);
110 writel(readl(UHCHR
) & ~UHCHR_FHR
, UHCHR
);
112 writel(readl(UHCCOMS
) | 1, UHCCOMS
);
115 writel(readl(CKEN
) & ~CKEN10_USBHOST
, CKEN
);
121 #if defined(CONFIG_FPGA)
122 /* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
123 int fpga_pgm_fn(int nassert
, int nflush
, int cookie
)
130 writel(0x100, GPCR3
);
132 writel(0x100, GPSR3
);
136 /* Check GPIO83 -- INITB */
137 int fpga_init_fn(int cookie
)
139 return !(readl(GPLR2
) & 0x80000);
142 /* Check GPIO84 -- BUSY */
143 int fpga_busy_fn(int cookie
)
145 return !(readl(GPLR2
) & 0x100000);
148 /* Check GPIO111 -- DONE */
149 int fpga_done_fn(int cookie
)
151 return readl(GPLR3
) & 0x8000;
154 /* Configure GPIO104 as GPIO and deassert it */
155 int fpga_pre_config_fn(int cookie
)
157 writel(readl(GAFR3_L
) & ~0x30000, GAFR3_L
);
158 writel(0x100, GPCR3
);
162 /* Configure GPIO104 as nSKTSEL */
163 int fpga_post_config_fn(int cookie
)
165 writel(readl(GAFR3_L
) | 0x10000, GAFR3_L
);
170 int fpga_wr_fn(int nassert_write
, int flush
, int cookie
)
175 writel(0x100, GPCR3
);
177 writel(0x100, GPSR3
);
179 return nassert_write
;
182 /* Write program to the FPGA */
183 int fpga_wdata_fn(uchar data
, int flush
, int cookie
)
185 writeb(data
, 0x10f00000);
189 /* Toggle Clock pin -- NO-OP */
190 int fpga_clk_fn(int assert_clk
, int flush
, int cookie
)
195 /* Toggle ChipSelect pin -- NO-OP */
196 int fpga_cs_fn(int assert_clk
, int flush
, int cookie
)
201 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns
= {
217 Xilinx_desc fpga
= XILINX_XC3S1000_DESC(slave_parallel
,
218 (void *)&balloon3_fpga_fns
, 0);
220 /* Initialize the FPGA */
221 void balloon3_init_fpga(void)
224 fpga_add(fpga_xilinx
, &fpga
);
227 void balloon3_init_fpga(void) {}
228 #endif /* CONFIG_FPGA */