board/balloon3/balloon3.c

   1 /*
   2  * Balloon3 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/pxa.h>
  25 #include <serial.h>
  26 #include <asm/io.h>
  27 #include <spartan3.h>
  28 #include <command.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 void balloon3_init_fpga(void);
  33
  34 /*
  35  * Miscelaneous platform dependent initialisations
  36  */
  37
  38 int board_init(void)
  39 {
  40         /* We have RAM, disable cache */
  41         dcache_disable();
  42         icache_disable();
  43
  44         /* arch number of vpac270 */
  45         gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
  46
  47         /* adress of boot parameters */
  48         gd->bd->bi_boot_params = 0xa0000100;
  49
  50         /* Init the FPGA */
  51         balloon3_init_fpga();
  52
  53         return 0;
  54 }
  55
  56 struct serial_device *default_serial_console(void)
  57 {
  58         return &serial_stuart_device;
  59 }
  60
  61 int dram_init(void)
  62 {
  63         pxa2xx_dram_init();
  64         gd->ram_size = PHYS_SDRAM_1_SIZE;
  65         return 0;
  66 }
  67
  68 void dram_init_banksize(void)
  69 {
  70         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  71         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  72         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  73
  74         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  75         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  76         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  77 }
  78
  79 #ifdef  CONFIG_CMD_USB
  80 int usb_board_init(void)
  81 {
  82         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  83                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  84                 UHCHR);
  85
  86         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  87
  88         while (readl(UHCHR) & UHCHR_FSBIR)
  89                 ;
  90
  91         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  92         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  93
  94         /* Clear any OTG Pin Hold */
  95         if (readl(PSSR) & PSSR_OTGPH)
  96                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  97
  98         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  99         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
 100
 101         /* Set port power control mask bits, only 3 ports. */
 102         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 103
 104         /* enable port 2 */
 105         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
 106                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
 107
 108         return 0;
 109 }
 110
 111 void usb_board_init_fail(void)
 112 {
 113         return;
 114 }
 115
 116 void usb_board_stop(void)
 117 {
 118         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 119         udelay(11);
 120         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 121
 122         writel(readl(UHCCOMS) | 1, UHCCOMS);
 123         udelay(10);
 124
 125         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 126
 127         return;
 128 }
 129 #endif
 130
 131 #if defined(CONFIG_FPGA)
 132 /* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
 133 int fpga_pgm_fn(int nassert, int nflush, int cookie)
 134 {
 135         if (nassert)
 136                 writel(0x80, GPCR3);
 137         else
 138                 writel(0x80, GPSR3);
 139         if (nflush)
 140                 writel(0x100, GPCR3);
 141         else
 142                 writel(0x100, GPSR3);
 143         return nassert;
 144 }
 145
 146 /* Check GPIO83 -- INITB */
 147 int fpga_init_fn(int cookie)
 148 {
 149         return !(readl(GPLR2) & 0x80000);
 150 }
 151
 152 /* Check GPIO84 -- BUSY */
 153 int fpga_busy_fn(int cookie)
 154 {
 155         return !(readl(GPLR2) & 0x100000);
 156 }
 157
 158 /* Check GPIO111 -- DONE */
 159 int fpga_done_fn(int cookie)
 160 {
 161         return readl(GPLR3) & 0x8000;
 162 }
 163
 164 /* Configure GPIO104 as GPIO and deassert it */
 165 int fpga_pre_config_fn(int cookie)
 166 {
 167         writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
 168         writel(0x100, GPCR3);
 169         return 0;
 170 }
 171
 172 /* Configure GPIO104 as nSKTSEL */
 173 int fpga_post_config_fn(int cookie)
 174 {
 175         writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
 176         return 0;
 177 }
 178
 179 /* Toggle RDnWR */
 180 int fpga_wr_fn(int nassert_write, int flush, int cookie)
 181 {
 182         udelay(1000);
 183
 184         if (nassert_write)
 185                 writel(0x100, GPCR3);
 186         else
 187                 writel(0x100, GPSR3);
 188
 189         return nassert_write;
 190 }
 191
 192 /* Write program to the FPGA */
 193 int fpga_wdata_fn(uchar data, int flush, int cookie)
 194 {
 195         writeb(data, 0x10f00000);
 196         return 0;
 197 }
 198
 199 /* Toggle Clock pin -- NO-OP */
 200 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 201 {
 202         return assert_clk;
 203 }
 204
 205 /* Toggle ChipSelect pin -- NO-OP */
 206 int fpga_cs_fn(int assert_clk, int flush, int cookie)
 207 {
 208         return assert_clk;
 209 }
 210
 211 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
 212         fpga_pre_config_fn,
 213         fpga_pgm_fn,
 214         fpga_init_fn,
 215         NULL,   /* err */
 216         fpga_done_fn,
 217         fpga_clk_fn,
 218         fpga_cs_fn,
 219         fpga_wr_fn,
 220         NULL,   /* rdata */
 221         fpga_wdata_fn,
 222         fpga_busy_fn,
 223         NULL,   /* abort */
 224         fpga_post_config_fn,
 225 };
 226
 227 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
 228                         (void *)&balloon3_fpga_fns, 0);
 229
 230 /* Initialize the FPGA */
 231 void balloon3_init_fpga(void)
 232 {
 233         fpga_init();
 234         fpga_add(fpga_xilinx, &fpga);
 235 }
 236 #else
 237 void balloon3_init_fpga(void) {}
 238 #endif /* CONFIG_FPGA */