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git.ipfire.org Git - people/ms/u-boot.git/blob - board/bf537-stamp/post-memory.c
7 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
9 #define PATTERN1 0x5A5A5A5A
10 #define PATTERN2 0xAAAAAAAA
15 void post_out_buff(char *buff
);
16 int post_key_pressed(void);
17 void post_init_pll(int mult
, int div
);
18 int post_init_sdram(int sclk
);
19 void post_init_uart(int sclk
);
21 const int pll
[CCLK_NUM
][SCLK_NUM
][2] = {
22 { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
23 { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */
24 { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */
25 { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */
27 const char *const log
[CCLK_NUM
][SCLK_NUM
] = {
28 {"CCLK-500MHz SCLK-125MHz: Writing...\0",
29 "CCLK-500MHz SCLK-100MHz: Writing...\0",
30 "CCLK-500MHz SCLK- 50MHz: Writing...\0",},
31 {"CCLK-400MHz SCLK-100MHz: Writing...\0",
32 "CCLK-400MHz SCLK- 80MHz: Writing...\0",
33 "CCLK-400MHz SCLK- 50MHz: Writing...\0",},
34 {"CCLK-200MHz SCLK-100MHz: Writing...\0",
35 "CCLK-200MHz SCLK- 50MHz: Writing...\0",
36 "CCLK-200MHz SCLK- 40MHz: Writing...\0",},
37 {"CCLK-100MHz SCLK-100MHz: Writing...\0",
38 "CCLK-100MHz SCLK- 50MHz: Writing...\0",
39 "CCLK-100MHz SCLK- 25MHz: Writing...\0",},
42 int memory_post_test(int flags
)
49 sclk_temp
= CLKIN
/ 1000000;
50 sclk_temp
= sclk_temp
* CONFIG_VCO_MULT
;
51 for (sclk
= 0; sclk_temp
> 0; sclk
++)
52 sclk_temp
-= CONFIG_SCLK_DIV
;
53 sclk
= sclk
* 1000000;
55 if (post_key_pressed() == 0)
58 for (m
= 0; m
< CCLK_NUM
; m
++) {
59 for (n
= 0; n
< SCLK_NUM
; n
++) {
60 /* Calculate the sclk */
61 sclk_temp
= CLKIN
/ 1000000;
62 sclk_temp
= sclk_temp
* pll
[m
][n
][0];
63 for (sclk
= 0; sclk_temp
> 0; sclk
++)
64 sclk_temp
-= pll
[m
][n
][1];
65 sclk
= sclk
* 1000000;
67 post_init_pll(pll
[m
][n
][0], pll
[m
][n
][1]);
68 post_init_sdram(sclk
);
70 post_out_buff("\n\r\0");
71 post_out_buff(log
[m
][n
]);
72 for (addr
= 0x0; addr
< CONFIG_SYS_MAX_RAM_SIZE
; addr
+= 4)
73 *(unsigned long *)addr
= PATTERN1
;
74 post_out_buff("Reading...\0");
75 for (addr
= 0x0; addr
< CONFIG_SYS_MAX_RAM_SIZE
; addr
+= 4) {
76 if ((*(unsigned long *)addr
) != PATTERN1
) {
77 post_out_buff("Error\n\r\0");
81 post_out_buff("OK\n\r\0");
85 post_out_buff("memory POST passed\n\r\0");
87 post_out_buff("memory POST failed\n\r\0");
89 post_out_buff("\n\r\n\r\0");
93 void post_init_uart(int sclk
)
97 for (divisor
= 0; sclk
> 0; divisor
++)
100 *pPORTF_FER
= 0x000F;
101 *pPORTH_FER
= 0xFFFF;
106 *pUART_DLL
= (divisor
& 0xFF);
108 *pUART_DLH
= ((divisor
>> 8) & 0xFF);
116 void post_out_buff(char *buff
)
120 for (i
= 0; i
< 0x80000; i
++)
123 while ((buff
[i
] != '\0') && (i
!= 100)) {
124 while (!(*pUART_LSR
& 0x20)) ;
125 *pUART_THR
= buff
[i
];
129 for (i
= 0; i
< 0x80000; i
++)
133 /* Using sw10-PF5 as the hotkey */
134 #define KEY_LOOP 0x80000
135 #define KEY_DELAY 0x80
136 int post_key_pressed(void)
139 unsigned short value
;
142 *pPORTFIO_DIR
&= ~PF5
;
143 *pPORTFIO_INEN
|= PF5
;
146 post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
147 for (i
= 0; i
< KEY_LOOP
; i
++) {
148 value
= *pPORTFIO
& PF5
;
149 if (*pUART0_RBR
== 0x0D) {
155 for (n
= 0; n
< KEY_DELAY
; n
++)
158 post_out_buff("\b2\0");
160 for (i
= 0; i
< KEY_LOOP
; i
++) {
161 value
= *pPORTFIO
& PF5
;
162 if (*pUART0_RBR
== 0x0D) {
168 for (n
= 0; n
< KEY_DELAY
; n
++)
171 post_out_buff("\b1\0");
173 for (i
= 0; i
< KEY_LOOP
; i
++) {
174 value
= *pPORTFIO
& PF5
;
175 if (*pUART0_RBR
== 0x0D) {
181 for (n
= 0; n
< KEY_DELAY
; n
++)
185 post_out_buff("\b0");
186 post_out_buff("\n\r\0");
189 post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
193 void post_init_pll(int mult
, int div
)
197 *pPLL_CTL
= (mult
<< 9);
202 while (!(*pPLL_STAT
& 0x20)) ;
205 int post_init_sdram(int sclk
)
207 int SDRAM_tRP
, SDRAM_tRP_num
, SDRAM_tRAS
, SDRAM_tRAS_num
, SDRAM_tRCD
,
209 int SDRAM_Tref
, SDRAM_NRA
, SDRAM_CL
, SDRAM_SIZE
, SDRAM_WIDTH
,
210 mem_SDGCTL
, mem_SDBCTL
, mem_SDRRC
;
212 if ((sclk
> 119402985)) {
219 } else if ((sclk
> 104477612) && (sclk
<= 119402985)) {
226 } else if ((sclk
> 89552239) && (sclk
<= 104477612)) {
233 } else if ((sclk
> 74626866) && (sclk
<= 89552239)) {
240 } else if ((sclk
> 66666667) && (sclk
<= 74626866)) {
247 } else if ((sclk
> 59701493) && (sclk
<= 66666667)) {
254 } else if ((sclk
> 44776119) && (sclk
<= 59701493)) {
261 } else if ((sclk
> 29850746) && (sclk
<= 44776119)) {
268 } else if (sclk
<= 29850746) {
283 /*SDRAM INFORMATION: */
284 SDRAM_Tref
= 64; /* Refresh period in milliseconds */
285 SDRAM_NRA
= 4096; /* Number of row addresses in SDRAM */
286 SDRAM_CL
= CL_3
; /* 2 */
288 SDRAM_SIZE
= EBSZ_64
;
289 SDRAM_WIDTH
= EBCAW_10
;
291 mem_SDBCTL
= SDRAM_WIDTH
| SDRAM_SIZE
| EBE
;
293 /* Equation from section 17 (p17-46) of BF533 HRM */
295 (((CONFIG_SCLK_HZ
/ 1000) * SDRAM_Tref
) / SDRAM_NRA
) -
296 (SDRAM_tRAS_num
+ SDRAM_tRP_num
);
298 /* Enable SCLK Out */
300 (SCTLE
| SDRAM_CL
| SDRAM_tRAS
| SDRAM_tRP
| SDRAM_tRCD
| SDRAM_tWR
305 *pEBIU_SDGCTL
|= 0x1000000;
306 /* Set the SDRAM Refresh Rate control register based on SSCLK value */
307 *pEBIU_SDRRC
= mem_SDRRC
;
309 /* SDRAM Memory Bank Control Register */
310 *pEBIU_SDBCTL
= mem_SDBCTL
;
312 /* SDRAM Memory Global Control Register */
313 *pEBIU_SDGCTL
= mem_SDGCTL
;
318 #endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */