board/bluegiga/apx4devkit/apx4devkit.c

   1 /*
   2  * Bluegiga APX4 Development Kit
   3  *
   4  * Copyright (C) 2012 Bluegiga Technologies Oy
   5  *
   6  * Authors:
   7  * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
   8  * Lauri Hintsala <lauri.hintsala@bluegiga.com>
   9  *
  10  * Based on m28evk.c:
  11  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  12  * on behalf of DENX Software Engineering GmbH
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/iomux-mx28.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <linux/mii.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <errno.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* Functions */
  32 int board_early_init_f(void)
  33 {
  34         /* IO0 clock at 480MHz */
  35         mxs_set_ioclk(MXC_IOCLK0, 480000);
  36         /* IO1 clock at 480MHz */
  37         mxs_set_ioclk(MXC_IOCLK1, 480000);
  38
  39         /* SSP0 clock at 96MHz */
  40         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
  41
  42         return 0;
  43 }
  44
  45 int dram_init(void)
  46 {
  47         return mxs_dram_init();
  48 }
  49
  50 int board_init(void)
  51 {
  52         /* Adress of boot parameters */
  53         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  54
  55         return 0;
  56 }
  57
  58 #ifdef CONFIG_CMD_MMC
  59 int board_mmc_init(bd_t *bis)
  60 {
  61         return mxsmmc_initialize(bis, 0, NULL, NULL);
  62 }
  63 #endif
  64
  65
  66 #ifdef CONFIG_CMD_NET
  67
  68 #define MII_PHY_CTRL2 0x1f
  69 int fecmxc_mii_postcall(int phy)
  70 {
  71         /* change PHY RMII clock to 50MHz */
  72         miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
  73
  74         return 0;
  75 }
  76
  77 int board_eth_init(bd_t *bis)
  78 {
  79         int ret;
  80         struct eth_device *dev;
  81
  82         ret = cpu_eth_init(bis);
  83         if (ret) {
  84                 printf("FEC MXS: Unable to init FEC clocks\n");
  85                 return ret;
  86         }
  87
  88         ret = fecmxc_initialize(bis);
  89         if (ret) {
  90                 printf("FEC MXS: Unable to init FEC\n");
  91                 return ret;
  92         }
  93
  94         dev = eth_get_dev_by_name("FEC");
  95         if (!dev) {
  96                 printf("FEC MXS: Unable to get FEC device entry\n");
  97                 return -EINVAL;
  98         }
  99
 100         ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
 101         if (ret) {
 102                 printf("FEC MXS: Unable to register FEC MII postcall\n");
 103                 return ret;
 104         }
 105
 106         return ret;
 107 }
 108 #endif
 109
 110 #ifdef CONFIG_SERIAL_TAG
 111 #define MXS_OCOTP_MAX_TIMEOUT 1000000
 112 void get_board_serial(struct tag_serialnr *serialnr)
 113 {
 114         struct mxs_ocotp_regs *ocotp_regs =
 115                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 116
 117         serialnr->high = 0;
 118         serialnr->low = 0;
 119
 120         writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
 121
 122         if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
 123                 MXS_OCOTP_MAX_TIMEOUT)) {
 124                 printf("MXS: Can't get serial number from OCOTP\n");
 125                 return;
 126         }
 127
 128         serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
 129 }
 130 #endif
 131
 132 #ifdef CONFIG_REVISION_TAG
 133 u32 get_board_rev(void)
 134 {
 135         if (getenv("revision#") != NULL)
 136                 return simple_strtoul(getenv("revision#"), NULL, 10);
 137         return 0;
 138 }
 139 #endif