board/bosch/guardian/mux.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * mux.c
   4  *
   5  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   6  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/mux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/io.h>
  15 #include "board.h"
  16
  17 static struct module_pin_mux uart0_pin_mux[] = {
  18         {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
  19         {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  20         {-1},
  21 };
  22
  23 static struct module_pin_mux i2c0_pin_mux[] = {
  24         {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  25         {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  26         {-1},
  27 };
  28
  29 static struct module_pin_mux guardian_interfaces_pin_mux[] = {
  30         {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
  31         {OFFSET(mcasp0_aclkx),  (MODE(7) | PULLUP_EN)},
  32         {OFFSET(mii1_txd0),     (MODE(7) | PULLUP_EN)},
  33         {OFFSET(uart1_rxd),     (MODE(7) | RXACTIVE | PULLUDDIS)},
  34         {OFFSET(uart1_txd),     (MODE(7) | PULLUDDIS)},
  35         {OFFSET(mii1_crs),      (MODE(7) | PULLDOWN_EN)},
  36         {OFFSET(rmii1_refclk),  (MODE(7) | PULLDOWN_EN)},
  37         {OFFSET(mii1_txd3),     (MODE(7) | PULLUDDIS)},
  38         {OFFSET(mii1_rxdv),     (MODE(7) | PULLDOWN_EN)},
  39         {-1},
  40 };
  41
  42 #ifdef CONFIG_MTD_RAW_NAND
  43 static struct module_pin_mux nand_pin_mux[] = {
  44         {OFFSET(gpmc_ad0),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  45         {OFFSET(gpmc_ad1),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  46         {OFFSET(gpmc_ad2),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  47         {OFFSET(gpmc_ad3),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  48         {OFFSET(gpmc_ad4),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  49         {OFFSET(gpmc_ad5),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  50         {OFFSET(gpmc_ad6),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  51         {OFFSET(gpmc_ad7),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  52 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  53         {OFFSET(gpmc_ad8),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  54         {OFFSET(gpmc_ad9),      (MODE(0) | PULLUDDIS | RXACTIVE)},
  55         {OFFSET(gpmc_ad10),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  56         {OFFSET(gpmc_ad11),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  57         {OFFSET(gpmc_ad12),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  58         {OFFSET(gpmc_ad13),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  59         {OFFSET(gpmc_ad14),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  60         {OFFSET(gpmc_ad15),     (MODE(0) | PULLUDDIS | RXACTIVE)},
  61 #endif
  62         {OFFSET(gpmc_wait0),    (MODE(0) | PULLUP_EN | RXACTIVE)},
  63         {OFFSET(gpmc_wpn),      (MODE(7) | PULLUP_EN)},
  64         {OFFSET(gpmc_csn0),     (MODE(0) | PULLUP_EN)},
  65         {OFFSET(gpmc_wen),      (MODE(0) | PULLDOWN_EN)},
  66         {OFFSET(gpmc_oen_ren),  (MODE(0) | PULLDOWN_EN)},
  67         {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
  68         {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
  69         {-1},
  70 };
  71 #endif
  72
  73 void enable_uart0_pin_mux(void)
  74 {
  75         configure_module_pin_mux(uart0_pin_mux);
  76 }
  77
  78 void enable_i2c0_pin_mux(void)
  79 {
  80         configure_module_pin_mux(i2c0_pin_mux);
  81 }
  82
  83 void enable_board_pin_mux(void)
  84 {
  85 #ifdef CONFIG_MTD_RAW_NAND
  86         configure_module_pin_mux(nand_pin_mux);
  87 #endif
  88         configure_module_pin_mux(guardian_interfaces_pin_mux);
  89 }