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git.ipfire.org Git - thirdparty/u-boot.git/blob - board/canmb/canmb.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * SPDX-License-Identifier: GPL-2.0+
15 #if defined(CONFIG_MPC5200_DDR)
16 #include "mt46v16m16-75.h"
18 #include "mt48lc16m32s2-75.h"
21 #ifndef CONFIG_SYS_RAMBOOT
22 static void sdram_start (int hi_addr
)
24 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
26 /* unlock mode register */
27 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
;
28 __asm__
volatile ("sync");
30 /* precharge all banks */
31 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
32 __asm__
volatile ("sync");
35 /* set mode register: extended mode */
36 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_EMODE
;
37 __asm__
volatile ("sync");
39 /* set mode register: reset DLL */
40 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
| 0x04000000;
41 __asm__
volatile ("sync");
44 /* precharge all banks */
45 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
46 __asm__
volatile ("sync");
49 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
;
50 __asm__
volatile ("sync");
52 /* set mode register */
53 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
;
54 __asm__
volatile ("sync");
56 /* normal operation */
57 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| hi_addr_bit
;
58 __asm__
volatile ("sync");
63 * ATTENTION: Although partially referenced initdram does NOT make real use
64 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
65 * is something else than 0x00000000.
68 phys_size_t
initdram (int board_type
)
72 #ifndef CONFIG_SYS_RAMBOOT
75 /* setup SDRAM chip selects */
76 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x0000001e;/* 2G at 0x0 */
77 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= 0x80000000;/* disabled */
78 __asm__
volatile ("sync");
80 /* setup config registers */
81 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
82 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
83 __asm__
volatile ("sync");
87 *(vu_long
*)MPC5XXX_CDM_PORCFG
= SDRAM_TAPDELAY
;
88 __asm__
volatile ("sync");
91 /* find RAM size using SDRAM CS0 only */
93 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
95 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
103 /* memory smaller than 1MB is impossible */
104 if (dramsize
< (1 << 20)) {
108 /* set SDRAM CS0 size according to the amount of RAM found */
110 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x13 + __builtin_ffs(dramsize
>> 20) - 1;
112 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0; /* disabled */
115 /* let SDRAM CS1 start right after CS0 */
116 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
118 /* find RAM size using SDRAM CS1 only */
121 test2
= test1
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
124 test2
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
133 /* memory smaller than 1MB is impossible */
134 if (dramsize2
< (1 << 20)) {
138 /* set SDRAM CS1 size according to the amount of RAM found */
140 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
141 | (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
143 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
146 #else /* CONFIG_SYS_RAMBOOT */
148 /* retrieve size of memory connected to SDRAM CS0 */
149 dramsize
= *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
& 0xFF;
150 if (dramsize
>= 0x13) {
151 dramsize
= (1 << (dramsize
- 0x13)) << 20;
156 /* retrieve size of memory connected to SDRAM CS1 */
157 dramsize2
= *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
& 0xFF;
158 if (dramsize2
>= 0x13) {
159 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
164 #endif /* CONFIG_SYS_RAMBOOT */
166 return dramsize
+ dramsize2
;
169 int checkboard (void)
171 puts ("Board: CANMB\n");
175 int board_early_init_r (void)
177 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
178 *(vu_long
*)MPC5XXX_BOOTCS_START
=
179 *(vu_long
*)MPC5XXX_CS0_START
= START_REG(CONFIG_SYS_FLASH_BASE
);
180 *(vu_long
*)MPC5XXX_BOOTCS_STOP
=
181 *(vu_long
*)MPC5XXX_CS0_STOP
= STOP_REG(CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_SIZE
);