board/cds/common/via.c

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25
  26 /* Config the VIA chip */
  27 void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  28 {
  29         pci_dev_t bridge;
  30
  31         /* Enable USB and IDE functions */
  32         pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
  33
  34         pciauto_config_device(hose, dev);
  35
  36         /*
  37          * Force the backplane P2P bridge to have a window
  38          * open from 0x00000000-0x00001fff in PCI I/O space.
  39          * This allows legacy I/O (i8259, etc) on the VIA
  40          * southbridge to be accessed.
  41          */
  42         bridge = PCI_BDF(0,17,0);
  43         pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
  44         pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
  45         pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
  46         pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
  47 }
  48
  49 /* Function 1, IDE */
  50 void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  51 {
  52         pciauto_config_device(hose, dev);
  53         /*
  54          * Since the P2P window was forced to cover the fixed
  55          * legacy I/O addresses, it is necessary to manually
  56          * place the base addresses for the IDE and USB functions
  57          * within this window.
  58          */
  59         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
  60         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
  61         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
  62         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
  63         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
  64 }
  65
  66 /* Function 2, USB ports 0-1 */
  67 void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  68 {
  69         pciauto_config_device(hose, dev);
  70
  71         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
  72 }
  73
  74 /* Function 3, USB ports 2-3 */
  75 void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  76 {
  77         pciauto_config_device(hose, dev);
  78
  79         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
  80 }
  81
  82 /* Function 5, Power Management */
  83 void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  84 {
  85         pciauto_config_device(hose, dev);
  86
  87         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
  88         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
  89         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
  90 }
  91
  92 /* Function 6, AC97 Interface */
  93 void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  94 {
  95         pciauto_config_device(hose, dev);
  96
  97         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
  98 }
  99