board/cds/mpc8548cds/mpc8548cds.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/immap_85xx.h>
  29 #include <spd.h>
  30
  31 #include "../common/cadmus.h"
  32 #include "../common/eeprom.h"
  33 #include "../common/via.h"
  34
  35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  36 extern void ddr_enable_ecc(unsigned int dram_size);
  37 #endif
  38
  39 extern long int spd_sdram(void);
  40
  41 void local_bus_init(void);
  42 void sdram_init(void);
  43
  44 int board_early_init_f (void)
  45 {
  46         return 0;
  47 }
  48
  49 int checkboard (void)
  50 {
  51         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  52         volatile ccsr_gur_t *gur = &immap->im_gur;
  53
  54         /* PCI slot in USER bits CSR[6:7] by convention. */
  55         uint pci_slot = get_pci_slot ();
  56
  57         uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
  58         uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
  59         uint pci1_clk_sel = gur->porpllsr & 0x8000;     /* PORPLLSR[16] */
  60         uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
  61
  62         uint pci1_speed = get_clock_freq ();    /* PCI PSPEED in [4:5] */
  63
  64         uint cpu_board_rev = get_cpu_board_revision ();
  65
  66         printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
  67                 get_board_version (), pci_slot);
  68
  69         printf ("CPU Board Revision %d.%d (0x%04x)\n",
  70                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  71                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  72
  73         printf ("    PCI1: %d bit, %s MHz, %s\n",
  74                 (pci1_32) ? 32 : 64,
  75                 (pci1_speed == 33000000) ? "33" :
  76                 (pci1_speed == 66000000) ? "66" : "unknown",
  77                 pci1_clk_sel ? "sync" : "async");
  78
  79         if (pci_dual) {
  80                 printf ("    PCI2: 32 bit, 66 MHz, %s\n",
  81                         pci2_clk_sel ? "sync" : "async");
  82         } else {
  83                 printf ("    PCI2: disabled\n");
  84         }
  85
  86         /*
  87          * Initialize local bus.
  88          */
  89         local_bus_init ();
  90
  91
  92         /*
  93          * Hack TSEC 3 and 4 IO voltages.
  94          */
  95         gur->tsec34ioovcr = 0xe7e0;     /*  1110 0111 1110 0xxx */
  96
  97         return 0;
  98 }
  99
 100 long int
 101 initdram(int board_type)
 102 {
 103         long dram_size = 0;
 104         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 105
 106         puts("Initializing\n");
 107
 108 #if defined(CONFIG_DDR_DLL)
 109         {
 110                 /*
 111                  * Work around to stabilize DDR DLL MSYNC_IN.
 112                  * Errata DDR9 seems to have been fixed.
 113                  * This is now the workaround for Errata DDR11:
 114                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 115                  */
 116
 117                 volatile ccsr_gur_t *gur= &immap->im_gur;
 118
 119                 gur->ddrdllcr = 0x81000000;
 120                 asm("sync;isync;msync");
 121                 udelay(200);
 122         }
 123 #endif
 124         dram_size = spd_sdram();
 125
 126 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 127         /*
 128          * Initialize and enable DDR ECC.
 129          */
 130         ddr_enable_ecc(dram_size);
 131 #endif
 132         /*
 133          * SDRAM Initialization
 134          */
 135         sdram_init();
 136
 137         puts("    DDR: ");
 138         return dram_size;
 139 }
 140
 141 /*
 142  * Initialize Local Bus
 143  */
 144 void
 145 local_bus_init(void)
 146 {
 147         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 148         volatile ccsr_gur_t *gur = &immap->im_gur;
 149         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 150
 151         uint clkdiv;
 152         uint lbc_hz;
 153         sys_info_t sysinfo;
 154
 155         get_sys_info(&sysinfo);
 156         clkdiv = (lbc->lcrr & 0x0f) * 2;
 157         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 158
 159         gur->lbiuiplldcr1 = 0x00078080;
 160         if (clkdiv == 16) {
 161                 gur->lbiuiplldcr0 = 0x7c0f1bf0;
 162         } else if (clkdiv == 8) {
 163                 gur->lbiuiplldcr0 = 0x6c0f1bf0;
 164         } else if (clkdiv == 4) {
 165                 gur->lbiuiplldcr0 = 0x5c0f1bf0;
 166         }
 167
 168         lbc->lcrr |= 0x00030000;
 169
 170         asm("sync;isync;msync");
 171 }
 172
 173 /*
 174  * Initialize SDRAM memory on the Local Bus.
 175  */
 176 void
 177 sdram_init(void)
 178 {
 179 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 180
 181         uint idx;
 182         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 183         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 184         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 185         uint cpu_board_rev;
 186         uint lsdmr_common;
 187
 188         puts("    SDRAM: ");
 189
 190         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 191
 192         /*
 193          * Setup SDRAM Base and Option Registers
 194          */
 195         lbc->or2 = CFG_OR2_PRELIM;
 196         asm("msync");
 197
 198         lbc->br2 = CFG_BR2_PRELIM;
 199         asm("msync");
 200
 201         lbc->lbcr = CFG_LBC_LBCR;
 202         asm("msync");
 203
 204
 205         lbc->lsrt = CFG_LBC_LSRT;
 206         lbc->mrtpr = CFG_LBC_MRTPR;
 207         asm("msync");
 208
 209         /*
 210          * MPC8548 uses "new" 15-16 style addressing.
 211          */
 212         cpu_board_rev = get_cpu_board_revision();
 213         lsdmr_common = CFG_LBC_LSDMR_COMMON;
 214         lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
 215
 216         /*
 217          * Issue PRECHARGE ALL command.
 218          */
 219         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
 220         asm("sync;msync");
 221         *sdram_addr = 0xff;
 222         ppcDcbf((unsigned long) sdram_addr);
 223         udelay(100);
 224
 225         /*
 226          * Issue 8 AUTO REFRESH commands.
 227          */
 228         for (idx = 0; idx < 8; idx++) {
 229                 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
 230                 asm("sync;msync");
 231                 *sdram_addr = 0xff;
 232                 ppcDcbf((unsigned long) sdram_addr);
 233                 udelay(100);
 234         }
 235
 236         /*
 237          * Issue 8 MODE-set command.
 238          */
 239         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
 240         asm("sync;msync");
 241         *sdram_addr = 0xff;
 242         ppcDcbf((unsigned long) sdram_addr);
 243         udelay(100);
 244
 245         /*
 246          * Issue NORMAL OP command.
 247          */
 248         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
 249         asm("sync;msync");
 250         *sdram_addr = 0xff;
 251         ppcDcbf((unsigned long) sdram_addr);
 252         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 253
 254 #endif  /* enable SDRAM init */
 255 }
 256
 257 #if defined(CFG_DRAM_TEST)
 258 int
 259 testdram(void)
 260 {
 261         uint *pstart = (uint *) CFG_MEMTEST_START;
 262         uint *pend = (uint *) CFG_MEMTEST_END;
 263         uint *p;
 264
 265         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 266                CFG_MEMTEST_START,
 267                CFG_MEMTEST_END);
 268
 269         printf("DRAM test phase 1:\n");
 270         for (p = pstart; p < pend; p++)
 271                 *p = 0xaaaaaaaa;
 272
 273         for (p = pstart; p < pend; p++) {
 274                 if (*p != 0xaaaaaaaa) {
 275                         printf ("DRAM test fails at: %08x\n", (uint) p);
 276                         return 1;
 277                 }
 278         }
 279
 280         printf("DRAM test phase 2:\n");
 281         for (p = pstart; p < pend; p++)
 282                 *p = 0x55555555;
 283
 284         for (p = pstart; p < pend; p++) {
 285                 if (*p != 0x55555555) {
 286                         printf ("DRAM test fails at: %08x\n", (uint) p);
 287                         return 1;
 288                 }
 289         }
 290
 291         printf("DRAM test passed.\n");
 292         return 0;
 293 }
 294 #endif
 295
 296 #if defined(CONFIG_PCI)
 297 /* For some reason the Tundra PCI bridge shows up on itself as a
 298  * different device.  Work around that by refusing to configure it.
 299  */
 300 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 301
 302 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 303         {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 304         {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
 305         {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
 306         {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
 307         {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
 308         {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
 309         {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
 310 };
 311
 312 static struct pci_controller hose[] = {
 313         { config_table: pci_mpc85xxcds_config_table,},
 314 #ifdef CONFIG_MPC85XX_PCI2
 315         {},
 316 #endif
 317 };
 318
 319 #endif  /* CONFIG_PCI */
 320
 321 void
 322 pci_init_board(void)
 323 {
 324 #ifdef CONFIG_PCI
 325         extern void pci_mpc85xx_init(struct pci_controller **hose);
 326
 327         pci_mpc85xx_init(&hose);
 328 #endif
 329 }