board/cds/mpc8555cds/mpc8555cds.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23
  24 #include <common.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_85xx.h>
  28 #include <spd.h>
  29
  30 #include "../common/cadmus.h"
  31 #include "../common/eeprom.h"
  32
  33 #if defined(CONFIG_DDR_ECC)
  34 extern void ddr_enable_ecc(unsigned int dram_size);
  35 #endif
  36
  37 extern long int spd_sdram(void);
  38
  39 void local_bus_init(void);
  40 void sdram_init(void);
  41
  42
  43
  44 int
  45 board_early_init_f(void)
  46 {
  47     return 0;
  48 }
  49
  50
  51 int
  52 checkboard(void)
  53 {
  54     volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
  55     volatile ccsr_gur_t *gur = &immap->im_gur;
  56
  57     /* PCI slot in USER bits CSR[6:7] by convention. */
  58     uint pci_slot = get_pci_slot();
  59
  60     uint pci_dual = get_pci_dual();             /* PCI DUAL in CM_PCI[3] */
  61     uint pci1_32 = gur->pordevsr & 0x10000;     /* PORDEVSR[15] */
  62     uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
  63     uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  64
  65     uint pci1_speed = get_clock_freq();         /* PCI PSPEED in [4:5] */
  66
  67     uint cpu_board_rev = get_cpu_board_revision();
  68
  69     printf("Board: CDS Version 0x%02x, PCI Slot %d\n",
  70            get_board_version(),
  71            pci_slot);
  72
  73     printf("CPU Board Revision %d.%d (0x%04x)\n",
  74            MPC85XX_CPU_BOARD_MAJOR(cpu_board_rev),
  75            MPC85XX_CPU_BOARD_MINOR(cpu_board_rev),
  76            cpu_board_rev);
  77
  78     printf("    PCI1: %d bit, %s MHz, %s\n",
  79            (pci1_32) ? 32 : 64,
  80            (pci1_speed == 33000000) ? "33" :
  81            (pci1_speed == 66000000) ? "66" : "unknown",
  82            pci1_clk_sel ? "sync" : "async"
  83            );
  84
  85     if (pci_dual) {
  86         printf("    PCI2: 32 bit, 66 MHz, %s\n",
  87                pci2_clk_sel ? "sync" : "async"
  88                );
  89     } else {
  90         printf("    PCI2: disabled\n");
  91     }
  92
  93     /*
  94      * Initialize local bus.
  95      */
  96     local_bus_init();
  97
  98     return 0;
  99 }
 100
 101
 102 long int
 103 initdram(int board_type)
 104 {
 105         long dram_size = 0;
 106         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 107
 108         puts("Initializing\n");
 109
 110 #if defined(CONFIG_DDR_DLL)
 111         {
 112                 /*
 113                  * Work around to stabilize DDR DLL MSYNC_IN.
 114                  * Errata DDR9 seems to have been fixed.
 115                  * This is now the workaround for Errata DDR11:
 116                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 117                  */
 118
 119                 volatile ccsr_gur_t *gur= &immap->im_gur;
 120
 121                 gur->ddrdllcr = 0x81000000;
 122                 asm("sync;isync;msync");
 123                 udelay(200);
 124         }
 125 #endif
 126
 127         dram_size = spd_sdram();
 128
 129
 130 #if defined(CONFIG_DDR_ECC)
 131         /*
 132          * Initialize and enable DDR ECC.
 133          */
 134         ddr_enable_ecc(dram_size);
 135 #endif
 136
 137
 138         /*
 139          * SDRAM Initialization
 140          */
 141         sdram_init();
 142
 143         puts("    DDR: ");
 144         return dram_size;
 145 }
 146
 147
 148 /*
 149  * Initialize Local Bus
 150  */
 151
 152 void
 153 local_bus_init(void)
 154 {
 155         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 156         volatile ccsr_gur_t *gur = &immap->im_gur;
 157         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 158
 159         uint clkdiv;
 160         uint lbc_hz;
 161         sys_info_t sysinfo;
 162         uint temp_lbcdll;
 163
 164         /*
 165          * Errata LBC11.
 166          * Fix Local Bus clock glitch when DLL is enabled.
 167          *
 168          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 169          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 170          * Between 66 and 133, the DLL is enabled with an override workaround.
 171          */
 172
 173         get_sys_info(&sysinfo);
 174         clkdiv = lbc->lcrr & 0x0f;
 175         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 176
 177         if (lbc_hz < 66) {
 178                 lbc->lcrr |= 0x80000000;        /* DLL Bypass */
 179
 180         } else if (lbc_hz >= 133) {
 181                 lbc->lcrr &= (~0x80000000);             /* DLL Enabled */
 182
 183         } else {
 184                 lbc->lcrr &= (~0x8000000);      /* DLL Enabled */
 185                 udelay(200);
 186
 187                 /*
 188                  * Sample LBC DLL ctrl reg, upshift it to set the
 189                  * override bits.
 190                  */
 191                 temp_lbcdll = gur->lbcdllcr;
 192                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 193                 asm("sync;isync;msync");
 194         }
 195 }
 196
 197
 198 /*
 199  * Initialize SDRAM memory on the Local Bus.
 200  */
 201
 202 void
 203 sdram_init(void)
 204 {
 205 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
 206
 207         uint idx;
 208         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 209         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 210         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 211         uint cpu_board_rev;
 212         uint lsdmr_common;
 213
 214         puts("    SDRAM: ");
 215
 216         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 217
 218         /*
 219          * Setup SDRAM Base and Option Registers
 220          */
 221         lbc->or2 = CFG_OR2_PRELIM;
 222         asm("msync");
 223
 224         lbc->br2 = CFG_BR2_PRELIM;
 225         asm("msync");
 226
 227         lbc->lbcr = CFG_LBC_LBCR;
 228         asm("msync");
 229
 230
 231         lbc->lsrt = CFG_LBC_LSRT;
 232         lbc->mrtpr = CFG_LBC_MRTPR;
 233         asm("msync");
 234
 235         /*
 236          * Determine which address lines to use baed on CPU board rev.
 237          */
 238         cpu_board_rev = get_cpu_board_revision();
 239         lsdmr_common = CFG_LBC_LSDMR_COMMON;
 240         if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
 241                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
 242         } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
 243                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
 244         } else {
 245                 /*
 246                  * Assume something unable to identify itself is
 247                  * really old, and likely has lines 16/17 mapped.
 248                  */
 249                 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
 250         }
 251
 252         /*
 253          * Issue PRECHARGE ALL command.
 254          */
 255         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
 256         asm("sync;msync");
 257         *sdram_addr = 0xff;
 258         ppcDcbf((unsigned long) sdram_addr);
 259         udelay(100);
 260
 261         /*
 262          * Issue 8 AUTO REFRESH commands.
 263          */
 264         for (idx = 0; idx < 8; idx++) {
 265                 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
 266                 asm("sync;msync");
 267                 *sdram_addr = 0xff;
 268                 ppcDcbf((unsigned long) sdram_addr);
 269                 udelay(100);
 270         }
 271
 272         /*
 273          * Issue 8 MODE-set command.
 274          */
 275         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
 276         asm("sync;msync");
 277         *sdram_addr = 0xff;
 278         ppcDcbf((unsigned long) sdram_addr);
 279         udelay(100);
 280
 281         /*
 282          * Issue NORMAL OP command.
 283          */
 284         lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
 285         asm("sync;msync");
 286         *sdram_addr = 0xff;
 287         ppcDcbf((unsigned long) sdram_addr);
 288         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 289
 290 #endif  /* enable SDRAM init */
 291 }
 292
 293
 294 #if defined(CFG_DRAM_TEST)
 295 int
 296 testdram(void)
 297 {
 298         uint *pstart = (uint *) CFG_MEMTEST_START;
 299         uint *pend = (uint *) CFG_MEMTEST_END;
 300         uint *p;
 301
 302         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 303                CFG_MEMTEST_START,
 304                CFG_MEMTEST_END);
 305
 306         printf("DRAM test phase 1:\n");
 307         for (p = pstart; p < pend; p++)
 308                 *p = 0xaaaaaaaa;
 309
 310         for (p = pstart; p < pend; p++) {
 311                 if (*p != 0xaaaaaaaa) {
 312                         printf ("DRAM test fails at: %08x\n", (uint) p);
 313                         return 1;
 314                 }
 315         }
 316
 317         printf("DRAM test phase 2:\n");
 318         for (p = pstart; p < pend; p++)
 319                 *p = 0x55555555;
 320
 321         for (p = pstart; p < pend; p++) {
 322                 if (*p != 0x55555555) {
 323                         printf ("DRAM test fails at: %08x\n", (uint) p);
 324                         return 1;
 325                 }
 326         }
 327
 328         printf("DRAM test passed.\n");
 329         return 0;
 330 }
 331 #endif
 332
 333
 334
 335 #if defined(CONFIG_PCI)
 336
 337 /*
 338  * Initialize PCI Devices, report devices found.
 339  */
 340
 341 #ifndef CONFIG_PCI_PNP
 342 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 343     { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 344       PCI_IDSEL_NUMBER, PCI_ANY_ID,
 345       pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 346                                    PCI_ENET0_MEMADDR,
 347                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 348       } },
 349     { }
 350 };
 351 #endif
 352
 353
 354 static struct pci_controller hose = {
 355 #ifndef CONFIG_PCI_PNP
 356         config_table: pci_mpc85xxcds_config_table,
 357 #endif
 358 };
 359
 360 #endif  /* CONFIG_PCI */
 361
 362
 363 void
 364 pci_init_board(void)
 365 {
 366 #ifdef CONFIG_PCI
 367         extern void pci_mpc85xx_init(struct pci_controller *hose);
 368
 369         pci_mpc85xx_init(&hose);
 370 #endif
 371 }