board/cm-bf548/video.c

   1 /*
   2  * video.c - run splash screen on lcd
   3  *
   4  * Copyright (c) 2007-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <stdarg.h>
  10 #include <common.h>
  11 #include <config.h>
  12 #include <malloc.h>
  13 #include <asm/blackfin.h>
  14 #include <asm/mach-common/bits/dma.h>
  15 #include <i2c.h>
  16 #include <linux/types.h>
  17 #include <stdio_dev.h>
  18
  19 #ifdef CONFIG_VIDEO
  20
  21 #define DMA_SIZE16      2
  22
  23 #include <asm/mach-common/bits/eppi.h>
  24
  25 #include <asm/bfin_logo_230x230.h>
  26
  27 #define LCD_X_RES               480     /*Horizontal Resolution */
  28 #define LCD_Y_RES               272     /* Vertical Resolution */
  29
  30 #define LCD_BPP                 24      /* Bit Per Pixel */
  31 #define LCD_PIXEL_SIZE          (LCD_BPP / 8)
  32 #define DMA_BUS_SIZE            32
  33 #define ACTIVE_VIDEO_MEM_OFFSET 0
  34
  35 /*      -- Horizontal synchronizing --
  36  *
  37  * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
  38  * (LCY-W-06602A Page 9 of 22)
  39  *
  40  * Clock Frequency      1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
  41  *
  42  * Period               TH - 525 - Clock
  43  * Pulse width          THp - 41 - Clock
  44  * Horizontal period    THd - 480 - Clock
  45  * Back porch           THb - 2 - Clock
  46  * Front porch          THf - 2 - Clock
  47  *
  48  * -- Vertical synchronizing --
  49  * Period               TV - 286 - Line
  50  * Pulse width          TVp - 10 - Line
  51  * Vertical period      TVd - 272 - Line
  52  * Back porch           TVb - 2 - Line
  53  * Front porch          TVf - 2 - Line
  54  */
  55
  56 #define LCD_CLK                 (8*1000*1000)   /* 8MHz */
  57
  58 /* # active data to transfer after Horizontal Delay clock */
  59 #define EPPI_HCOUNT             LCD_X_RES
  60
  61 /* # active lines to transfer after Vertical Delay clock */
  62 #define EPPI_VCOUNT             LCD_Y_RES
  63
  64 /* Samples per Line = 480 (active data) + 45 (padding) */
  65 #define EPPI_LINE               525
  66
  67 /* Lines per Frame = 272 (active data) + 14 (padding) */
  68 #define EPPI_FRAME              286
  69
  70 /* FS1 (Hsync) Width (Typical)*/
  71 #define EPPI_FS1W_HBL           41
  72
  73 /* FS1 (Hsync) Period (Typical) */
  74 #define EPPI_FS1P_AVPL          EPPI_LINE
  75
  76 /* Horizontal Delay clock after assertion of Hsync (Typical) */
  77 #define EPPI_HDELAY             43
  78
  79 /* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
  80 #define EPPI_FS2W_LVB           (EPPI_LINE * 10)
  81
  82  /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
  83 #define EPPI_FS2P_LAVF          (EPPI_LINE * EPPI_FRAME)
  84
  85 /* Vertical Delay after assertion of Vsync (2 Lines) */
  86 #define EPPI_VDELAY             12
  87
  88 #define EPPI_CLIP               0xFF00FF00
  89
  90 /* EPPI Control register configuration value for RGB out
  91  * - EPPI as Output
  92  * GP 2 frame sync mode,
  93  * Internal Clock generation disabled, Internal FS generation enabled,
  94  * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
  95  * FS1 & FS2 are active high,
  96  * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
  97  * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
  98  * Swapping Enabled,
  99  * One (DMA) Channel Mode,
 100  * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
 101  * Regular watermark - when FIFO is 100% full,
 102  * Urgent watermark - when FIFO is 75% full
 103  */
 104
 105 #define EPPI_CONTROL            (0x20136E2E)
 106
 107 static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
 108 {
 109         u32 sclk = get_sclk();
 110
 111         /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
 112
 113         return (((sclk / target_ppi_clk) / 2) - 1);
 114 }
 115
 116 void Init_PPI(void)
 117 {
 118         u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
 119
 120         bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
 121         bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
 122         bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
 123         bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
 124         bfin_write_EPPI0_CLIP(EPPI_CLIP);
 125
 126         bfin_write_EPPI0_FRAME(EPPI_FRAME);
 127         bfin_write_EPPI0_LINE(EPPI_LINE);
 128
 129         bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
 130         bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
 131         bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
 132         bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
 133
 134         bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
 135
 136 /*
 137  * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
 138  * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
 139  */
 140 #if defined(CONFIG_VIDEO_RGB666)
 141         bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
 142                                  RGB_FMT_EN);
 143 #else
 144         bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
 145                                  ~RGB_FMT_EN);
 146 #endif
 147
 148 }
 149
 150 #define               DEB2_URGENT  0x2000       /* DEB2 Urgent */
 151
 152 void Init_DMA(void *dst)
 153 {
 154
 155 #if defined(CONFIG_DEB_DMA_URGENT)
 156         *pEBIU_DDRQUE |= DEB2_URGENT;
 157 #endif
 158
 159         *pDMA12_START_ADDR = dst;
 160
 161         /* X count */
 162         *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
 163         *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
 164
 165         /* Y count */
 166         *pDMA12_Y_COUNT = LCD_Y_RES;
 167         *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
 168
 169         /* DMA Config */
 170         *pDMA12_CONFIG = WDSIZE_32 |    /* 32 bit DMA */
 171             DMA2D |             /* 2D DMA */
 172             FLOW_AUTO;          /* autobuffer mode */
 173 }
 174
 175 void Init_Ports(void)
 176 {
 177         *pPORTF_MUX = 0x00000000;
 178         *pPORTF_FER |= 0xFFFF;  /* PPI0..15 */
 179
 180         *pPORTG_MUX &=
 181             ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
 182               PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
 183         *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4;     /* CLK, FS1, FS2, PPI16..17  */
 184
 185 #if !defined(CONFIG_VIDEO_RGB666)
 186         *pPORTD_MUX &=
 187             ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
 188               PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
 189         *pPORTD_MUX |=
 190             (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 |
 191              PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
 192         *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5;       /* PPI18..23  */
 193 #endif
 194
 195         *pPORTE_FER &= ~PE3;    /* DISP */
 196         *pPORTE_DIR_SET = PE3;
 197         *pPORTE_SET = PE3;
 198
 199 }
 200
 201 void EnableDMA(void)
 202 {
 203         *pDMA12_CONFIG |= DMAEN;
 204 }
 205
 206 void DisableDMA(void)
 207 {
 208         *pDMA12_CONFIG &= ~DMAEN;
 209 }
 210
 211 /* enable and disable PPI functions */
 212 void EnablePPI(void)
 213 {
 214         bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
 215 }
 216
 217 void DisablePPI(void)
 218 {
 219         bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
 220 }
 221
 222 int video_init(void *dst)
 223 {
 224         Init_Ports();
 225         Init_DMA(dst);
 226         EnableDMA();
 227         Init_PPI();
 228         EnablePPI();
 229
 230         return 0;
 231 }
 232
 233 static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
 234 {
 235         if (dcache_status())
 236                 blackfin_dcache_flush_range(logo->data,
 237                                             logo->data + logo->size);
 238
 239         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
 240
 241         /* Setup destination start address */
 242         bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
 243                                       + (y * LCD_X_RES * LCD_PIXEL_SIZE));
 244         /* Setup destination xcount */
 245         bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
 246         /* Setup destination xmodify */
 247         bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
 248
 249         /* Setup destination ycount */
 250         bfin_write_MDMA_D0_Y_COUNT(logo->height);
 251         /* Setup destination ymodify */
 252         bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
 253                                     DMA_SIZE16);
 254
 255         /* Setup Source start address */
 256         bfin_write_MDMA_S0_START_ADDR(logo->data);
 257         /* Setup Source xcount */
 258         bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
 259         /* Setup Source xmodify */
 260         bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
 261
 262         /* Setup Source ycount */
 263         bfin_write_MDMA_S0_Y_COUNT(logo->height);
 264         /* Setup Source ymodify */
 265         bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
 266
 267         /* Enable source DMA */
 268         bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
 269         SSYNC();
 270         bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
 271
 272         while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
 273
 274         bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
 275                                       | DMA_ERR);
 276         bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
 277                                       | DMA_ERR);
 278
 279 }
 280
 281 void video_putc(const char c)
 282 {
 283 }
 284
 285 void video_puts(const char *s)
 286 {
 287 }
 288
 289 int drv_video_init(void)
 290 {
 291         int error, devices = 1;
 292         struct stdio_dev videodev;
 293
 294         u8 *dst;
 295         u32 fbmem_size =
 296             LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
 297
 298         dst = malloc(fbmem_size);
 299
 300         if (dst == NULL) {
 301                 printf("Failed to alloc FB memory\n");
 302                 return -1;
 303         }
 304 #ifdef EASYLOGO_ENABLE_GZIP
 305         unsigned char *data = EASYLOGO_DECOMP_BUFFER;
 306         unsigned long src_len = EASYLOGO_ENABLE_GZIP;
 307         if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
 308                 puts("Failed to decompress logo\n");
 309                 free(dst);
 310                 return -1;
 311         }
 312         bfin_logo.data = data;
 313 #endif
 314
 315         memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
 316                fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
 317
 318         dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
 319                     (LCD_X_RES - bfin_logo.width) / 2,
 320                     (LCD_Y_RES - bfin_logo.height) / 2);
 321
 322         video_init(dst);        /* Video initialization */
 323
 324         memset(&videodev, 0, sizeof(videodev));
 325
 326         strcpy(videodev.name, "video");
 327         videodev.ext = DEV_EXT_VIDEO;   /* Video extensions */
 328         videodev.flags = DEV_FLAGS_SYSTEM;      /* No Output */
 329         videodev.putc = video_putc;     /* 'putc' function */
 330         videodev.puts = video_puts;     /* 'puts' function */
 331
 332         error = stdio_register(&videodev);
 333
 334         return (error == 0) ? devices : error;
 335 }
 336
 337 #endif