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git.ipfire.org Git - people/ms/u-boot.git/blob - board/cm-bf548/video.c
2 * video.c - run splash screen on lcd
4 * Copyright (c) 2007-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
15 #include <asm/portmux.h>
16 #include <asm/mach-common/bits/dma.h>
18 #include <linux/types.h>
19 #include <stdio_dev.h>
25 #include <asm/mach-common/bits/eppi.h>
27 #include <asm/bfin_logo_230x230.h>
29 #define LCD_X_RES 480 /*Horizontal Resolution */
30 #define LCD_Y_RES 272 /* Vertical Resolution */
32 #define LCD_BPP 24 /* Bit Per Pixel */
33 #define LCD_PIXEL_SIZE (LCD_BPP / 8)
34 #define DMA_BUS_SIZE 32
35 #define ACTIVE_VIDEO_MEM_OFFSET 0
37 /* -- Horizontal synchronizing --
39 * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
40 * (LCY-W-06602A Page 9 of 22)
42 * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
44 * Period TH - 525 - Clock
45 * Pulse width THp - 41 - Clock
46 * Horizontal period THd - 480 - Clock
47 * Back porch THb - 2 - Clock
48 * Front porch THf - 2 - Clock
50 * -- Vertical synchronizing --
51 * Period TV - 286 - Line
52 * Pulse width TVp - 10 - Line
53 * Vertical period TVd - 272 - Line
54 * Back porch TVb - 2 - Line
55 * Front porch TVf - 2 - Line
58 #define LCD_CLK (8*1000*1000) /* 8MHz */
60 /* # active data to transfer after Horizontal Delay clock */
61 #define EPPI_HCOUNT LCD_X_RES
63 /* # active lines to transfer after Vertical Delay clock */
64 #define EPPI_VCOUNT LCD_Y_RES
66 /* Samples per Line = 480 (active data) + 45 (padding) */
69 /* Lines per Frame = 272 (active data) + 14 (padding) */
70 #define EPPI_FRAME 286
72 /* FS1 (Hsync) Width (Typical)*/
73 #define EPPI_FS1W_HBL 41
75 /* FS1 (Hsync) Period (Typical) */
76 #define EPPI_FS1P_AVPL EPPI_LINE
78 /* Horizontal Delay clock after assertion of Hsync (Typical) */
79 #define EPPI_HDELAY 43
81 /* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
82 #define EPPI_FS2W_LVB (EPPI_LINE * 10)
84 /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
85 #define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
87 /* Vertical Delay after assertion of Vsync (2 Lines) */
88 #define EPPI_VDELAY 12
90 #define EPPI_CLIP 0xFF00FF00
92 /* EPPI Control register configuration value for RGB out
94 * GP 2 frame sync mode,
95 * Internal Clock generation disabled, Internal FS generation enabled,
96 * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
97 * FS1 & FS2 are active high,
98 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
99 * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
101 * One (DMA) Channel Mode,
102 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
103 * Regular watermark - when FIFO is 100% full,
104 * Urgent watermark - when FIFO is 75% full
107 #define EPPI_CONTROL (0x20136E2E)
109 static inline u16
get_eppi_clkdiv(u32 target_ppi_clk
)
111 u32 sclk
= get_sclk();
113 /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
115 return (((sclk
/ target_ppi_clk
) / 2) - 1);
120 u16 eppi_clkdiv
= get_eppi_clkdiv(LCD_CLK
);
122 bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL
);
123 bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL
);
124 bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB
);
125 bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF
);
126 bfin_write_EPPI0_CLIP(EPPI_CLIP
);
128 bfin_write_EPPI0_FRAME(EPPI_FRAME
);
129 bfin_write_EPPI0_LINE(EPPI_LINE
);
131 bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT
);
132 bfin_write_EPPI0_HDELAY(EPPI_HDELAY
);
133 bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT
);
134 bfin_write_EPPI0_VDELAY(EPPI_VDELAY
);
136 bfin_write_EPPI0_CLKDIV(eppi_clkdiv
);
139 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
140 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
142 #if defined(CONFIG_VIDEO_RGB666)
143 bfin_write_EPPI0_CONTROL((EPPI_CONTROL
& ~DLENGTH
) | DLEN_18
|
146 bfin_write_EPPI0_CONTROL(((EPPI_CONTROL
& ~DLENGTH
) | DLEN_24
) &
152 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */
154 void Init_DMA(void *dst
)
157 #if defined(CONFIG_DEB_DMA_URGENT)
158 *pEBIU_DDRQUE
|= DEB2_URGENT
;
161 *pDMA12_START_ADDR
= dst
;
164 *pDMA12_X_COUNT
= (LCD_X_RES
* LCD_BPP
) / DMA_BUS_SIZE
;
165 *pDMA12_X_MODIFY
= DMA_BUS_SIZE
/ 8;
168 *pDMA12_Y_COUNT
= LCD_Y_RES
;
169 *pDMA12_Y_MODIFY
= DMA_BUS_SIZE
/ 8;
172 *pDMA12_CONFIG
= WDSIZE_32
| /* 32 bit DMA */
174 FLOW_AUTO
; /* autobuffer mode */
177 void Init_Ports(void)
179 const unsigned short pins
[] = {
180 P_PPI0_D0
, P_PPI0_D1
, P_PPI0_D2
, P_PPI0_D3
, P_PPI0_D4
,
181 P_PPI0_D5
, P_PPI0_D6
, P_PPI0_D7
, P_PPI0_D8
, P_PPI0_D9
,
182 P_PPI0_D10
, P_PPI0_D11
, P_PPI0_D12
, P_PPI0_D13
, P_PPI0_D14
,
183 P_PPI0_D15
, P_PPI0_D16
, P_PPI0_D17
,
184 #if !defined(CONFIG_VIDEO_RGB666)
185 P_PPI0_D18
, P_PPI0_D19
, P_PPI0_D20
, P_PPI0_D21
, P_PPI0_D22
,
188 P_PPI0_CLK
, P_PPI0_FS1
, P_PPI0_FS2
, 0,
190 peripheral_request_list(pins
, "lcd");
192 gpio_request(GPIO_PE3
, "lcd-disp");
193 gpio_direction_output(GPIO_PE3
, 1);
198 *pDMA12_CONFIG
|= DMAEN
;
201 void DisableDMA(void)
203 *pDMA12_CONFIG
&= ~DMAEN
;
206 /* enable and disable PPI functions */
209 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN
);
212 void DisablePPI(void)
214 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN
);
217 int video_init(void *dst
)
228 static void dma_bitblit(void *dst
, fastimage_t
*logo
, int x
, int y
)
231 blackfin_dcache_flush_range(logo
->data
,
232 logo
->data
+ logo
->size
);
234 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE
| DMA_ERR
);
236 /* Setup destination start address */
237 bfin_write_MDMA_D0_START_ADDR(dst
+ ((x
& -2) * LCD_PIXEL_SIZE
)
238 + (y
* LCD_X_RES
* LCD_PIXEL_SIZE
));
239 /* Setup destination xcount */
240 bfin_write_MDMA_D0_X_COUNT(logo
->width
* LCD_PIXEL_SIZE
/ DMA_SIZE16
);
241 /* Setup destination xmodify */
242 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16
);
244 /* Setup destination ycount */
245 bfin_write_MDMA_D0_Y_COUNT(logo
->height
);
246 /* Setup destination ymodify */
247 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES
- logo
->width
) * LCD_PIXEL_SIZE
+
250 /* Setup Source start address */
251 bfin_write_MDMA_S0_START_ADDR(logo
->data
);
252 /* Setup Source xcount */
253 bfin_write_MDMA_S0_X_COUNT(logo
->width
* LCD_PIXEL_SIZE
/ DMA_SIZE16
);
254 /* Setup Source xmodify */
255 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16
);
257 /* Setup Source ycount */
258 bfin_write_MDMA_S0_Y_COUNT(logo
->height
);
259 /* Setup Source ymodify */
260 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16
);
262 /* Enable source DMA */
263 bfin_write_MDMA_S0_CONFIG(DMAEN
| WDSIZE_16
| DMA2D
);
265 bfin_write_MDMA_D0_CONFIG(WNR
| DMAEN
| WDSIZE_16
| DMA2D
);
267 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN
) ;
269 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
271 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
276 void video_putc(const char c
)
280 void video_puts(const char *s
)
284 int drv_video_init(void)
286 int error
, devices
= 1;
287 struct stdio_dev videodev
;
291 LCD_X_RES
* LCD_Y_RES
* LCD_PIXEL_SIZE
+ ACTIVE_VIDEO_MEM_OFFSET
;
293 dst
= malloc(fbmem_size
);
296 printf("Failed to alloc FB memory\n");
299 #ifdef EASYLOGO_ENABLE_GZIP
300 unsigned char *data
= EASYLOGO_DECOMP_BUFFER
;
301 unsigned long src_len
= EASYLOGO_ENABLE_GZIP
;
302 if (gunzip(data
, bfin_logo
.size
, bfin_logo
.data
, &src_len
)) {
303 puts("Failed to decompress logo\n");
307 bfin_logo
.data
= data
;
310 memset(dst
+ ACTIVE_VIDEO_MEM_OFFSET
, bfin_logo
.data
[0],
311 fbmem_size
- ACTIVE_VIDEO_MEM_OFFSET
);
313 dma_bitblit(dst
+ ACTIVE_VIDEO_MEM_OFFSET
, &bfin_logo
,
314 (LCD_X_RES
- bfin_logo
.width
) / 2,
315 (LCD_Y_RES
- bfin_logo
.height
) / 2);
317 video_init(dst
); /* Video initialization */
319 memset(&videodev
, 0, sizeof(videodev
));
321 strcpy(videodev
.name
, "video");
322 videodev
.ext
= DEV_EXT_VIDEO
; /* Video extensions */
323 videodev
.flags
= DEV_FLAGS_SYSTEM
; /* No Output */
324 videodev
.putc
= video_putc
; /* 'putc' function */
325 videodev
.puts
= video_puts
; /* 'puts' function */
327 error
= stdio_register(&videodev
);
329 return (error
== 0) ? devices
: error
;