board/cm_t35/cm_t35.c

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
   3  *
   4  * Authors: Mike Rapoport <mike@compulab.co.il>
   5  *          Igor Grinberg <grinberg@compulab.co.il>
   6  *
   7  * Derived from omap3evm and Beagle Board by
   8  *      Manikandan Pillai <mani.pillai@ti.com>
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc.
  28  */
  29
  30 #include <common.h>
  31 #include <status_led.h>
  32 #include <netdev.h>
  33 #include <net.h>
  34 #include <i2c.h>
  35 #include <usb.h>
  36 #include <twl4030.h>
  37 #include <linux/compiler.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/arch/mem.h>
  41 #include <asm/arch/mux.h>
  42 #include <asm/arch/mmc_host_def.h>
  43 #include <asm/arch/sys_proto.h>
  44 #include <asm/mach-types.h>
  45 #include <asm/ehci-omap.h>
  46 #include <asm/gpio.h>
  47
  48 #include "eeprom.h"
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 const omap3_sysinfo sysinfo = {
  53         DDR_DISCRETE,
  54         "CM-T3x board",
  55         "NAND",
  56 };
  57
  58 static u32 gpmc_net_config[GPMC_MAX_REG] = {
  59         NET_GPMC_CONFIG1,
  60         NET_GPMC_CONFIG2,
  61         NET_GPMC_CONFIG3,
  62         NET_GPMC_CONFIG4,
  63         NET_GPMC_CONFIG5,
  64         NET_GPMC_CONFIG6,
  65         0
  66 };
  67
  68 static u32 gpmc_nand_config[GPMC_MAX_REG] = {
  69         SMNAND_GPMC_CONFIG1,
  70         SMNAND_GPMC_CONFIG2,
  71         SMNAND_GPMC_CONFIG3,
  72         SMNAND_GPMC_CONFIG4,
  73         SMNAND_GPMC_CONFIG5,
  74         SMNAND_GPMC_CONFIG6,
  75         0,
  76 };
  77
  78 /*
  79  * Routine: board_init
  80  * Description: hardware init.
  81  */
  82 int board_init(void)
  83 {
  84         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  85
  86         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
  87                               CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
  88
  89         /* board id for Linux */
  90         if (get_cpu_family() == CPU_OMAP34XX)
  91                 gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
  92         else
  93                 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
  94
  95         /* boot param addr */
  96         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  97
  98 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  99         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 100 #endif
 101
 102         return 0;
 103 }
 104
 105 static u32 cm_t3x_rev;
 106
 107 /*
 108  * Routine: get_board_rev
 109  * Description: read system revision
 110  */
 111 u32 get_board_rev(void)
 112 {
 113         if (!cm_t3x_rev)
 114                 cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
 115
 116         return cm_t3x_rev;
 117 };
 118
 119 /*
 120  * Routine: misc_init_r
 121  * Description: display die ID
 122  */
 123 int misc_init_r(void)
 124 {
 125         u32 board_rev = get_board_rev();
 126         u32 rev_major = board_rev / 100;
 127         u32 rev_minor = board_rev - (rev_major * 100);
 128
 129         if ((rev_minor / 10) * 10 == rev_minor)
 130                 rev_minor = rev_minor / 10;
 131
 132         printf("PCB:   %u.%u\n", rev_major, rev_minor);
 133         dieid_num_r();
 134
 135         return 0;
 136 }
 137
 138 /*
 139  * Routine: set_muxconf_regs
 140  * Description: Setting up the configuration Mux registers specific to the
 141  *              hardware. Many pins need to be moved from protect to primary
 142  *              mode.
 143  */
 144 static void cm_t3x_set_common_muxconf(void)
 145 {
 146         /* SDRC */
 147         MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)); /*SDRC_D0*/
 148         MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)); /*SDRC_D1*/
 149         MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)); /*SDRC_D2*/
 150         MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)); /*SDRC_D3*/
 151         MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)); /*SDRC_D4*/
 152         MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)); /*SDRC_D5*/
 153         MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)); /*SDRC_D6*/
 154         MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)); /*SDRC_D7*/
 155         MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)); /*SDRC_D8*/
 156         MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)); /*SDRC_D9*/
 157         MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)); /*SDRC_D10*/
 158         MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)); /*SDRC_D11*/
 159         MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)); /*SDRC_D12*/
 160         MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)); /*SDRC_D13*/
 161         MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)); /*SDRC_D14*/
 162         MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)); /*SDRC_D15*/
 163         MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)); /*SDRC_D16*/
 164         MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)); /*SDRC_D17*/
 165         MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)); /*SDRC_D18*/
 166         MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)); /*SDRC_D19*/
 167         MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)); /*SDRC_D20*/
 168         MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)); /*SDRC_D21*/
 169         MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)); /*SDRC_D22*/
 170         MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)); /*SDRC_D23*/
 171         MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)); /*SDRC_D24*/
 172         MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)); /*SDRC_D25*/
 173         MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)); /*SDRC_D26*/
 174         MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)); /*SDRC_D27*/
 175         MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)); /*SDRC_D28*/
 176         MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)); /*SDRC_D29*/
 177         MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)); /*SDRC_D30*/
 178         MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)); /*SDRC_D31*/
 179         MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
 180         MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
 181         MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
 182         MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
 183         MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
 184         MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
 185         MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
 186
 187         /* GPMC */
 188         MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
 189         MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
 190         MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)); /*GPMC_A3*/
 191         MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)); /*GPMC_A4*/
 192         MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)); /*GPMC_A5*/
 193         MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)); /*GPMC_A6*/
 194         MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)); /*GPMC_A7*/
 195         MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)); /*GPMC_A8*/
 196         MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)); /*GPMC_A9*/
 197         MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)); /*GPMC_A10*/
 198         MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)); /*GPMC_D0*/
 199         MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)); /*GPMC_D1*/
 200         MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)); /*GPMC_D2*/
 201         MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)); /*GPMC_D3*/
 202         MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)); /*GPMC_D4*/
 203         MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)); /*GPMC_D5*/
 204         MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)); /*GPMC_D6*/
 205         MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)); /*GPMC_D7*/
 206         MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)); /*GPMC_D8*/
 207         MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)); /*GPMC_D9*/
 208         MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)); /*GPMC_D10*/
 209         MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)); /*GPMC_D11*/
 210         MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)); /*GPMC_D12*/
 211         MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)); /*GPMC_D13*/
 212         MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)); /*GPMC_D14*/
 213         MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)); /*GPMC_D15*/
 214         MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
 215
 216         /* SB-T35 Ethernet */
 217         MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
 218
 219         /* CM-T3x Ethernet */
 220         MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
 221         MUX_VAL(CP(GPMC_CLK),           (IEN  | PTD | DIS | M4)); /*GPIO_59*/
 222         MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
 223         MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)); /*nOE*/
 224         MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)); /*nWE*/
 225         MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)); /*nBE0_CLE*/
 226         MUX_VAL(CP(GPMC_NBE1),          (IDIS | PTD | DIS | M4)); /*GPIO_61*/
 227         MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)); /*nWP*/
 228         MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)); /*WAIT0*/
 229
 230         /* DSS */
 231         MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
 232         MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
 233         MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
 234         MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
 235         MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
 236         MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
 237         MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
 238         MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
 239         MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
 240         MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
 241         MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
 242         MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
 243         MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
 244         MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
 245         MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
 246         MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
 247
 248         /* serial interface */
 249         MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)); /*UART3_RX*/
 250         MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)); /*UART3_TX*/
 251
 252         /* mUSB */
 253         MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)); /*HSUSB0_CLK*/
 254         MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)); /*HSUSB0_STP*/
 255         MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)); /*HSUSB0_DIR*/
 256         MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)); /*HSUSB0_NXT*/
 257         MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA0*/
 258         MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA1*/
 259         MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA2*/
 260         MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA3*/
 261         MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA4*/
 262         MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA5*/
 263         MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
 264         MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/
 265
 266         /* USB EHCI */
 267         MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT0*/
 268         MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT1*/
 269         MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT2*/
 270         MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT3*/
 271         MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT4*/
 272         MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT5*/
 273         MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT6*/
 274         MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT7*/
 275         MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DIR*/
 276         MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_NXT*/
 277         MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
 278         MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
 279
 280         MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT0*/
 281         MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT1*/
 282         MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT2*/
 283         MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT3*/
 284         MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT4*/
 285         MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT5*/
 286         MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT6*/
 287         MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT7*/
 288         MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DIR*/
 289         MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_NXT*/
 290         MUX_VAL(CP(ETK_D10_ES2),        (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
 291         MUX_VAL(CP(ETK_D11_ES2),        (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
 292
 293         /* SB_T35_USB_HUB_RESET_GPIO */
 294         MUX_VAL(CP(CAM_WEN),            (IDIS | PTD | DIS | M4)); /*GPIO_167*/
 295
 296         /* I2C1 */
 297         MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
 298         MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
 299         /* I2C2 */
 300         MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)); /*I2C2_SCL*/
 301         MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)); /*I2C2_SDA*/
 302         /* I2C3 */
 303         MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)); /*I2C3_SCL*/
 304         MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)); /*I2C3_SDA*/
 305
 306         /* control and debug */
 307         MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)); /*SYS_32K*/
 308         MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)); /*SYS_CLKREQ*/
 309         MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)); /*SYS_nIRQ*/
 310         MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)); /*OFF_MODE*/
 311         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)); /*CLKOUT1*/
 312         MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTU | DIS | M4)); /*green LED*/
 313         MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
 314         MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
 315         MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
 316         MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
 317
 318         /* MMC1 */
 319         MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)); /*MMC1_CLK*/
 320         MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)); /*MMC1_CMD*/
 321         MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT0*/
 322         MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
 323         MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
 324         MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
 325 }
 326
 327 static void cm_t35_set_muxconf(void)
 328 {
 329         /* DSS */
 330         MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
 331         MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
 332         MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
 333         MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
 334         MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
 335         MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
 336
 337         MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
 338         MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
 339         MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
 340         MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
 341         MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
 342         MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
 343
 344         /* MMC1 */
 345         MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT4*/
 346         MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT5*/
 347         MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT6*/
 348         MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT7*/
 349 }
 350
 351 static void cm_t3730_set_muxconf(void)
 352 {
 353         /* DSS */
 354         MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
 355         MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
 356         MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
 357         MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
 358         MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
 359         MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
 360
 361         MUX_VAL(CP(SYS_BOOT0),          (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
 362         MUX_VAL(CP(SYS_BOOT1),          (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
 363         MUX_VAL(CP(SYS_BOOT3),          (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
 364         MUX_VAL(CP(SYS_BOOT4),          (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
 365         MUX_VAL(CP(SYS_BOOT5),          (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
 366         MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
 367 }
 368
 369 void set_muxconf_regs(void)
 370 {
 371         cm_t3x_set_common_muxconf();
 372
 373         if (get_cpu_family() == CPU_OMAP34XX)
 374                 cm_t35_set_muxconf();
 375         else
 376                 cm_t3730_set_muxconf();
 377 }
 378
 379 #ifdef CONFIG_GENERIC_MMC
 380 int board_mmc_init(bd_t *bis)
 381 {
 382         return omap_mmc_init(0, 0, 0);
 383 }
 384 #endif
 385
 386 /*
 387  * Routine: setup_net_chip_gmpc
 388  * Description: Setting up the configuration GPMC registers specific to the
 389  *              Ethernet hardware.
 390  */
 391 static void setup_net_chip_gmpc(void)
 392 {
 393         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 394
 395         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
 396                               CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
 397         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
 398                               SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
 399
 400         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 401         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 402
 403         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 404         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 405
 406         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 407         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 408                 &ctrl_base->gpmc_nadv_ale);
 409 }
 410
 411 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 412 /*
 413  * Routine: reset_net_chip
 414  * Description: reset the Ethernet controller via TPS65930 GPIO
 415  */
 416 static void reset_net_chip(void)
 417 {
 418         /* Set GPIO1 of TPS65930 as output */
 419         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 420                                 TWL4030_BASEADD_GPIO + 0x03);
 421         /* Send a pulse on the GPIO pin */
 422         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 423                                 TWL4030_BASEADD_GPIO + 0x0C);
 424         udelay(1);
 425         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 426                                 TWL4030_BASEADD_GPIO + 0x09);
 427         mdelay(40);
 428         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 429                                 TWL4030_BASEADD_GPIO + 0x0C);
 430         mdelay(1);
 431 }
 432 #else
 433 static inline void reset_net_chip(void) {}
 434 #endif
 435
 436 #ifdef CONFIG_SMC911X
 437 /*
 438  * Routine: handle_mac_address
 439  * Description: prepare MAC address for on-board Ethernet.
 440  */
 441 static int handle_mac_address(void)
 442 {
 443         unsigned char enetaddr[6];
 444         int rc;
 445
 446         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 447         if (rc)
 448                 return 0;
 449
 450         rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
 451         if (rc)
 452                 return rc;
 453
 454         if (!is_valid_ether_addr(enetaddr))
 455                 return -1;
 456
 457         return eth_setenv_enetaddr("ethaddr", enetaddr);
 458 }
 459
 460
 461 /*
 462  * Routine: board_eth_init
 463  * Description: initialize module and base-board Ethernet chips
 464  */
 465 int board_eth_init(bd_t *bis)
 466 {
 467         int rc = 0, rc1 = 0;
 468
 469         setup_net_chip_gmpc();
 470         reset_net_chip();
 471
 472         rc1 = handle_mac_address();
 473         if (rc1)
 474                 printf("No MAC address found! ");
 475
 476         rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
 477         if (rc1 > 0)
 478                 rc++;
 479
 480         rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
 481         if (rc1 > 0)
 482                 rc++;
 483
 484         return rc;
 485 }
 486 #endif
 487
 488 void __weak get_board_serial(struct tag_serialnr *serialnr)
 489 {
 490         /*
 491          * This corresponds to what happens when we can communicate with the
 492          * eeprom but don't get a valid board serial value.
 493          */
 494         serialnr->low = 0;
 495         serialnr->high = 0;
 496 };
 497
 498 #ifdef CONFIG_USB_EHCI_OMAP
 499 struct omap_usbhs_board_data usbhs_bdata = {
 500         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 501         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 502         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 503 };
 504
 505 #define SB_T35_USB_HUB_RESET_GPIO       167
 506 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 507 {
 508         u8 val;
 509         int offset;
 510
 511         if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
 512                 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
 513                                 SB_T35_USB_HUB_RESET_GPIO);
 514                 return -1;
 515         }
 516
 517         gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
 518         udelay(10);
 519         gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
 520         udelay(1000);
 521
 522         offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
 523         twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
 524         /* Set GPIO6 and GPIO7 of TPS65930 as output */
 525         val |= 0xC0;
 526         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
 527         offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
 528         /* Take both PHYs out of reset */
 529         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
 530         udelay(1);
 531
 532         return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
 533 }
 534
 535 int ehci_hcd_stop(void)
 536 {
 537         return omap_ehci_hcd_stop();
 538 }
 539
 540 #endif /* CONFIG_USB_EHCI_OMAP */